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Group-IV alloy semiconductor materials are much attractive for photovoltaic application, as those realizes multijunction photovoltaic with multi-heterostructure like group-III-V compound semiconductors [1]. In addition, group-IV alloy materials are expected to be familiar to Si integrated electronics. Ge1–x–ySixSny is one of candidate materials suitable for multijunction photovoltaic, since ternary alloy semiconductor provides energy band design independent on the lattice constant. The energy band gap of Ge1–x–ySixSny can be controlled from 0.66 eV to 1.0 eV with the epitaxial layer whose lattice is matching to Ge substrate. We previously reported the epitaxial growth of Ge1–x–ySixSny layers and also investigated the crystalline and electronic properties of them [2, 3]. However, the junction properties of Ge1–x–ySixSny/Ge heterostructure have not been well understood and it is necessary to clarify the crystalline and electronic properties of group-IV ternary alloy hetero junctions. In this study, we examined the crystal growth of pseudomorphic epitaxial layers of Ge1–x–ySixSny ternary alloy on Ge(001) substrates to form heterojunction structure for photovoltaic application. We also investigated the electronic and optoelectronic properties of these Ge1–x–ySixSny/n-Ge heterojunction diodes. Substrate used was n-type Ge(001) wafer. After chemical cleaning of substrate, a 200 nm-thick undoped Ge1–x–ySixSny layer was grown at 150–350 °C on substrate using molecular beam epitaxy system in ultrahigh vacuum chamber. Ge and Sn were deposited using Knudsen cells and Si was done using electron gun evaporation. Then, we prepared a mesa-shaped structure with wet etching. A 300 nm-thick SiO2 layer was deposited with coating of spin-on-glass and annealing at 450 °C. Finally, an Al electrode was prepared on contact holes to form heterojunction diode structure. We confirmed the crystalline structure of epitaxial layers with X-ray diffraction reciprocal space mapping. A Ge1–x–ySixSny layer with a high Sn content of 12% can be prepared with lattice matching epitaxy on Ge at a low temperature below 250 °C. It is also found that the small misfit between Ge1–x–ySixSny and Ge effectively impacts on the high crystalline quality and high thermal stability of substitutional Sn atoms in Ge matrix. Absorption spectroscopy and current-voltage characteristics of undoped Ge1–x–ySixSny/n-Ge heterojunction diodes were also performed. We observed good rectifying property of the diodes meaning that the majority carrier of these undoped Ge1–x–ySixSny ternary alloy layers is hole unintentionally generated due to defects. We also found the extension of the energy band gap of Ge1–x–ySixSny layer with Si and Sn contents. Photovoltaic property of Ge1–x–ySixSny/Ge heterojunction diodes were also measured. We can see the increasing of the open circuit voltage, Voc from 0.08 to 0.12 V for undoped Ge/n-Ge to undoped Ge0.54Si0.36Sn0.10/Ge heterojunction photovoltaic cell structure, which indicates the enhancement of Voc with increasing the energy bandgap of epitaxial layer. We also achieved the improvement of Voc by 0.14 V with 500 °C-annealing in hydrogen (H2) ambient, which suggests the annihilation or termination of point defect in the heterojunction structure. In conclusions, heterojunction structure with Ge1–x–ySixSny ternary alloy semiconductor layer provides the energy band engineering for photovoltaic applications. Understanding and controlling the defect properties in epitaxial growth and heterojunction formation should be key factors for the enhancement of performance of group-IV multijunction photovoltaic. References [1] S. Asaba et al., in Ext. Abstra. of Int. Conf. on Solid State Devices and Materials (SSDM2013), pp. 1172-1173, Fukuoka, Japan, Sept. 2013. [2] T. Asano et al., Solid State Electronics 110, 49 (2015). [3] T. Yamaha et al., Appl. Phys. Lett. 108, 061909 (2016).

Toward creation of a direct gap group-IV semiconductor, we have developed a new method of growing Si1-xSnx layers with various Sn content including a very high Sn content around 40% by using solid phase epitaxy. Crystallographic analyses indicate that grown Si1−xSnx layers are nearly lattice-matched to the substrates, specifically, the substitutional Sn contents of ~20 and ~40% are achieved for case of growth on (001)-oriented Ge and InP substrates, respectively. Although band structure of the Si0.6Sn0.4 layers grown on InP is still indirect band gap, the difference between the indirect and direct band gap energies decreases from 3.01 (Si) to 0.14 eV (Si0.6Sn0.4) following Sn substitution.

We examined the formation of locally strained Ge nanostructures sandwiched between Ge1−x Sn x stressors using metal-organic chemical vapor deposition method. We have investigated the microscopic local strain and stress in the Ge/Ge1−x Sn x heterostructures using synchrotron microdiffraction and finite element method calculation. The microdiffraction measurement for an asymmetric lattice plane enables directly quantitative evaluation of the strain value of an individual Ge fine line structure with a few tens of nanometers width. An in-plane compressive strain value of 0.9% is achieved for a 30 nm-width Ge line with Ge1−x Sn x stressors, which corresponds to a compressive stress of 1.2 GPa.

Thermoelectric generator has attracted attention because of their ability to recover waste heat with converting it to electricity. The energy conversion efficiency is related to the thermoelectric figure of merit Z, expressed as Z = S2σ/κ, where σ and κ is electrical and thermal conductivities, respectively, and S is the Seebeck coefficient. Consequently, in order to achieve a high Z value, the material must possess a unique combination of electrical and thermal properties, i.e., metal-like high σ and glass-like low κ. In our previous study on electrical and thermal properties of a Ga-doped Ge0.929Sn0.071 thin film grown on Ge(001), it was revealed that simultaneous realization of a high σ (6.5×102 S/cm) and a low κ (2.0 Wm-1K-1) by the incorporations of the Sn and Ga atoms into Ge matrix [1]. Very recently, Uchida et al. [2] has reported heat transport property of polycrystalline GeSn (poly-GeSn) films on SiO2, together with the carrier transport property, to assess self-heating effect of the poly-GeSn channel thin-film transistors. Here, they showed a relatively lower κ of 5–9 Wm-1K-1 for poly-Ge1-xSnx (x-1K-1) [3]. These results are quite beneficial in the field of Ge-based thermoelectric generator. However, the thermoelectric properties of GeSn films have not been entirely understood. It is therefore, in the present study, we aim to reveal the thermoelectric properties of the Ge-rich poly-Ge1-xSnx films grown by solid phase crystallization. Doping effects in poly-Ge1-xSnxon the thermoelectric properties will be discussed. Acknowledgments The authors would like to thank Drs. Hiroshi Onoda and Yoshiki Nakashima of Nissin Ion Equipment Co., Ltd. for providing the opportunity to use ion implanters. This work was partially supported by a Grant-in-Aid for Scientific Research (S) (Grant No. 26220605) of the JSPS and PRESTO from JST. References [1] M. Kurosawa, M. Fukuda, K. Takahashi, M. Sakashita, O. Nakatsuka, and S. Zaima, “Thermophysical characterizations of Ge1-xSnx epitaxial layers aiming for thermoelectric device,” 9th International Conference on Silicon Epitaxy and Heterostructures (ICSI-9), Montreal, Canada, 4.4.1, May 21, 2015. [2] N. Uchida, T. Maeda, R. R. Lieten, S. Okajima, Y. Ohishi, R. Takase, M. Ishimaru, and J.-P. Locquet, Appl. Phys. Lett. 107, 232105 (2015). [3] C. J. Glassbrenner and G. A. Slack, Phys. Rev. 134, A1058 (1964).

Research and development of GeSn and related group-IV semiconductor materials have been widely extended in recent years for not only electronic transistors but also various optoelectronic applications [1,2]. Design and engineering of the energy band structure of group-IV semiconductor materials are swiftly blossoming with establishing the crystal growth technology of GeSn and related materials. We have successively developed the crystalline growth technology of GeSn and GeSiSn thin films on various substrates mainly by using molecular beam epitaxy [1-7]. Recently, we also achieved the epitaxial growth of GeSn layer by using metal organic chemical vapor deposition method [8]. In this presentation, we will report our recent achievements of our study for the crystalline growth and electronic properties including energy band structure of GeSn and related group-IV materials. Controlling the composition of elements and the strain structure of the group-IV semiconductor alloys promises prospective energy band engineering technology. Increasing in the Sn content over about 10% or tensile strain over about 1% achieve the indirect-to-direct crossover, which is a strong driving force of the optical applications of GeSn material. In addition, we recently achieved the formation of polycrystalline SiSn thin layers with a very high Sn content of 20%, and demonstrated that the direct bandgap decreases to 1.05 eV with Si-Sn alloying, which is just 0.22 eV higher than the indirect bandgap of the poly-SiSn even by using Si matrix material [9]. Also, the ternary alloy GeSiSn promises the control of the energy band structure independently on the lattice constant by changing each content of three elements. We found that unstrained GeSiSn/Ge heterostructure realizes a type-I energy band alignment without using strain structure, that promises various electronic and optoelectronic applications [10]. We will demonstrate the experimental results of the energy band engineering with GeSn and related materials. The energy band engineering also provides controlling technology of the electronic property at the interface such as metal/Ge contact. Recently, we found that the Sn/Ge or GeSn/Ge contacts effectively reduces the Schottky barrier height at the metal/n-Ge interface [11,12]. In our presentation, we will also discuss the influence of the energy band structure on the interface properties for Ge and GeSn. This work was partially supported by Grant-in-Aid for Scientific Researches of the JSPS and the JSPS Core-to-Core Program, A. Advanced Research Networks. References [1] S. Zaima, Jpn. J. Appl. Phys. 52, 030001 (2013). [2] S. Zaima et al., Sci. Technol. Adv. Mater., submitted. [3] S. Zaima et al., ECS Trans. 41, 231 (2011). [4] S. Zaima et al., ECS Trans. 50, 897 (2012). [5] O. Nakatsuka et al., ECS Trans. 58, 149 (2013). [6] S. Zaima et al. ECS Trans. 64, 147 (2014). [7] O. Nakatsuka et al. ECS Trans. 64, 793 (2014). [8] Y. Inuzuka et al., ECS Solid State Lett., submitted. [9] M. Kurosawa et al., Appl. Phys. Lett. 106, 171908 (2015). [10] T. Yamaha et al., in Abstr. of ICSI-9, Montreal, Canada, May, 2015. [11] Suzuki et al., Jpn. J. Appl. Phys. 53, 04EA06 (2014). [12] A. Suzuki et al., SSDM2015, Hokkaido, Japan, Sept. 2015, to be submitted.

Sn-related group-IV semiconductor such as Ge1-xSnx and Ge1-x-ySixSny are one of the most attractive materials for Si nanoelectronic applications. Ge1-xSnx alloy is expected to be a stressor for strain-engineering material of Ge devices [1,2]. In addition, Ge1-xSnx with a Sn content approximately higher than 10% is a direct transition semiconductor material, and that allows us to use electrons of the conduction band at the G-point for electronic applications. Those promise to improve on the performance of Ge devices and to introduce new functions of transistors, light receiving/emitting element, photovoltaic cells, etcon Si nanoelectronics. In these several years, we have investigated the crystal growth of Ge1-xSnx and Ge1-x-ySixSny thin films and the crystalline and electronic properties [2-5]. In addition, we have recently investigated and developed Ge1-xSnx technologies for electronic applications; those are (1) crystalline and electronic properties of defects, (2) strain and energy band engineering, (3) impurity doping, (4) metal/insulator/semiconductor (MOS) gate-stack structure, (5) metal/semiconductor (MS) contacts. In this report, we will present recent achievements in our research of Ge1-xSnxtechnology. Defects in Ge1-xSnx alloy It is known that a vacancy in Ge is an acceptor-like defect and undoped Ge grown at low temperature often shows p-type conduction. The formation and behavior of defects in Ge1-xSnx alloy should be essentially understood for electronic and optoelectronic applications. We investigated the influence of Sn on the electronic properties of Ge1-xSnx by preparing metal/Ge Schottky diodes with Sn-ion implantation and measuring the deep-level transient spectroscopy (DLTS) [6]. The Sn-ion implantation with a dose of 1014 cm-2 and a acceleration voltage of 370 kV generates acceptor-like defects in Ge substrate with a hole-concentration of 1017 cm-3, and these defects is hardly annihilated even after annealing as high as 500 °C. Also, we found by DLTS measurement that the concentration of vacancy-related deep-level defects can be reduced with Sn-implantation, although some additional Sn-related defects are formed. Oxidation of Ge1-xSnx and gate-stack structures It is essentially important to investigate the oxidation behavior of Ge1-xSnx for engineering the Ge1-xSnx gate-stacks. We previously reported the electrical properties of Al2O3/Ge1-xSnx/Ge MOS capacitors [7]. Recently, we examined the oxidation of Ge1-xSnx layers pseudomorphically grown on Ge substrate and investigated the behavior of Sn segregation during oxidation [8]. We found the surface segregation of Sn atoms near the Ge1-xSnx surface by oxidation at 400 °C. Thermal oxidation of Ge1-xSnx causes the Sn diffusion from Ge1-xSnx and the formation of Sn oxide on the surface. The capacitance-voltage measurement of Al/Al2O3/Ge1-xSnx capacitors also reveals that the oxidation of Ge1-xSnx increases in the concentration of holes unintentionally generated from acceptor-like defects in Ge1-xSnx layers. We need to develop the defect control technology for gate-stack formation of Ge1-xSnxwith considering Sn behavior during oxidation and annealing. Metal/Ge1-xSnx contact formation The formation of metal/Ge contacts with low parasitic resistance is required to improve on the performance of Ge devices. We examined the formation of NiGe/Ge1-xSnx contacts with germanidation processes of Ni/Ge1-xSnx system [9]. A single layer of Ni mono germanostanane, Ni(Ge1-xSnx) can be formed by annealing Ni/Ge1-xSnx/Ge samples at 350~550 °C. We found that the Sn content in Ni(Ge1-xSnx) increases with the Sn content of Ge1-xSnx and that decreases with the annealing temperature due to the Sn segregation from Ni(Ge1-xSnx). Smooth surface of Ni(Ge1-xSnx) layers on Ge1-xSnx can be successfully obtained with annealing at as low as 350 °C even for a Sn content as high as 6.5%, although the agglomeration of Ni(Ge1-xSnx) grains severely occurs after annealing at higher than 550°C. In summary, the incorporation of Sn promises additional key factors for engineering strain, energy band structure, interface, and defects in Ge nanoelectronics. We need to develop the crystal growth, process, and device technologies based on deeply understanding the crystalline and electronic properties of Sn-related group-IV semiconductor materials. Acknowledgements This work was partially supported by a Grant-in-Aid for Specially Promoted Research of MEXT and an ALCA Program of JST in Japan. References [1] S. Takeuchi et al., APL 92, 231916 (2008). [2] S. Takeuchi et al. ECS Trans. 33, 529 (2010). [3] O. Nakatsuka et al. ECS Trans. 58, 149 (2013). [4] S. Zaima et al., ECS Trans. 50, 897 (2012). [5] S. Zaima et al., ECS Trans. 41, 231 (2011). [6] T. Arahira et al., Ext. Abstr. of Int. Conf. on SSDM2013, p. 620, 2013. [7] C. Merckling et al., Appl. Phys. Lett. 98, 192110 (2011). [8] K. Kato et al., in Abstr. of IWDTF2013, p. 99, 2013. [9] T. Nishimura et al., Solid-State Electronics 60, 46 (2011).

Ge1-xSnx alloy thin films are much attractive for not only improving in Si nanoelectronics but also introducing new functional applications. High Sn content Ge1-xSnx promises to be direct semiconductor which promises the optoelectronic applications. We need to control the Sn precipitation, strain, dislocations, and point defects in Ge1-xSnx epitaxial layers for practical electronic and optoelectronic applications. We have been developing the growth technique of Ge1-xSnx epitaxial layers on various Si, Ge, Si on insulator (SOI), and Ge on insulator (GOI) substrates with molecular beam epitaxy (MBE) method [1-3]. Recently, we achieved high crystallinity Ge1-xSnx layers with a high Sn content up to 12% by lowering the growth temperature and controlling the lattice mismatch and strain [4]. In addition, the orientation of substrate has to be considered to improve on the crystalline quality and performance of Ge1-xSnx devices, because the substrate orientation significantly influence on the strain structure, defect structure, propagation of dislocations, energy band structures, and effective mass. The development of global- and local-growth technology of Ge1-xSnxepitaxial layers on not only Si(001) but also various substrates with (110) and/or (111) orientations is essentially required for various applications. Ge1-xSnx epitaxial growth on (110) and (111) substrates We examined the epitaxial growth of Ge1-xSnx layers on (110) and (111) Ge substrates [5-8]. We found that introducing Sn with a content as low as 2% into Ge is effective to reduce staking faults and twin defects in Ge epitaxial layers on (110) substrates even with the low-temperature growth of 150°C. We also found that the strain relaxation of Ge1-xSnxon (110) and (111) substrates takes place preferentially with a smaller Sn content than that grown on (001) substrate, that is attributed to the surface orientation dependence of the elastic modulus of epitaxial layers. The Sn incorporation into Ge also improves on the crystalline quality of epitaxial layers prepared with low-temperature MBE on Si(110) substrate [9]. Formation of twin defects in Ge epitaxial layers on Si(110) can be drastically suppressed by the incorporation of Sn with a content of 2%. The propagation of misfit dislocations can be effectively enhanced during the post deposition annealing by suppressing the formation of twin defects. Local growth of Ge1-xSnx epitaxial layers We examined the formation of locally strained Ge1-xSnx/Ge fine structure and characterized the microscopic local strain structures by using X-ray microdiffraction method [10]. The local growth of Ge1-xSnx with a Sn content of 6.5% on fine-structure-patterned-Ge is achieved with low-temperature MBE. The concentration of local stress in embedded Ge1-xSnx layer causes the degradation of crystallinity with tilting of the lattice plane and Sn precipitation. We can directly measure the individual local strain in Ge sandwiched with Ge1-xSnxlocal stressor by microdiffraction. We demonstrate increasing in the in-plane strain with shrinking the Ge width and increasing the Sn content. The maximum in-plane compressive strain is estimated to be 1.4% for a width of 25 nm. In the presentation, we will also talk about some electronic and optical properties of high Sn content Ge1-xSnx epitaxial layers and introduce some recent achievement in the epitaxial growth of Sn-related ternary alloys such as Ge1-x-ySixSny. Acknowledgements This work was partially supported by a Grant-in-Aid for Specially Promoted Research of MEXT, the JSPS through the FIRST Program, and the ALCA program from JST in Japan. The microdiffraction measurement was performed at SPring-8 with the approval of general proposals (No. 2013A1682 and No. 2013B1779/BL13XU). References [1] S. Zaima et al., ECS Trans. 41, 231 (2011). [2] S. Zaima et al., ECS Trans. 50, 897 (2012). [3] O. Nakatsuka et al., ECS Trans. 58, 149 (2013). [4] Y. Shimura et al., ECS Trans. 33, 529 (2010). [5] Y. Shimura et al., Appl. Phys. Express 5, 015501 (2012). [6] T. Asano et al., Thin Solid Films 531, 504 (2013). [7] T. Asano et al., Solid-State Electron. 83, 71 (2013). [8] T. Asano et al., Thin Solid Films, 557, 159 (2014). [9] S. Kidowaki et al., in Ext. Abstra of SSDM2012, p. 1043, Fukuoka, Japan, Sept., 2013. [10] S. Ike et al., Thin Solid Films, 557, 164 (2014).

Group-IV element semiconductor materials, germanium tin (GeSn) and germanium silicon tin (SiGeSn) have attracted much attention for electronic and optoelectronic applications because of those unique properties; direct transition with a high Sn content, higher carrier mobility than Si and Ge, low growth temperature, and low thermal conductivity [1-3]. GeSiSn realizes the control of energy band structure independently on the lattice constant of alloy. Also, GeSiSn/Ge(Sn) heterostructure provides a type-I energy band alignment with sufficiently large energy band offsets at both conduction and valence band edges simultaneously with the lattice constant matching. That promises an effective carrier confinement structure for quantum well laser and high electron mobility transistor. On the other hand, the development of crystal growth technology for GeSn-related materials is still a challenge, since the thermal equilibrium solid solubilities of Sn in Ge and Si are very low compared to a required substitutional Sn content higher than 10%. It is necessary to understand the behavior of Sn atoms in the epitaxial growth and post deposition process and to control the stability of Sn at substitutional site in GeSn-related epitaxial layers. In addition, the development of interface engineering technology is required for not only GeSn/GeSiSn heterostructure but also metal/GeSn and insulator/GeSn structures for nano-scale electronic devices. Recently, we examined the formation of double heterostructure with GeSiSn/GeSn/GeSiSn layers on Ge substrate using a molecular beam epitaxy (MBE) system [4]. The hard x-ray photoelectron spectroscopy measurement reveals that the sufficiently large energy band offset can be formed at the valence band edge of its GeSiSn/GeSn interface. We also demonstrated that the carrier confinement with this GeSiSn/GeSn/GeSiSn double heterostructure effectively improved the efficiency of photoluminescence (PL) [5]. However, we also found that the crystalline quality of the heteroepitaxial layers significantly influence on the PL intensity and it is necessary to understand the key factor of the crystallinity of heterostructures in order to reduce the dislocation and point defect in the epitaxial layers. For the low temperature growth of GeSn and GeSiSn hetero-epitaxial layers on Ge using MBE, a biaxial compressive strain is often induced into the epitaxial layers, as a GeSn or GeSiSn layer is often grown pseudomorphically on Ge substrate. The compressive strain of GeSn is a disadvantage for enhancing the luminescence efficiency because a higher Sn content is generally required to the indirect-to-direct crossover for a compressively strained GeSn compared to the unstrained case. In order to improve the efficiency of luminescence, it is important not only to enhance the Sn content but also to control the strain structure. We developed the strain relaxation technology of GeSn epitaxial layer on a substrate or buffer layer. We found that the ion implantation into Ge substrate effectively enhance the strain relaxation of GeSn layer. The degree of strain relaxation achieved over 90% for the GeSn layer grown on the Ge substrate after the boron ion implantation with 3x1014 cm-2, while the compressively strained GeSn layer was pseudomorphically grown on the Ge substrate without the ion implantation. This work was partly supported with a Grant-in-Aid for Scientific Research (S) (No. 26220605) and the Core-to-Core Program ICRC-ACP4ULSI from the JSPS. References [1] S. Zaima, O. Nakatsuka, N. Taoka, M. Kuorsawa, W. Takeuchi, and M. Sakashita, Sci. Technol. Adv. Mater. 16, 043502 (2015). [2] S.Wirths, D.Buca, and S.Mantl, Prog. Crystal Growth Character. Mater. 62, 1 (2016) [3] M. Kurosawa, Y. Imai, T. Iwahashi, K. Takahashi, M. Sakashita, O. Nakatsuka, and S. Zaima, ECS Trans. 86, 311 (2018). [4] M. Fukuda, T. Yamaha, T. Asano, S. Fujinami, Y. Shimura, M. Kurosawa, O. Nakatsuka, and S. Zaima, Mater. Sci. Semicond. Proc. 70, 156 (2017). [5] M. Fukuda, K. Watanabe, M. Sakashita, M. Kurosawa, O. Nakatsuka, and S. Zaima, Semicond. Sci. Technol. 32, 104008 (2017).

We have investigated the correlation between interface state density (D it) and interface structure of Al2O3/Ge with post thermal oxidation. D it around the midgap of Ge decreases with increment of oxidation temperature and saturates at more than 500°C. It is clarified that the AlGeO formation near the Al2O3/Ge interface occurs with increase in oxidation temperature. At more than 500°C, a stable Al6Ge2O13 is formed. On the other hand, GeO2 formation which is limited by the oxygen diffusion in the Al2O3 layer mainly occurred on the Al2O3 surface. Considering that Al2O3 layer prevents the oxygen diffusion compared to GeO2 layer, decomposition of GeO2 is dominant at Al2O3/Ge interface and GeO2 should be hardly formed at Al2O3/Ge interface. Therefore, AlGeO dominantly exists near the Al2O3/Ge interface and it surely lead to reduction of D it.

In this study, we have examined the local growth of Ge1 − x Sn x heteroepitaxial layers on micrometer-scale-patterned Ge substrates with molecular beam epitaxy method. We have investigated the strain relaxation behavior and microscopic local strain structure in both Ge and Ge1 − x Sn x by using x-ray microdiffraction and finite element method calculation. We found that the anisotropic strain relaxation of embedded Ge1 − x Sn x layers preferentially occurs along the direction which is perpendicular to the stripe line. Microdiffraction method revealed that the elastic strain relaxation of the embedded Ge1 − x Sn x layer occurs near the edge region. We demonstrated that the uniaxial compressive strain of 0.2% is locally induced in Ge with Ge1 − x Sn x stressors.

We have examined the heteroepitaxial growth of Ge1-xSnx and Ge1-x-ySixSny layers and investigated the crystalline and electrical properties of these Sn-related group-IV material thin films. We achieved the epitaxial growth of Ge1-xSnx on Ge(110) with suppressing the formation of twin defects. Ge1-x-ySixSny layers on Ge substrates show high thermal robustness without Sn precipitation even after annealing at 600°C. We also found that the incorporation of 0.1%-Sn and H2-annealing are effective to reduce the unintentional generation of holes due to the vacancy defects.

We have examined the epitaxial growth of Ge1-x-ySixSny layers on Ge substrates with a Sn content of 3~15% with low temperature molecular beam epitaxy method. The Ge1-x-ySixSny layers are psuedomorphically grown on Ge substrates with high crystalline quality. The surface morphology of the Ge1-x-ySixSny layers with a Sn content below 7% shows very flat and uniform, although surface roughening occurs in the sample with a Sn content as high as 15% provably due to the Sn precipitation. We also roughly estimated the energy band structure with liner approximation calculation. The energy bandgap of Ge1-x-ySixSny alloy prepared in this study is expected to be 0.8~1.0 eV at the L or X point.

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the basic semiconductor equations. We developed a numerical formalism based on a drift-diffusion model including a trap level and applied it to typical GeSn-based heterostructures by focusing on the electrical response under small-signal alternating current regime. The results demonstrate that our method provides an access to both microscopic and macroscopic properties, and thereon, to a physical interpretation of the electrical characteristics of GeSn-based structures by linking measurable quantities to micro-scale variations in the structures.

We have investigated the epitaxial growth of Ge1-xSnx layers with a high Sn content over 10% and their optical properties. We examined the growth of Ge1-xSnx epitaxial layers with Sn contents over 10% on Ge and InP substrates. We have achieved the epitaxial growth of a Ge1-xSnx layer with a 27%-Sn content which is much higher than a thermoequilibrium solid solubility of Sn in Ge. We have also revealed the Sn content dependence of the direct energy bandgap for Ge1-xSnx layers with wide Sn contents ranging from 5% to 27%.

In this paper, we reports our recent studies of the electrical and crystalline properties of heteroepitaxial Ge1-xSnx layers with various Sn content of 0~25%. We examined Ga-doping in strained Ge1-xSnx layers for developing source/drain stressor in CMOS applications and investigated the effect of Sn on the doping profile. The impact of Sn on carrier properties has been also studied with the Hall measurement of Ge1-xSnx/SOI structures. Also, we achieved the epitaxial growth of Ge1-xSnx layers with a Sn content as high as 25% on InP considering misfit between the epitaxial layer and substrate.

We have investigated the dependence of strain relaxation behavior of Ge1-xSnx layers on the misfit strain at the interface between Ge1-xSnx layers and substrates. When the large misfit strain was induced, surface roughening and degradation of the crystallinity occurred during the Ge1-xSnx growth. We found that the universal dependency of the strain relaxation behavior, which is independent on kinds of substrates. As a result, the Ge1-xSnx layer having a Sn content of 12.3% was achieved, which has a potential to induce a tensile strain of 1.28% in a Ge layer.

In this paper, we propose the fabrication of whole strained Ge complementary metal-oxide-semiconductor (CMOS) with Ge1-xSnx materials as embedded stressors to outperform the state-of-the-art strained Si CMOS. Ge1-xSnx materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Compatibility of Ge1-xSnx (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation, in situ Ga doping, and Ni(Ge1-ySny) formation) is characterized. A low thermal budget has been determined for those processes on Ge1-xSnx alloys: temperatures must be lower than 600{degree sign}C for B activation and lower than 450{degree sign}C for Ni(Ge1-ySny) formation.

Sequential integration of thermoelectric generators (TEGs) on a silicon wafer is essential for next-generation electronics such as internet-of-things sensing network as an energy-harvesting device. A guideline of thermoelectric performance is defined as dimensionless figure of merit, zT=S2 σT/κ, which is calculated from Seebeck coefficient (S), electrical conductivity (σ), thermal conductivity (κ), and absolute temperature (T). Germanium tin (Ge1 − x Sn x ) binary alloys theoretically possess a low κ [1] and a high σ [2], implying that Ge1 − x Sn x enables high-performance TEGs. In our previous study on the thermal conductivity of Ge1 − x Sn x epitaxial layer grown on (001)-oriented Ge [3], it was revealed that a very low κ of 2.0 W/mK was obtained for a Ga-doped Ge0.929Sn0.071 epitaxial layer. The value is at least 77 and 30 times lower than that for bulk-Si (156 W/mK) and bulk-Ge (60 W/mK) [4], respectively, and same order with that for amorphous Si (1−2 W/mK) [5]. However, thermoelectric properties of the epitaxial layers could not be clarified because the underlying substrates were not electrical insulators. It is therefore, in this study, we aim to reveal thermoelectric properties of Ge1 − x Sn x epitaxial layers with a wide range of Sn contents grown by low-temperature molecular beam epitaxy. Here, semi-insulating wafers of Si, GaAs, and InP were used as a substrate in order to isolate electrically from the substrates. Combined with the results for the polycrystalline films, we will establish a guideline for enhancing the zT value in narrow band-gap group-IV materials. Acknowledgments: This work was partially supported by Grants-in-Aid for Scientific Research (S) (Grant No. 26220605) and Young Scientists (A) (Grant No. 17H04919) from JSPS in Japan and PRESTO (Grant No. JPMJPR15R2) from JST in Japan. References: [1] S. N. Khatami and Z. Aksamiji, Phys. Rev. Appl. 6, 014015 (2016). [2] K. L. Low et al., J. Appl. Phys. 112, 103715 (2012). [3] M. Kurosawa et al., “Thermophysical characterizations of Ge1 −x Sn x epitaxial layers aiming for thermoelectric device,” 9th International Conference on Silicon Epitaxy and Hetero-structures (ICSI-9), Montreal, Canada, 4.4.1, May 21, (2015). [4] C. J. Glassbrenner and G. A. Slack, Phys. Rev. 134, A1058 (1964). [5] D. G. Cahill et al., J. Vac. Sci. Technol. A 7, 1259 (1989).

Silicon ultralarge-scale integrated circuits (ULSIs) are now being faced to various physical and technological limits on the scaling. In order to realize future nano-scaled complementary metal-oxidesemiconductor (CMOS) devices, the development of new materials and new functions to integrate on Si platforms and the control of variability and fluctuations of device characteristics is important.

New structures and materials alternative to conventional bulk-Si(001) substrates are now under consideration for their application to CMOS channel layers on a Si platform. However, mismatch of lattice parameter between the alternative channel material and the Si substrate inevitably causes defect introduction which is one of crucial issues when implementing the formation of channels on Si. In this work, we perform interface and defect engineering for group IV semiconductor materials; Si with hybrid crystal orientation, Ge, and Sn. Engineered channel crystals formed with the wafer direct bonding and heteroepitaxy technologies are characterized in terms of crystalline quality and strain.

We report silicide and germanide technology for ohmic contacts and metal gates of MOSFET applications. We have investigated control of crystalline and electrical properties of NiSi/Si contacts by the incorporation of third elements. Thermal stability and electrical properties of NiSi/Si contacts are effectively controlled by the incorporation of Ge and C. We have also systematically investigated the work function and the resistivity of various Ni and Pt germanides as metal gate materials. The low resistivity and tunable work function of these germanides and silcides are desirable for future CMOS devices.

Introduction Using Ge as a channel material in the metal-oxidesemiconductor field effect transistor (MOSFET) is one of promising solutions for problems associated with physical limitations in the progressive device miniaturization. Since Ge has higher carrier mobility than that in Si, both higher drive current and lower power consumption in the operation of MOSFETs are simultaneously anticipated. However, process technologies based on Ge are immature, and the passivation and the insulator film formation on the Ge surface are not established yet. In this work, we use in situ scanning tunneling microscopy (STM) to investigate the reaction of oxygen with clean Ge(001) surfaces. Oxidation and etching processes depending on the substrate temperature and the oxygen partial pressure are characterized on an atomic scale.

Integration of near-infrared light source/detector on Si chips has long been expected to achieve on-chip and/or chip-to-chip optical interconnectivity. However, the indirect band gap of group-IV semiconductor such as Si and Ge remains a challenge especially for photoemission. Although the direct band gap in Si is 3.1 eV above the indirect band gap and the solid solubility limit of Sn in Si is extremely low (0.1%), the Si1-xSnx alloys must have a direct band gap for a sufficiently high Sn content, as for Ge1-xSnx. From a device perspective, an experimental demonstration of the band gap is desired. However, the relevant optical property for Si1-xSnxhas to date not been obtained. Under such a background, the present paper reports our recent progress in advanced low-temperature crystallizations for Si1-xSnx (x: 0–0.4) thin films on various substrates (insulators, Si, Ge, InP, etc.). Composition analyses indicate that approximately 20% of the Sn atoms are substituted into the polycrystalline (or epitaxial) thin films grown on an insulator (or Ge(001)) after annealing at 220 oC for 5 h. By using InP(001) substrates, the Sn content could raise up to about 40%. Comparison of the band gap with the calculated values and new applications, such as Si1-xSnx-source tunnel field effect transistors and thermoelectric generator, will be discussed. Acknowledgments This work was partially supported by Grants-in-Aid for Scientific Research (S) (Grant No. 26220605) and Young Scientists (A) (Grant No. 17H04919) from JSPS in Japan and PRESTO (Grant No. JPMJPR15R2) from JST in Japan.

The strain engineering is a promising technology not only for low-power CMOS but also for optoelectronic applications of germanium (Ge) devices compatible with the conventional silicon (Si) process technology [1]. In terms of CMOS applications, a uniaxial compressive strained Ge has drawn attention as high-mobility channel material in p-MOSFET which is expected to transcend that of conventional strained Si channel [2]. We are focusing on germanium-tin (Ge1−x Sn x ) as a source/drain (S/D) stressors to apply a uniaxial compressive strain into Ge in analogy with Si1−x Ge x S/D for strained Si channel. However, there are few reports of the local epitaxial growth of Ge1−x Sn x on patterned Ge substrate and the local strain technology of the Ge/Ge1−x Sn x heterostructures. Since the recent device dimensions of Si CMOS devices have reached the sub-100 nm scale in accordance with Moore’s law, the investigation of the microscopic crystalline and the strain structures for various next generation semiconductor materials has grown increasingly important. In this study, we experimentally characterized the local strain structure in Ge/Ge1−x Sn x fine heterostructures by using synchrotron x-ray microdiffraction method [3,4]. We prepared Ge stripe structures with various line widths (25–100 nm) sandwiched with Ge1−x Sn x stressors. Patterned Ge(001) substrate with a SiO­ 2 cap layer was formed by anisotropic wet/dry etching as lines parallel along to the direction. The pitch of a Ge stripe is 500 nm. The Ge1−x Sn x layers were grown with solid-source molecular beam epitaxy (MBE) system and metal-organic chemical vapor deposition (MOCVD) system [5]. The Sn content in the Ge1−x Sn x was 2.9–6.5%. The x-ray microdiffraction measurement was performed at the beamline BL13XU in SPring-8 to analyze the local strain distribution and crystalline structure in Ge/Ge1−x Sn x samples. A synchrotron radiation light with an energy of 8 keV (λ=0.155 nm) was used. The cross-section size of an incident x-ray microbeam was estimated to be 0.16×0.20–0.82×0.26 μm2 in preliminary experiments. Transmission electron microscope observations revealed that Ge1−x Sn x were epitaxially grown on both sides of a Ge line, while the crystalline structure of Ge1−x Sn x on SiO2 on the top of Ge line was polycrystalline. We consider that the stressors of locally grown epitaxial Ge1−x Sn x can induce a local strain into the Ge line. In order to directly characterize the in-plane strain status in strained Ge region, we examined two-dimensional reciprocal space mapping (2DRSM) around the Ge1—1—3 asymmetric Bragg reflection with step scans of the microbeam position across the Ge lines with a step of 50 nm. Three diffraction peaks related to the bulk Ge, the epitaxial Ge1−x Sn x stressors, and the strained Ge are clearly observed in 2DRSM results. The intensity of diffraction peak of the strained Ge periodically varied corresponds to the stripe pitches. The diffraction peak position of the strained Ge in 2DRSM indicates an in-plane compressive strain is induced into a Ge line sandwiched with Ge1−x Sn x stressors. From the 2DRSM results for various Ge stripe widths, an in-plane strain value can be estimated from the lattice spacing with respect to that of bulk Ge. The in-plane compressive strain value in the Ge increases with narrowing the Ge line width and increasing the Sn content in the Ge1−x Sn x stressors, which is consistent with the simulated results of finite element method calculations. For the Ge0.943Sn0.057 stressors, the in-plane compressive strains were estimated to be 0.84%, 0.46% and 0.38% for 30, 60, and 100 nm-wide Ge lines, respectively. In summary, the formation of Ge/Ge1−x Sn x fine heterostructures were achieved by MBE and MOCVD, and experimentally characterized the local strain distribution in the Ge/Ge1−x Sn x by synchrotron radiation microdiffraction method. The microdiffraction enables a quantitative analysis of strain and an investigation of local crystalline structure in sub-100 nm-scale Ge lines sandwiched with Ge1−x Sn x stressors. This work was partly supported by the JSPS through the FIRST Program initiated by the CSTP, a Grant-in-Aid for Scientific Research (S) (Grant No. 26220605) and Core-to-Core Program ICRC-ACP4ULSI from the JSPS in Japan. The synchrotron radiation experiments were performed at SPring-8 with the approval of JASRI (Nos. 2012B1783, 2013A1682, 2013B1779, 2015A1874, and 2015B1813/BL13XU). [1] S. Zaima et al., Sci. Technol. Adv. Mater. 16, 043502 (2015). [2] T. Krishnamohan et al., IEDM Proc., 899 (2008). [3] S. Takeda et al., Jpn. J. Appl. Phys. 45, L1054 (2006). [4] Y. Imai et al., AIP Conf. Proc. 1221, 30 (2010). [5] Y. Inuzuka et al., Thin Solid Films 602, 7 (2016).

Electrical properties and conduction mechanisms of leakage current of tantalum pentoxide films have been studied. films were deposited by cold wall‐type, low‐pressure chemical vapor deposition (LPCVD), and then annealed at temperatures ranging from 600° to 900°C in . The leakage current flowing through films decreases drastically following the annealing. The conduction mechanism in the films annealed below 800°C is dominated by hopping conduction, at room temperature. On the other hand, Fowler‐Nordheim tunneling conduction becomes predominant for films annealed above 850°C. The decrease in leakage current with increasing annealing temperature can be mainly explained by a reduction in the carrier density, originating from defects in the films, such as dangling bonds.

Preparation and electrical properties of tantalum pentoxide (Ta 2 O 5 ) films have been studied for the application to ultra large scale integrated circuits (ULSIs). Ta 2 O 5 films were deposited by a cold wall-type low-pressure chemical vapor deposition (LPCVD) at temperatures of 340 o -400 o C, and then annealed at temperatures ranging from 600 o to 900 o C in O 2 . It can be found that for the films grown by the present method, a high-temperature annealing is exceedingly effective for an increase in dielectric constant and a decrease in leakage current flowing through the film. Relative dielectric constants of 25-35 are achieved for the annealed Ta 2 O 5 films with the thickness above 40 nm, which are about 1.4 times larger than those reported previously

carrier mobility compared with Si. 1 Although closely related to Si, in some aspects Ge shows a quite different behavior. This should be taken into account when processing steps are developed for the production of electronic devices with active Ge layers, in which the Ge layer surfaces and interfaces will play an important role. 2 In this letter, we investigated the effect of the free (001) surface on positron annihilation spectroscopy (PAS) results, comparing Si and Ge substrates. PAS is a powerful tool for the study of vacancy-type defects in semiconductors, 3,4 e.g. in irradiated Si and Ge. Positron trapping at vacancies can be observed by the narrowing of the Doppler-broadened 511 keV annihilation γ-ray peak. By varying the incident positron energy, one can probe different sample depths in the submicron range. This method is called Doppler Broadening Spectroscopy (DBS). The so called S-parameter, extracted from DBS, corresponds to positron annihilation by the valence electrons and is sensitive to open volume defects. An increase of the S-parameter can be simply interpreted as an increase of the number of vacancy-type defects. The S-parameter obtained for an incident positron energy lower than 2 keV, however, in general differs from the one obtained for positron energies above 15 keV. Incident positrons with lower energy will indeed mainly interact with the near surface area of the sample, and will be sensitive for thin native oxide layers, surface contamination, surface roughness, surface defects, etc. The S-parameter decreases in general toward the surface for most materials due to positron diffusion toward and annihilation at the surface. 5 The present letter reports on the different behavior of Si and Ge with this respect. While in case of Si, the S-parameter decreases considerably near the Si (001) surface as expected and as is the case for other semiconductor materials, in the case of a Ge (001) surface, the S-parameter shows no remarkable dependence on depth although both are group IV elements and have the same diamond structure. For the PAS measurements, moderately doped p-type Si and n-type Ge (001) wafers were used with a resistivity at room temperature in the range of 10–100 ohm corresponding with a carrier concentration at room temperature in the range of 10 13 ∼10 15 cm −3 . As a reference for the Si bulk and at the same time the near surface of Ge, a Geon-Insulator (GOI) wafer with a un-doped Ge top-layer produced by the Ge condensation technique, was also included in the study. The carrier concentration in the n-type Ge film of the GOI wafer that

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Formation of Ge3N4 on Ge(001) substrates by nitrogen radicals and their thermal stability were investigated in this study. A Ge3N4/Ge structure with a root-mean-square surface roughness of 0.18 nm is successfully formed by layer-by-layer manner at a substrate temperature of 300oC. In contrast, island growth and thermal decomposition of Ge3N4 occur during the nitridation at 600oC, and consequently island structures and locally-flat areas are formed. Ge3N4 thickness is saturated at a certain nitridation time and, not only saturation times but also saturation thicknesses are different depending on plasma condition. By a 2-step nitridation in which the nitridation at 300oC and 600oC for 900 sec were sequentially subjected to Ge surfaces, a Ge3N4 thickness much larger than that at the single-step nitridation can be obtained without surface roughening.

Pr silicate and (La2O3)1-x(Al2O3)x composite silicate films have been synthesized. In the fabrication process developed in this study, metal oxide-based films deposited by molecular beam epitaxy or pulsed laser deposition are subjected to high temperature post-deposition annealing (PDA). The PDA effectively induces intermixing of a parasitic interfacial layer with the upper high dielectric constant film and forms a homogeneous film without the interfacial layer, realizing reduced capacitance equivalent oxide thickness as a gate dielectric. Physical and chemical structures of the synthesized films were systematically analyzed as well as their electrical properties.

Metal-oxide-semiconductor field-effect-transistor (MOSFET) with germanium (Ge) channel draws much attention as a probable candidate of next-generation high-mobility devices in recent years. However, it is a serious and essential issue that there is much interface state density (Dit) between germanium dioxide (GeO2) and Ge. Additionally, as is well known, GeO2 is water-soluble so that it is hard to perform conventional ULSI processes to GeO2/Ge stacked structures. Therefore, a stable gate dielectric film on the Ge surface, like silicon dioxide (SiO2) on a silicon (Si) surface, is required. Ge nitride (Ge3N4) is an interesting candidate, which is water-insoluble, and Dit at Ge3N4/Ge interface might be sufficiently low. However, electrical properties of Ge3N4, such as Dit against Ge surface and energy band diagram, are not clear yet. In this study, performing a radical nitridation of amorphous Si (a-Si)/Ge structures, Si nitride/Ge nitride/Ge stacked structures were formed.