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During decommissioning of nuclear facilities, it is generally thought that the risk is relatively low after high activity inventory such as the spent fuel is removed. However, dismantlement works may be carried out with nonmultiple barriers with a nonregular process depending mainly on human activities. Moreover, fire or gas incidents caused by conventional industry methods may lead to accidents with radioactivity release. This means more attention is necessary for safer dismantlement, especially for nuclear reactors with high activity. Therefore, utilization of risk information based on risk assessment of the decommissioning was proposed. A method of risk assessment for decommissioning was developed and applied for the dismantlement of typical reactor facilities and nuclear fuel facilities (a uranium enrichment plant and a reprocessing plant). The results show that the consequences of such troubles are low but their occurrences are still not negligible. This fact is supported by past trouble cases. Taking into account the risk assessment results, a methodology to secure the safety of decommissioning was proposed. It consists of four steps, i.e., (1) risk-informed approach, (2) graded approach, (3) phased approach, and (4) layered approach and the results can be reflected to the management and regulation. The regulation means, for example, the review of decommissioning plan or the operational safety program, the periodic safety inspections and usual monitoring. The methodology can evaluate the risk level of decommissioning more objectively and enable reasonable regulation based on the risk level. This leads to the appropriate distribution of resources for safety enhancement. [DOI: 10.1115/1.4000624]

In digital signal processing, radixes other than two are often used for high-speed computation. In the computation for finance, decimal numbers are used instead of binary numbers. In such cases, radix converters are necessary. This paper considers design methods for binary to q-nary converters. It introduces a new design technique based on weighted-sum (WS) functions. The method computes a WS function for each digit by an LUT cascade and a binary adder, then adds adjacent digits with q-nary adders. A 16-bit binary to decimal converter is designed to show the method. [ABSTRACT FROM AUTHOR]

The authors propose a system to evaluate multiple output logic functions using hardware based on a decision diagram. In addition, the authors propose a PMDD (Paged reduced ordered Multivalued Decision Diagram) as a data structure. Methods to evaluate a logic function in hardware include methods based on an SBDD (Shared reduced ordered Binary Decision Diagram). The method based on a PMDD evaluates multiple output functions using several computational units, and as a result is faster compared to methods based on an SBDD. The multiple output logic function to be created is represented using a PMDD and stored in memory. Then a control circuit which can search the PMDD is added. The authors compare the memory capacity and processing time required for various benchmark functions for the SBDD and their PMDD. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 87(9): 73–81, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20097 [ABSTRACT FROM AUTHOR]

It is desired to reduce the area of mask PLA to save the silicon area and im- prove the switching speed. In the usual methods for folding, the columns and/or rows are folded with cuts. On the contrary, recently, a new folding technique has been proposed by the authors In that technique, a variable line and its negation are folded into one line by inserting an inverter. This paper formulates that folding by using the regular ternary logic function and then clarifies its properties. An algorithm is described which generates the maximum folding. Some experimental results indicate that this algorithm is effective. It is easy to implement the algorithm on computers. [ABSTRACT FROM AUTHOR]