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Compressive sensing (CS) is recognized for its adeptness at compressing signals, making it a pivotal technology in the context of sensor data acquisition. With the proliferation of image data in Internet of Things (IoT) systems, CS is expected to reduce the transmission cost of signals captured by various sensor devices. However, the quality of CS-reconstructed signals inevitably degrades as the sampling rate decreases, which poses a challenge in terms of the inference accuracy in downstream computer vision (CV) tasks. This limitation imposes an obstacle to the real-world application of existing CS techniques, especially for reducing transmission costs in sensor-rich environments. In response to this challenge, this paper contributes a CV-oriented adaptive CS framework based on saliency detection to the field of sensing technology that enables sensor systems to intelligently prioritize and transmit the most relevant data. Unlike existing CS techniques, the proposal prioritizes the accuracy of reconstructed images for CV purposes, not only for visual quality. The primary objective of this proposal is to enhance the preservation of information critical for CV tasks while optimizing the utilization of sensor data. This work conducts experiments on various realistic scenario datasets collected by real sensor devices. Experimental results demonstrate superior performance compared to existing CS sampling techniques across the STL10, Intel, and Imagenette datasets for classification and KITTI for object detection. Compared with the baseline uniform sampling technique, the average classification accuracy shows a maximum improvement of 26.23%, 11.69%, and 18.25%, respectively, at specific sampling rates. In addition, even at very low sampling rates, the proposal is demonstrated to be robust in terms of classification and detection as compared to state-of-the-art CS techniques. This ensures essential information for CV tasks is retained, improving the efficacy of sensor-based data acquisition systems. [ABSTRACT FROM AUTHOR]

This letter proposes an online energy management framework for smart buildings. Two low-complexity estimators for thermal comfort and electrical load are investigated and integrated into an optimization framework. The proposed framework optimizes operations of a battery system and multiple heating, ventilation, and air conditioning (HVAC) systems to minimize energy consumption and power peak while maximizing occupants’ thermal comfort. The effectiveness of the proposed framework is demonstrated using data measured in actual campus buildings in terms of system costs, thermal comfort, and computational complexity. The results show that the proposed framework can reduce electricity costs by 5.7% compared to the baseline. [ABSTRACT FROM AUTHOR]

Non-Intrusive Load Monitoring (NILM), which provides sufficient load for the energy consumption of an entire building, has become crucial in improving the operation of energy systems. Although NILM can decompose overall energy consumption into individual electrical sub-loads, it struggles to estimate thermal-driven sub-loads such as occupants. Previous studies proposed Non-Intrusive Thermal Load Monitoring (NITLM), which disaggregates the overall thermal load into sub-loads; however, these studies evaluated only a single building. The results change for other buildings due to individual building factors, such as floor area, location, and occupancy patterns; thus, it is necessary to analyze how these factors affect the accuracy of disaggregation for accurate monitoring. In this paper, we conduct a fundamental evaluation of NITLM in various realistic office buildings to accurately disaggregate the overall thermal load into sub-loads, focusing on occupant thermal load. Through experiments, we introduce NITLM with deep learning models and evaluate these models using thermal load datasets. These thermal load datasets are generated by a building energy simulation, and its inputs for the simulation were derived from realistic data like HVAC on/off data. Such fundamental evaluation has not been done before, but insights obtained from the comparison of learning models are necessary and useful for improving learning models. Our experimental results shed light on the deep learning-based NITLM models for building-level efficient energy management systems. [ABSTRACT FROM AUTHOR]

Power integrity is a crucial design issue for nano-meter technologies because of decreased supply voltage and increased current. We focused on gate delay variation caused by power/ground noise, and developed a full-chip simulation current model with capacitance and a variable resistor to accurately model current dependency on voltage drop. Measurement results for 90-nm technology are well reproduced in simulation. The error of average supply voltage is 0.9 % in average. Measurement results also demonstrate that gate delay depends on average voltage drop. Index Terms--Delay estimation, full-chip simulation, linear element model, power-supply noise, transistor model.

A proposed media-processor architecture, which is appropriate for MPEG-4 natural and synthetic video decoding, was developed. The architecture focused on the functional module for inverse discrete cosine transform (IDCT) and a geometrical transformer. Its distinct feature is that four matrix-vector multipliers can carry out matrix-vector multiplications required in the geometrical transformation of 3-D computer graphics for synthetic video objects and in the IDCT for natural video objects.

The main target of Single image super-resolution is to recover high-quality or high-resolution image from degraded version of low-quality or low-resolution image. Recently, deep learning-based approaches have achieved significant performance in image super-resolution tasks. However, existing approaches related with image super-resolution fail to use the features information of low-resolution images as well as do not recover the hierarchical features for the final reconstruction purpose. In this research work, we have proposed a new architecture inspired by ResNet and Xception networks, which enable a significant drop in the number of network parameters and improve the processing speed to obtain the SR results. We are compared our proposed algorithm with existing state-of-the-art algorithms and confirmed the great ability to construct HR images with fine, rich, and sharp texture details as well as edges. The experimental results validate that our proposed approach has robust performance compared to other popular techniques related to accuracy, speed, and visual quality. [ABSTRACT FROM AUTHOR]

An MPEG2 video decoder core dedicated to MP@HL (Main Profile at High Level) images is described with the main theme focused on an inverse discrete cosine transformer and a motion compensator. By means of various novel architectures, the inverse discrete cosine transformer achieves a high throughput, and the motion compensator performs different types of picture prediction modes employed by the MPEG2 algorithm. The decoder core, implemented in the total chip area of 22.0 [mm.sup.2] by a 0.6-[[micro]meter] triple-metal CMOS technology, processes a macroblock within 3.84 [[micro]seconds], and therefore is capable of decoding HDTV (1920 x 1152 pels) images in real time.

In this study, we clarify the effectiveness of the energy‐effective techniques for the occupancy lighting control that is based on an occupancy sensor. The time delay from detecting no occupant to turning off the light is used for performing the occupancy control to avoid erroneously turning off the light (hereafter referred to as false‐off). Our experiment was conducted at an actual home environment over 8 days. We evaluated the performance of an image‐based sensor, which detects the occupants using image‐processing techniques and time‐delay adaptation, which decreases the time delay without false‐off. Compared with a passive infrared sensor, the image‐based sensor increased the average sensing accuracy for occupants with small movements by 21.58% or more. In addition, compared with the no‐adaptation case, the time‐delay adaptation increased the rate of average lighting energy saving by 3.94% or more. However, the experimental results suggested that the parameter of the time‐delay adaptation should be carefully set in terms of the energy‐saving effect and false‐off. The analysis and its practical discussions are included in this paper to achieve further energy efficiency. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

Herein, a picture control method designed to facilitate power management of large active‐matrix organic‐light‐emitting‐diode displays is proposed. In this method, Hybrid Log‐Gamma (HLG) pictures are presented simply by multiplying the upper half of the picture level by the gain corresponding to the power suppression. HLG is a standard for high‐dynamic‐range images. The controlled picture is processed by nominal luminance transformation, as well as by color conversion from red–green–blue into hue–saturation–value (HSV) imagery. Results obtained via simulations show that high‐contrast HLG pictures can be better simulated by our proposed method than by currently used conventional methods. The simulation results also demonstrate that when the picture is presented using the proposed power consumption management method, both the dark and bright regions show less deterioration. In addition, through an examination of image histograms created to elucidate detail descriptions of simulated pictures in the red–green–blue and HSV color spaces, we found that using HSV color conversion in conjunction with the proposed method mitigates chromaticity shift and that the feasibility of HSV color conversions could be quantitatively clarified by the evaluation of color differences defined by the Euclidean distance in a uniform color space. A picture level control method designed for power management of large active‐matrix organic‐light‐emitting‐diode displays is demonstrated. Bright regions of Hybrid Log‐Gamma pictures are partly suppressed to efficiently control the power consumption, and hue–saturation–value color conversion is employed to reduce chromaticity shift. Simulation results show that the proposed method can provide Hybrid Log‐Gamma pictures with less deterioration of both the dark and bright regions. [ABSTRACT FROM AUTHOR]

This paper proposes a mean time-to-failure (MTTF) aware design methodology for minimizing power dissipation while satisfying target chip lifetime. The key contributions of the proposed design methodology are to explicitly introduce MTTF as a design constraint and optimize the design with activation-aware slack assignment (ASA). Conventionally, the gates included in nonintrinsic critical paths are downscaled or replaced with high- $V$ th gates for power savings, where the nonintrinsic critical paths are timing paths which originally had large timing slacks before the downscaling and replacement. On the other hand, ASA gives timing slacks to nonintrinsic critical paths and reduces the number of active paths whose delays are very close to those of intrinsic critical paths whose timing slacks cannot be increased by resynthesis and sizing. The proposed optimization includes both pre-ASA circuit design and ASA implementation. The former pre-ASA design prepares several design candidates that laid out with different timing constraints and selects the most promising candidate regarding power. For this selection, every candidate is analyzed to estimate minimum supply voltage after ASA that can achieve the target MTTF. Then, the proposed methodology selects a set of flip-flops for ASA using integer linear programming, such that it reduces the sum of gatewise failure probability maximumly, and performs ASA. We evaluate MTTF of circuits with and without ASA and examine how much power saving can be obtained while satisfying the target MTTF, e.g., 10 years. Evaluation results show that the circuits with ASA achieve up to 49.6% power saving. [ABSTRACT FROM AUTHOR]

In this paper, we propose OptRod, a shape‐free and multi‐functional display system operated by projected images. A PC generates images as control signals and projects them to the bottom of OptRods by a projector or LCD. An OptRod receives the light and converts its brightness into a control signal for the attached output device. By using multiple OptRods, the PC can simultaneously operate many output devices without any signal lines. Moreover, we can arrange surfaces of various shapes easily by combining multiple OptRods. OptRod supports various functions by replacing the device unit connected to OptRod. [ABSTRACT FROM AUTHOR]

The mode decision strategy adopted in the High Efficiency Video Coding test model increases the complexity drastically. In this paper, we present a course of low-complexity fast mode decision algorithms. First, the depth information of the colocated block from a previous frame is used to predict the size of current block. Next, for a certain sized block, the inter-prediction residual is analyzed to determine whether to terminate the mode decision process or to skip unnecessary modes and split the block into smaller sizes. After inter-prediction, a hardware-oriented low-complexity fast intra-mode decision algorithm is proposed. A fast discrete cross difference is adopted to detect the dominant direction of the block. In addition, four simple but efficient early termination strategies are proposed to terminate the rate-distortion optimization process properly. The simulation results show that these proposed algorithms reduce the encoding time by 54.0%–68.4% without incurring any noticeable performance degradation. Hardware synthesis results demonstrate that the proposed fast intra-mode decision algorithm can be easily implemented on a hardware platform with fewer resources consumed. [ABSTRACT FROM PUBLISHER]

We experimentally characterized and compared the soft error rates of 65-nm bulk and silicon on thin buried oxide (SOTB) SRAMs by conducting accelerated alpha and neutron irradiation tests. Measurement results show that an SOTB SRAM has better soft error immunity than a bulk SRAM. In particular, the number of 2-bit multiple cell upsets (MCUs) of SOTB SRAM was smaller by two orders of magnitude than that of bulk SRAM, and the number of 3-bit or larger MCUs decreased further. In addition, the reverse body bias (RBB) reduced the soft error rate of SOTB SRAM to two-thirds of zero body bias (ZBB). To investigate this dependence on body bias, we evaluated the sensitive cross sectional area for ZBB and RBB with 3D technology computer aided design device simulations. The simulation results show that the RBB decreases the sensitive cross-sectional area of an SOTB device for small linear energy transfer (LET) ions, which is consistent with the measured dependence on body bias. [ABSTRACT FROM PUBLISHER]