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The design, manufacture and subsequent testing of a superconductive flash digitizer circuit utilizing niobium trilayer technology is presented. The device will be used in recording transient physical phenomena such as electromagnetic pulses. The superconductive flash digitizer is composed of a 6-bit flash analog-to-digital converter, on-chip switches for data acquisition control and a bank of acquisition shift-registers for on-chip memory.

The development of a 16-bit serial analog-to-digital converter (ADC) aimed at reducing the number of outputs originating from the chip is presented. The device is intended for producing a high-resolution ADC that is expected to have wide applications in areas such as readout electronics for infrared detectors. Extracting the serial ADC output with an optical fiber coupled to a laser diode results in a further reduction of the heat load and a stronger signal transmission.

A study was conducted on a single-chip digital superconducting quantum interference device (SQUID) magnetometer. Results show that an input analog SQUID determines the noise level and sensitivity in an optimized magnetometer chip. The chips can be used in high magnetic field environments without extensive magnetic shielding due to their wide dynamic range. External two-phase clock frequencies were used to determine the devices' slew rate.

Digital error-correction circuits for enhancing superconductive flash analog-to-digital converter (ADC) performance were designed, fabricated and tested. Threshold errors occur mostly in comparators coding the most significant bits since they are not sensitive to input signal and are subject to threshold misplacement and jitter. The new ADC architecture employs two comparators per bit and is free from threshold errors.

High bandwidth Josephson circuits were developed for interfacing the rapid single flux quantum (RSFQ) circuits' output to room temperature electronics. The RSFQ signal levels were amplified to voltage outputs in the 2-4 mV range using asynchronous direct current powered voltage driver circuits which were analyzed and tested for data rates of up to 8 Gb/s. Circuits integrated with drivers were successfully tested at low speed while shift registers integrated with voltage driver circuits were demonstrated at high-speed.

A time-to-digital converter was designed, fabricated and tested. The converter circuit features superconductive counters based on toggle flip-flops with destructive readout, pulse detectors, parallel-to-serial converters and shift registers. HYPRES' library of standard RSFQ cells was used for the implementation of the circuits in HYPRES' standard Nb process with a 1.0 kA/cm2 critical current density.

A new Rapid Single Flux Quantum (RSFQ) compatible design was compared to a superconducting quantum interference device wheel/Quantum Flux Parametron comparator. Both provide -0.5 ps threshold accuracy which enables the development of a flash analog-to-digital converter with six effective bits of resolution at 10 GHz input bandwidth. Results show that the RSFQ design has a faster and more flexible clocking scheme and a better signal-to-noise ratio than the comparator.

A flux-quantizing analog-to-digital converter is built using rapid single flux quantum elements. The converter features a single-junction voltage-biased front end that provides wide-dynamic-range hysteresis-free operation with fractional-flux-quantum least significant bit. The front end also enables the generation of high-linearity multibit differential code, allowing conversions with large oversampling ratio and effective resolution.

A digital superconducting quantum interference device (SQUID) that uses the oversampling delta-modulation technique is fabricated using a novel architecture. The device consists of a pickup coil, a SQUID amplifier, a feedback loop and edge-triggered latching comparators. It generates a sampling frequency which can suppress the quantization noise below the the SQUID intrinsic noise.

The linearity and dynamic range of flux-quantizing analog/digital converters (ADCs) were measured using a simple double-counter analog/digital architecture. Analog/digital converter chips fabricated using a standard niobium processing technology were used in the study. Results show that the flux-quantizing ADCs have excellent conversion properties and exhibit no evidence of nonlinearity.

This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits. The target application is the integration of optics on to the first-level package, connecting high-speed optical I/O directly to an advanced CMOS host chip (e.g., processor and switch) to increase package I/O bandwidth density and lower overall system power and cost. The optical link is designed for maximum link margin to tolerate high optical losses created by low-cost optical packaging. The transmitter (TX) uses a three-tap, 1/2-unit-interval-spaced feed-forward equalizer to improve eye opening. The receiver (RX) uses a low-bandwidth, low-noise transimpedance amplifier and a speculative one-tap decision-feedback equalizer for high sensitivity. The TX and RX power efficiencies are 3.3 and 1.4 pJ/bit, respectively. The TX optical modulation amplitude (OMA) is 1.2 dBm, and the RX sensitivity is −11.7 dBm OMA at a bit error rate of 10−12 with PRBS31 data, providing 12.9-dB link margin. [ABSTRACT FROM AUTHOR]

A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels without loss of bandwidth. Transceiver circuit innovations are described including a low-skew transmission-line clock distribution, a 4:1 serializer with quadrature quarter-rate clocks, and a phase rotator based on current-integrating phase interpolators. Measurements of a test chip fabricated in 32 nm SOI CMOS technology demonstrate 1.4 pJ/b efficiency over 0.75” Megtron-6 PCB traces, and 1.9 pJ/b efficiency over 20” Megtron-6 PCB traces. [ABSTRACT FROM PUBLISHER]

This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking amplifier is enhanced by adopting a structure with capacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the transceiver over a channel with 35 dB loss at half-baud frequency. In a four-port core configuration, the power consumption at 28~Gb/s is 693 mW/lane. [ABSTRACT FROM PUBLISHER]

A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging technologies, the system uses 50 \mum-pitch \muC4s to reduce I/O cell size and fine-pitch interconnects on silicon carrier to achieve record-breaking interconnect density. An I/O architecture is introduced with link redundancy such that any link can be taken out of service for periodic recalibration without interrupting data transmission. A timing recovery system using two phase rotators shared across all bits in a receive bus is presented. To demonstrate these concepts, an I/O chipset using this architecture is fabricated in 45 nm SOI CMOS technology. It includes compact DFE-IIR equalization in the receiver, as well as a new all-CMOS phase rotator. The chipset is mounted to a silicon carrier tile via Pb-free SnAg \muC4 solder bumps. Chip-to-chip communication is achieved over ultra-dense interconnects with pitches of between 8 \mum and 22 \mum. 8\,\times\,10-Gb/s data is received over distances up to 4 cm with a link energy efficiency of 5.3 pJ/bit from 1 V TX and RX power supplies. 8\,\times\,9-Gb/s data is recovered from a 6-cm link with 16.3 dB loss at 4.5 GHz with an efficiency of 6.1 pJ/bit. [ABSTRACT FROM PUBLISHER]

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feed- back equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200 mVppd, one transmitter/receiver pair and one PLL consume 300 mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization. [ABSTRACT FROM AUTHOR]