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We investigate bias temperature instability (BTI) charge trapping trends in high- $k$ metal gate (HKMG) stacks with a variety of work function metals (WFMs). Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work function. However, experimental data on capacitors show enhanced or reduced charge trapping at a constant oxide electric field for different WFM stacks. We ascribe this to a different chemical interaction of the metals with the dielectric, which yields different defect profiles depending on the process thermal budget, and not to the gate work function per se. This observation is confirmed by comparing BTI degradation in nMOS and pMOS replacement gate planar transistors with three selected WFM stacks (representative of high-, standard-, and low- $V_{\mathrm{ th}}$ device flavors), and two different process thermal budgets. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy,” we also show that, on top of the unavoidable chemical interaction of different metals with the underlying SiO2/HfO2 dielectric stack, different gate work functions within a typical range of relevance (4.35–4.75 eV) can yield a different charge state of the deep high- $k$ defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs. [ABSTRACT FROM AUTHOR]

We investigate the negative-bias temperature instability (NBTI) degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages and thereby generalize existing digital-stress NBTI studies. Starting from our ultrafast NBTI measurements and an extensive TCAD analysis, we study two physics-based compact models for analog-stress NBTI including recovery. The high accuracy of both models is evidenced from single-FET analog-stress and circuit-level ring oscillator experiments. Their numerical efficiency allows direct coupling to circuit simulators and permits to accurately account for NBTI already during circuit design. Furthermore, one of the models calculates the time-dependent NBTI variability of single-FET and of circuit performance parameters. We demonstrate our NBTI models on a ring oscillator and calculate the mean drift and statistical distribution of its oscillation frequency. [ABSTRACT FROM AUTHOR]

It is well-established that oxide defects adversely affect functionality and reliability of a wide range of microelectronic devices. In semiconductor-insulator systems, insulator defects can capture or emit charge carriers from/to the semiconductor. These defects feature several stable configurations, which may have profound implications for the rates of the charge capture and emission processes. Recently, these complex capture/emission events have been investigated experimentally in considerable detail in Si/SiO 2 devices, but their theoretical understanding still remains vague. In this paper we discuss in detail how the capture/emission processes can be simulated using the theoretical methods developed for calculating rates of charge transfer reactions between molecules and in electro-chemistry. By employing this theoretical framework we link the atomistic defect configurations to known trapping model parameters (e.g. trap levels) as well as measured capture/emission times in Si/SiO 2 devices. Using density functional theory (DFT) calculations, we investigate possible atomistic configurations for various defects in amorphous ( a )-SiO 2 implicated in being involved in the degradation of microelectronic devices. These include the oxygen vacancy and hydrogen bridge as well as the recently proposed hydroxyl E ′ center. In order to capture the effects of statistical defect-to-defect variations that are inevitably present in amorphous insulators, we analyze a large ensemble of defects both experimentally and theoretically. This large-scale investigation allows us to prioritize the candidates from our defect list based on their trap parameter distributions. For example, we can rule out the E ′ center as a possible candidate. In addition, we establish realistic ranges for the trap parameters, which are useful for model calibration and increase the credibility of simulation results by avoiding artificial solutions. Furthermore, we address the effect of nuclear tunneling, which is involved according to the theory of charge transfer reactions. Based on our DFT results, we demonstrate the impact of nuclear tunneling on the capture/emission process, including their temperature and field dependence, and also give estimates for this effect in Si/SiO 2 devices. [ABSTRACT FROM AUTHOR]

SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology. [ABSTRACT FROM AUTHOR]

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained. [ABSTRACT FROM AUTHOR]

Mapping and visualization of all degradation modes in both n- and p-channel field effect transistors, specifically devices for dynamic random access memory periphery, is performed in the (VG, VD) bias space applicable for complementary metal-oxide-semiconductor operation. This "all-in-one" approach allows for tracking and studying in parallel all degradation regimes, including bias temperature instability, hot carrier degradation, and off-state stress, as well as the transitions between them. It should prove beneficial when developing new very large-scale integrated technologies, since it allows for simultaneous comparison and checking of all degradation regimes and promptly identifying "weak spots" of each technology option. It also allows to choose the correct criteria (voltages or fields) at a later time and postprocessing the data as necessary. [ABSTRACT FROM AUTHOR]