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Hard learning problems are important building blocks for the design of various cryptographic functionalities such as authentication protocols and post-quantum public key encryption. The standard implementations of such schemes add some controlled errors to simple (e.g., inner product) computations involving a public challenge and a secret key. Hard physical learning problems formalize the potential gains that could be obtained by leveraging inexact computing to directly generate erroneous samples. While they have good potential for improving the performances and physical security of more conventional samplers when implemented in specialized integrated circuits, it remains unknown whether physical defaults that inevitably occur in their instantiation can lead to security losses, nor whether their implementation can be viable on standard platforms such as FPGAs. We contribute to these questions in the context of the Learning Parity with Physical Noise (LPPN) problem by: (1) exhibiting new (output) data dependencies of the error probabilities that LPPN samples may suffer from; (2) formally showing that LPPN instances with such dependencies are as hard as the standard LPN problem; (3) analyzing an FPGA prototype of LPPN processor that satisfies basic security and performance requirements.

This paper focuses on the FPGA implementation of a slew-rate reduction (SR) shaping function for envelope tracking (ET) power amplifiers (PAs). The SR envelope has been proved effective to trade-off power efficiency and linearity in ET PA systems where the envelope tracking modulator (ETM) is bandwidth limited. However, the implementation issues need to be addressed when targeting high clock rates to cope with current 5G new radio wide-band signals. This paper shows the FPGA implementation of the SR envelope generation. We explore the use of high-level synthesis (HLS) for the SR envelope generation to evaluate the performance and resource usage of the hardware architecture. The HLS design is also compared with a hand-written hardware description language (HDL) version. An in-depth analysis shows strengths and limitations of the HLS design to meet the timing constraints when considering a throughput of 614.4 MSa/s. © 2022 IEEE.

Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called "data deluge gap"). This has resulted in both the academic and industrial community investigating novel computing paradigms and design approaches at all levels from materials, devices, circuits, architectures, and all the way to system-level implementations and applications. For example, to improve performance, the community has been investigating solutions through massively parallel and distributed systems that are a rupture from von Neumann architectures. As artificial neural networks (ANN) and deep neural networks (DNN) that are trained over hundreds of graphic processing units (GPU)-accelerated servers where each GPU can have thousands of cores. The limitations of data processing through the memory wall in von Neumann architectures have been overcome with bringing computing to the data inspired by biological brainlike computing. An alternative computing approach based on ANNs uses oscillators to compute or oscillatory neural networks (ONNs). Such an approach differs from classical CMOS and classical von Neumann where building blocks are analog and perform computations efficiently. Moreover, data is encoded on the oscillator signals phase, which is a departure from the classical voltage level-based data encoding (such as amplitude voltage to represent a logical bit '1' or '0'). ONNs can perform computations efficiently and can be used to build a more extensive neuromorphic system. How should a designer choose to optimally implement ONNs in analog is the focus of many ongoing research efforts. But here, we address a more fundamental problem, can we efficiently perform AI applications (such as image/pattern recognition) with ONNs? In other words, what are the advantages and limitations of the ONN computing paradigm for practical AI applications? Here, we present a digital ONN implementation to show a proof-of-concept of the ONN approach of "computing-in-phase" for pattern recognition applications. To the best of our knowledge, this is the first attempt to implement an FPGA-based fully-digital ONN. We report ONN accuracy, training, inference, memory capacity, operating frequency, hardware resources based on simulations and implementations of 5x3 and 10x6 ONNs. We present the digital ONN implementation on FPGA for pattern recognition applications such as performing digits recognition from a camera stream. We discuss practical challenges and future directions in implementing digital ONN.

The spread of epidemics and diseases is known to exhibit chaotic dynamics; a fact confirmed by many developed mathematical models. However, to the best of our knowledge, no attempt to realize any of these chaotic models in analog or digital electronic form has been reported in the literature. In this work, we report on the efficient FPGA implementations of three different virus spreading models and one disease progress model. In particular, the Ebola, Influenza, and COVID-19 virus spreading models in addition to a Cancer disease progress model are first numerically analyzed for parameter sensitivity via bifurcation diagrams. Subsequently and despite the large number of parameters and large number of multiplication (or division) operations, these models are efficiently implemented on FPGA platforms using fixed-point architectures. Detailed FPGA design process, hardware architecture and timing analysis are provided for three of the studied models (Ebola, Influenza, and Cancer) on an Altera Cyclone IV EP4CE115F29C7 FPGA chip. All models are also implemented on a high performance Xilinx Artix-7 XC7A100TCSG324 FPGA for comparison of the needed hardware resources. Experimental results showing real-time control of the chaotic dynamics are presented.

Lightweight cryptography is a vital and fast growing field in today&rsquo, s world where billions of constrained devices interact with each other. In this paper, two novel compact architectures of the Enocoro-128v2 stream cipher are presented. The Enocoro-128v2 is part of the ISO/IEC 29192-3 standard. The first architecture has an 8-bit datapath while the second one has a 4-bit datapath. The proposed architectures were implemented on the BASYS3 board (Artix 7 XC7A35T) using the VERILOG hardware description language. The hardware implementation of the proposed 8-bit architecture runs at a 189 MHz clock and reaches a throughput equal to 302 Mbps, while at the same time, it utilizes only 254 Look-up Tables (LUTs) and 330 Flip-flops (FFs). Each round of computations requires 5 clock cycles. The 4-bit implementation has an operating frequency of 204 MHz and reaches a throughput equal to 181 Mbps, with each round requiring 9 clock cycles. The 4-bit implementation utilizes 249 LUTs and 343 FFs. To our knowledge, this is the first time that such implementations of the Enocoro-128v2 are presented. Both implementations utilize a very low number of resources (only 78 FPGA slices are required for the 8-bit architecture and only 83 for the 4-bit one) and the results demonstrate that they are sustainable for area constrained embedded devices.

Support vector machine (SVM) is a robust machine learning model with high classification accuracy. SVM is widely utilized for online classification in various real-time embedded applications. However, implementing SVM classification algorithm for an embedded system is challenging due to intensive and complicated computations required. Several works attempted to optimize performance and cost by implementing SVM in hardware, especially on field-programmable gate array (FPGA) as it is a promising platform for meeting challenging embedded systems constraints. This article presents a comprehensive survey of hardware architectures used for implementing SVM on FPGA over the period 2010–2019. We performed a critical analysis and comparison of existing works with in-depth discussions around limitations, challenges, and research gaps. We concluded that the primary research gap is overcoming the challenging trade-off between meeting critical embedded systems constraints and achieving efficient and precise classification. Finally, some future research directions are proposed, aiming to address such research gaps.

The recently uncovered problem of multi-point progressive blocking (MPB) has significantly increased the complexity of schedulability analysis of priority-preemptive wormhole networks-on-chip. While state-of-the-art analysis is currently deemed safe, there is still significant inherent pessimism when it comes to considering backpressure issues caused by downstream indirect interference. In this paper, we attempt to simplify the problem by considering a novel flow control protocol that can avoid backpressure issues, enabling simpler schedulability analysis approaches to be used. Rather than construct the analysis to fit the protocol, we modify the protocol so that effective analysis applies. We describe the changes to a baseline wormhole router in order to implement the proposed protocol, and comment on the impact on hardware overheads. We also examine the number of routers that actually require these changes. Comparative analysis of FPGA implementations show that the hardware overheads of the proposed NoC router are comparable or lower than those of the baseline, while analytical comparison shows that the proposed approach can guarantee schedulability in up to 77% more cases.

Binarized neural networks (BNNs) have shown exciting potential for utilising neural networks in embedded implementations where area, energy and latency constraints are paramount. With BNNs, multiply-accumulate (MAC) operations can be simplified to XnorPopcount operations, leading to massive reductions in both memory and computation resources. Furthermore, multiple efficient implementations of BNNs have been reported on field-programmable gate array (FPGA) implementations. This paper proposes a smaller, faster, more energy-efficient approximate replacement for the XnorPopcountoperation, called XNorMaj, inspired by state-of-the-art FPGAlook-up table schemes which benefit FPGA implementations. Weshow that XNorMaj is up to 2x more resource-efficient than the XnorPopcount operation. While the XNorMaj operation has a minor detrimental impact on accuracy, the resource savings enable us to use larger networks to recover the loss., 4 pages

The increasing complexity of new digital signal processing (DSP) applications is forcing the use of floating point (FP) numbers in their hardware implementations. In this brief, we investigate the advantages of using half-unit biased (HUB) formats to implement these FP applications on field-programmable gate arrays (FPGAs). These new FP formats allow for the effective elimination of the rounding logic on FP arithmetic units. First, we experimentally show that HUB and standard formats provide equivalent signal-to-noise ratio on DSP application implementations. We then present a detailed study of the improvement achieved when implementing FP adders and multipliers on FPGAs by using HUB numbers. In most of the cases studied, the HUB approach reduces resource use and increases the speed of these FP units while always providing statistically equivalent accuracy as that of conventional formats. However, for some specific sizes, HUB multipliers require far more resources than the corresponding conventional approach.

International audience; We present various FPGA implementations of protections against SCAs for RLWE-based PKE. We implemented the main solutions from the state of the art with improved variants. We also propose a new protection based on a redundant representation of the ring elements to randomize computations. We compare the implementation results of all these solutions.

As redes reguladoras de genes são modelos baseados em grafos muito utilizadas para estudar o comportamento de células, processos de diferenciação celular ou tratamento e evolução de doenças. Uma rede pode ser implementada por um grafo com equações booleanas. Os algoritmos usados nas simulações das redes avaliam estas equações várias vezes ao longo da execução. Este artigo propõe um estudo das implementações em CPU, GPU e FPGA da operação básica que é o cálculo do próximo estado. Exploramos as técnicas de vetorização e paralelização com AVX e OpenMP para os processadores e uma nova arquitetura dinâmica é proposta para simplificar o uso das soluções com FPGA. Além do modelo booleano, mostramos como as redes podem ser transformadas em equações com somas de peso e limiares. Finalmente, 16 redes biológicas usados na literatura foram avaliadas, onde as implementações em CPU com OMP apresentaram uma aceleração de 3x em comparação com a CPU, as implementações em GPU foram em média 57,3x mais rápidas que a CPU e finalmente as implementações em FPGA foram em média 86,7x mais rápidas que a CPU. ∗

This paper presents a new technique that dynamically estimates and updates the coefficients of a digital predistorter (DPD) for power amplifier (PA) linearization. The proposed technique is dynamic in the sense of estimating, at every iteration of the coefficient’s update, only the minimum necessary parameters according to a criterion based on the residual estimation error. At the first step, the original basis functions defining the DPD in the forward path are orthonormalized for DPD adaptation in the feedback path by means of a precalculated principal component analysis (PCA) transformation. The robustness and reliability of the precalculated PCA transformation (i.e., PCA transformation matrix obtained off line and only once) is tested and verified. Then, at the second step, a properly modified partial least squares (PLS) method, named dynamic partial least squares (DPLS), is applied to obtain the minimum and most relevant transformed components required for updating the coefficients of the DPD linearizer. The combination of the PCA transformation with the DPLS extraction of components is equivalent to a canonical correlation analysis (CCA) updating solution, which is optimum in the sense of generating components with maximum correlation (instead of maximum covariance as in the case of the DPLS extraction alone). The proposed dynamic extraction technique is evaluated and compared in terms of computational cost and performance with the commonly used QR decomposition approach for solving the least squares (LS) problem. Experimental results show that the proposed method (i.e., combining PCA with DPLS) drastically reduces the amount of DPD coefficients to be estimated while maintaining the same linearization performance.

With the increasing need for highly secure systems, Physical Unclonable Functions (PUFs) have emerged within the last decade. Ordering based Ring Oscillator (RO) PUFs are one of the best performing structures with their robustness and suitability to FPGA implementations. Even though the performance of the ordering based RO-PUFs have been analyzed in detail, effects of aging have not been studied before. In this work, we present the results of an accelerated aging test applied to analyze the effects of aging on ROs. Then, the effects of aging on ordering based RO-PUFs are examined. Finally, a compensation method to protect the 100% robustness claim of the PUF structure is proposed and its influence on the circuit performance is presented. HighlightsResults of an accelerated aging test applied on ROs are presented.The effects of aging on ordering based RO-PUFs are examined.A compensation method to protect the 100% robustness of the PUF structure is proposed.

[EN] A method for the implementation of the atan2 operator based on the coordinate rotation digital computer algorithm is described. In the proposal, the computation of the z-path takes advantage of the look-up table-based FPGA resources to reduce by between 17 and 25%, without performance deterioration, the overall area of the unrolled architecture., This work was funded by the Spanish Ministerio de Economia y Competitividad and FEDER under the grant TEC2015-70858-C2-2-R.

Proyecto CESAR TEC2013-45523-R Proyecto INTERVALO TEC2016-80549-R Proyecto LACRE CSIC 201550E039 La información intercambiada diariamente en las redes de comunicación crece de forma exponencial y gran parte de ella está constituida por información sensible, por lo que debe estar protegida para prevenir su uso fraudulento. Una correcta aplicación de la Criptografía evita el acceso no deseado, de forma que esta información pueda ser protegida. Estudiar la fragilidad/robustez de la seguridad es, pues, una tarea esencial para garantizar esa protección. Por otra parte, el ámbito de uso es tan amplio (desde la seguridad gubernamental, como por ejemplo secretos militares del Pentágono, hasta la doméstica) que resulta necesario concretarlo, en este caso, para entornos de pocos recursos (lightweight cryptography) y centrados en implementaciones con dispositivos electrónicos programables de alta densidad. El Trabajo Fin de Máster que se presenta tiene como principal objetivo analizar el funcionamiento de implementaciones FPGA de cifradores de flujo en presencia de ataques laterales activos, en concreto de ataques que intenten introducir fallos en el funcionamiento del Trivium aumentando la frecuencia del reloj. A través del análisis de las técnicas de ataques laterales activos, se presenta un sistema cuyo objetivo es analizar la vulnerabilidad y comportamiento del cifrador Trivium, implementado sobre FPGA, frente a dichos ataques laterales activos. The large amount of information exchanged grows exponentially and a lot of it is constituted by sensitive data, it must be protected to prevent its fraudulent use. A correct application of Cryptography prevents malicious access, so that information can be protected. Studying the vulnerability/robustness of the security is, then, an essential aim in order to guarantee that protection. On the other hand, the field of use is so wide that it is necessary, in this case, for low resource environments and focused on device implementations with high density programmable electronic. The aim of this TFG is to analyze the behaviour of stream ciphers implemented on FPGAs against active attacks, that is inyecting faults in the clock line during the operation of Trivium stream ciphers. Through the analysis of active attack techniques, an attack system is presented with the aim of analyzing the Trivium cipher vulnerability and behavior, implemented on FPGA, against active fault attacks. Universidad de Sevilla. Grado en Ingeniería Electrónica Industrial

The growing trend toward heterogeneous platforms is crucial to meet time and power consumption constraints for high-performance computing applications. The OpenCL parallel programming language and framework enable programming CPU, GPU and recently FPGAs using the same source code. This eases software developers to implement applications on various devices supported by heterogeneous HPC platforms. This work presents two very different FPGA implementations of a database join operation, one using a direct O(n2) algorithm, and the other using a bitonic sort network to speed up the join operation. Comparison of performance and energy consumption for both FPGA and GPUs is provided which suggests a 40% performance/watt improvement by using an FPGA instead of a GPU.

This paper presents a comprehensive review and a comparative study of various hardware/FPGA implementations of Sobel edge detector and explored different architectures for Sobel gradient computation unit in order to show the various trade-offs involved in choosing one over another. The different architectures using pipelining and/or parallelism (key methodologies for improving the performance/frame rates) are explored for gradient computation unit in Sobel edge detector. How the different architectures affected performance (in terms of video frame rate and image size) and area (in terms of FPGA resources usages) has been demonstrated. By exploiting the trade-offs between video frame rate, image size, and FPGA resources a designer should be able to find an optimal architecture for a given application.

Sub-pixel interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC sub-pixel (half-pixel and quarter-pixel) interpolation algorithm using a HLS tool in the literature is proposed. The proposed HEVC sub-pixel interpolation hardware is implemented on Xilinx FPGAs using Xilinx Vivado HLS tool. It, in the worst case, can process 45 quad full HD (3840×2160) video frames per second. Using HLS tool significantly reduced the FPGA development time. Therefore, HLS tools can be used for FPGA implementation of HEVC video encoder.

Date of Conference: 12-14 April 2016 Conference name: 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem is fatal to application-specific Network-on-Chip (NoC) designs as well if they cannot tolerate such failures. One solution to this problem can be having alternative routing options on the network for each communicating pair. In this study, we present an FPGA implementation of such a method for application-specific NoCs. This method adds additional network resources to the non-fault-tolerant design in an attempt to make it fault-tolerant. We show the effects of the presented fault-tolerant method on an FPGA implementation of Mp3 encoder based on energy consumption and area increase against non-fault-tolerant case. © 2016 IEEE.

This paper describes the design and implementation of a hardware-software embedded system for face recognition applications in images and/or videos. The system has hardware components to speed up the face detection and recognition stages. It is a system suitable for applications requiring real-time, due that the response times are deterministic and bounded. The system is based on a previous implementation that had accelerated the image capturing process, and the face detection. This paper will focuses in the face recognition acceleration.

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5 dB for a PER = 10 -2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested. © 2011 Elsevier B.V. All rights reserved., This work was supported by the Spanish Ministerio de Educacion y Ciencia under grant TEC2008-06787.

This paper presents four different realizations of single-multiplier sine-cosine generators based on second-order digital filter structure. FPGA implementations of these four realizations are carried out on FPGA Spartan-3E Kit. Implementation results are compared from the view points of utilization resources and maximum frequency of operation. Another comparison is made between one of implementations of the derived structures and other two recent CORDIC-based implementations. The comparison results indicate that smaller chip area can be achieved in the case of the proposed structure of the sine-cosine generator. In addition, such structure can operate with higher circuit frequency as compared with the two others.

This paper presents a deep-pipelined FPGA implementation of real-time ellipse estimation for eye tracking. The system is constructed by the Starburst algorithm on a stream-oriented architecture and the RANSAC algorithm without any external memories. In particular, the paper presents comparative results between three different hypothesis generators for the RANSAC algorithm based on Cramer's rule, Gauss-Jordan elimination and LU decomposition. Comparison criteria include resource usage, throughput and energy consumption. The result shows that the three implementations have different characteristics and the optimal algorithm needs to be chosen depending on the amount of resources on FPGAs and required performance., 22nd International Conference on Field Programmable Logic and Applications, FPL 2012;Oslo;29 August 2012through31 August 2012, Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on, pp.458-463; 2012

The process to locate objects in an image passes through different phases. At the forefront of these phases, and most importantly, is the edge detection. If edges in an image are identified accurately, all of the objects will be located correctly for further processing phases. Noisy images contain high-frequency contents which might be interfered with image edges that makes edge detection more difficult. In this paper, a software comparative analysis of the performance of three different edge detectors, namely, Roberts, Prewitt and Sobel, is presented. The comparative analysis is performed to check the performance robustness of the edge detectors when noise level fluctuates in the image. In addition, an embedded hardware (HW) system is developed to implement the three detectors on the Zedboard FPGA prototyping board. The purpose of this implementation is to have an embedded system for on-the-move applications where portability is desired. To exploit the new features of the Xilinx Zynq-7000 series, we partition the implementation into (1) hardware part (running on logic gates of FPGA) and (2) software (SW) part (running on ARM processor of FPGA). This heterogeneous HW/SW implementation allows for high accurate results with high speed and efficient area. Furthermore, a hardware comparative analysis of the speed and area of the detectors is presented. The evaluation is performed by using different images (with their ground truths) downloaded from the BSDS500 dataset. The tools used for FPGA implementation are MATLAB and Microsoft Visual Studio (as software tools), Vivado High-level synthesis (HLS) and Software Development Kit (SDK) (as hardware tools). The experimental results show that the Roberts detector achieves better edge detection when the noise level is higher than 40%. It is also faster and requires less capacity of logic gates among the other detectors employed in this study.

In this paper, we propose a modified etaT pairing algorithm in characteristic three which does not need any cube root extraction. We also discuss its implementation on a low cost platform which hosts an Altera Cyclone II FPGA device. Our pairing accelerator is ten times faster than previous known FPGA implementations in characteristic three.