Search

The effect of different gate oxide processes on the performance of 4H-SiC MOSFETs is analyzed. Various MOS device parameters, including threshold voltage, subthreshold slope, field-effect electron mobility, sheet electron carrier concentration and Hall mobility, are correlated with different process steps.

The performance of 4H-SiC planar junction barrier Schottky (JBS) rectifiers and lateral channel JBS (LC-JBS) rectifiers is described. The lateral channel JBS rectifier is designed and demonstrated in 4H-SiC with up to 1.5-kV blocking capability and pinlike reverse characteristics.

A new analytical model including both forward and reverse characteristics for high-voltage junction barrier Schottky (JBS) rectifiers is developed and applied to high-voltage SiC JBS rectifiers. The forward on-resistance of a high-voltage 4H-SiC JBS rectifier has many components, which are dominated by the spreading resistances in the drift layer.

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. The results indicated that GaN MOSFETs could be realized with promising electrical properties using a self-aligned process applicable to power integrated circuits.

A novel flip-chip flex-circuit packaging platform is described that enables integration of multiple power dies and control circuitry with an advantageous form factor. A key attribute of this packaging platform is to extend the well-established flex-circuit and flip-chip soldering technologies in signal electronics to power electronics applications. The planar interconnection and flip-chip method facilitate multilayer packaging structure with reduced packaging dimensions and reduced packaging parasitics. A half-bridge test vehicle designed and fabricated for dc/ac inverter applications (42 V, 16 A) with an overall flex-circuit module footprint less than 30% that of a discrete device printed circuit board implementation has been modeled and demonstrated experimentally. Electrical results, confirmed with circuit simulation incorporating parasitic inductance electromagnetic modeling, have shown a turn-off voltage overshoot reduction of over 40% and a switching energy loss reduction of 24% with the flip-chip flex-circuit implementation. The power flex platform has a strong potential for integrated multichip power module applications that require minimized packaging size and parasitic inductance for high switching frequency and efficiency. Index Terms--Flex-circuit, flip-chip, packaging parasitics, power electronics packaging, switching energy loss, voltage overshoot.

Recent progress in silicon carbide (SIC) material has made it feasible to build power devices of reasonable current density. This paper will present recent results including a comparison with state-of-the-art silicon diodes. Switching losses for two silicon diodes (a fast diode, 600 V, 50 A, 60 ns Trr), an ultrafast silicon diode (600 V, 50 A, 23 ns Trr), and a 4H-SiC diode (600 V, 50 A) are compared. The effect of diode reverse recovery on the turn-on losses of a fast insulated gate bipolar transistor (IGBT) are studied both at room temperature and at 150 [degrees]C. At room temperature, SiC diodes allow a reduction of IGBT turn-on losses by 25% compared to ultrafast silicon diodes and by 70% compared to fast silicon diodes. At 150 [degrees]C junction temperature, SiC diodes allow turn-on loss reductions of 35% and 85% compared to ultrafast and fast silicon diodes, respectively. The silicon and SiC diodes are used in a boost converter with the IGBT to assess the overall effect of SiC diodes on the converter characteristics. Efficiency measurements at light load (100 W) and full load (500 W) are reported. Although SiC diodes exhibit very low switching losses, their high conduction losses due to the high forward drop dominate the overall losses, hence reducing the overall efficiency. Since this is an ongoing development, it is expected that future prototypes will have improved forward characteristics. Index Terms--4H-SiC, carbide, diode, insulated gate bipolar transistor (IGBT), recovery, reverse, silicon, silicon carbide (SIC).

GaN metal oxide semiconductor (MOS) capacitors are used to investigate the effects of annealing temperature and ambient on GaN-insulator interface properties.

SiC P-i-N rectifiers possess forward characteristics that exhibit current-controlled negative resistance. The forward characteristics of 6H-SiC P-i-N rectifiers suggest that the poor electrical performance of SiC diodes can be attributed to the absence of conductivity modulation. This behavior appears to result from high defect densities and low minority carrier lifetime in the lightly doped drift region.

6H-SiC P(super +)N layers have been fabricated using beryllium as an alternate p-type dopant. The implanted junctions have been characterized by photoluminescence and secondary ion mass spectrometry. Experimental results showed that beryllium-implanted 6H-SiC P(super +)N junctions exhibit improved forward characteristics and slightly higher reverse leakages. The activation energies obtained from the forward conduction and reverse leakage characteristics were presented.

A novel procedure for fabricating insulated gate bipolar transistors (IGBT) with a self-aligned deep diffusion p(super +) short is presented. Its viability is verified through a comparison of the forward conduction performance and balance with turn-off time between IGBTs with self-aligned shorts and non-self-aligned shorts. A demonstration of its implementation on a 600-V, symmetric-blocking, n-channel IGBT is also given.

Analysis of wide bandgap compound semiconductors for high frequency and high power unipolar electronic devices indicates that intermetallics, diamond and compounds such as AlN, ZnO, GaN and InN enhance the magnitude of on-resistance. The improvement in resistance facilitates high temperature operations.

The 1-kV 4H-SiC planar junction barrier Schottky (JBS) rectifiers were designed, fabricated, and characterized. Different p+ implantation dosages and activation anneal methods were used to determine an optimum baseline process. Using the optimized process, the forward drop of our JBS rectifiers is < 1.5 V while the reverse leakage current density is < 1 × 10-5 A/cm-2. Blocking voltage > 1 kV was achieved using a single-zone junction termination extension termination. It was shown experimentally that 4-μm p-type implantation window spacing gives an optimum tradeoff between forward drop voltage and leakage current density for these rectifiers, yielding a specific on-resistance of 3 mΩ ∙ cm². [ABSTRACT FROM AUTHOR]

A novel flip-chip flex-circuit packaging platform is described that enables integration of muItiple power dies and control circuitry with an advantageous form factor. A key attribute of this packaging platform is to extend the well-established flex-circuit and flip-chip soldering technologies in signal electronics to power electronics applications. The planar interconnection and flip-chip method facilitate multilayer packaging structure with reduced packaging dimensions and reduced packaging parasitics. A half-bridge test vehicle designed and fabricated for dc/ac inverter applications (42 V, 16 A) with an overall flex-circuit module footprint less than 30% that of a discrete device printed circuit board implementation has been modeled and demonstrated experimentally. Electrical results, confirmed with circuit shipulation incorporating parasitic inductance electromagnetic modeling, have shown a turn-off voltage overshoot reduction of over 40% and a switching energy loss reduction of 24% with the flip-chip flex-circuit implementation. The power flex platform has a strong potential for integrated multichip power module applications that require minimized packaging size and parasitic inductance for high switching frequency and efficiency. [ABSTRACT FROM AUTHOR]

The electrical characteristics of Schottky diodes fabricated on n-type epi layers regrown over an n-drift layer and regrown over a drift layer with selective boron-implanted p-type regions have been evaluated and compared to those on virgin, as-grown commercial epi-drift layers. Slightly lower (0.1-0.2 eV) Schottky barrier heights and larger ideality factors (1.2 vs. 1.03) were extracted for the regrown diodes from forward current-voltage and capacitance-voltage measurements. Although more than 1-2 orders higher reverse leakage current were also observed, our epi-regrowth process is still considered adequate for novel power device realization. [ABSTRACT FROM AUTHOR]

The electrical characteristics of both n- and p-type GaN metal-oxide semiconductor (MOS) capacitors utilizing plasma-enhanced CVD-SiO2 as the gate dielectric were measured. Both capacitance and conductance techniques were used to obtain the MOS properties (such as interface state density). Devices annealed at 1000°C/30 min. in N2 yielded an interface state density of 3.8 x 1010 cm-2 eV-1 at 0.19 eV from the conduction band edge, and it decreased to 1.1 x 1010 cm-2 eV-1 deeper into the band gap. A total fixed oxide charge density of 8 x 1012 q cm-2 near the valence band was estimated. Unlike the symmetric interface state density distribution in Si, an asymmetric interface state density distribution with lower density near the conduction band and higher density near the valence band was determined. [ABSTRACT FROM AUTHOR]

The profile of trap density at the SiO2/SiC interface in SiC metal-oxide semiconductor field-effect transistors (MOSFETs) is critical to study the channel electron mobility and evaluate device performance under various processing and annealing conditions. In this work, we report on our results in determining the interface trap density in 4H- and 6H-SiC MOSFETs annealed in dry O2, NO, and CO2, respectively, based on the device transfer and current-voltage characteristics in the subthreshold region at 25°C and 150°C. We also studied electron field-effect mobility, fixed oxide charge, and gate leakage in those devices. [ABSTRACT FROM AUTHOR]