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ispartof: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS vol:30 issue:11 pages:1748-1756 status: published

In state-of-the-art interconnect design, topologies including magnetic materials, such as the so-called superlattice conductors, are rapidly emerging as a novel strategy to handle the challenges associated with the evolution toward higher operating frequencies and integration densities. Consequently, it is imperative that the newly developed full-wave electromagnetic solvers rigorously model these innovative materials and still accurately capture phenomena such as the skin and proximity effect in good conductors. In this article, we propose such a method to rigorously characterize this important class of interconnects with arbitrary, possibly frequency-dependent, material properties, including combined dielectric and magnetic contrast. To that end, a 2-D differential surface admittance (DSA) operator is used, which invokes a single-source equivalence theorem to model both nonmagnetic and magnetic conductors efficiently. This operator is combined with the electric field integral equation (EFIE), yielding a comprehensive formalism to extract the pertinent per-unit-of-length (p.u.l.) resistance and inductance parameters of the modeled structures. The numerical properties of our technique are studied in detail, with particular attention to the influence of magnetic materials. Finally, various relevant application examples are considered to establish its correctness and versatility.

This letter describes the use of area-selective electroless Cu deposition for topography control of Cu-SiCN hybrid bonding pads. The electroless deposition of Cu allows one to obtain protrusions on hybrid bonding Cu pads without further polishing optimization. A recessed Cu pad after chemical mechanical polishing becomes a protrusion after electroless deposition. This indicates that the electroless Cu film was selectively deposited on Cu, without deposition on the SiCN surface. A void-free Cu-Cu bonding interface was observed after annealing at 350 °C with an electroless Cu layer at the interface. 100% electrical connection was obtained at 1.4- μm pitch where the deposition thickness was on target.

For a time, each new processor churned out more waste heat than the last. Had these chips kept on the trajectory they were following in the early 2000s, they would soon have packed about 6,400 watts onto each square centimeter-the power flux on the surface of the sun.

For die-to-wafer (D2W) stacking of high-density interconnects and fine-pitch microbumps, underfill serves to fill the spaces in-between microbumps for protection and reliability. Among the different types of underfill, nonconductive film (NCF) has the advantages of fillet and volume control. However, one of the challenges is the solder joint wetting. An NCF must have good embedded-flux activation to mitigate Cu UBM pad oxidation due to the repeated TCB cycles that accelerate oxidation on neighboring dice. The flux in the NCF also helps in wetting the solder bumps. To realize efficient solder wetting, one must also understand the NCF deformation quality, which is a function of its viscosity. This parameter has direct impact on the deformation of solder bumps. High-viscosity NCF would be difficult to deform, thus preventing solder contact to pad during TCB reflow temperature. High bond force is required and could lead to reduced alignment accuracy. For a low viscous NCF, it requires low bond force. Solder joint wetting is a challenge with excessive squeezeout due to fast and instantaneous deformation. We seek to demonstrate in this article a creative methodology for NCF material characterization, considering the factors of NCF viscosity, deformation, and solder squeezeout. We use TCB tool position-tracking data to define the deformation curve of the NCF as a function of temperature and time at very fast profile of TCB. We use the NCF viscosity curve as reference in relation to the actual deformation, and predict dynamic deformation in three different configurations. Deformation test configurations were performed on chips with and without microbumps bonded with a rigid flat glass surface and with a bottom Cu UBM pad. The experiments were performed with different heating ramp rates at target above Sn reflow of ~250°C interface temperature. As validation, we applied the optimized TCB process (force, temperature, and ramp rate) on a test vehicle with 20 and 40 μm pitch daisy chains and obtained very good connectivity with good joint and IMC formation.

We report a scanning photocapacitance microscopy technique for the localization of open electrical defects in hybrid bonding wafer-to-wafer (W2W) interconnect structures for 3-D system integration. Whereas the well-known optical beam induced resistance change (OBIRCH) method is effective for the localization of resistive opens and shorts, it cannot be applied on full electrical opens. Our approach uses a focused laser beam to stimulate the photocapacitance of the W2W interconnect, and by measuring its response, we can verify the electrical continuity of the structure. We show how illuminating the interconnects with the light of a suitable wavelength leads to an increase of the depletion capacitance due to carrier generation in the silicon substrate. Our measurement instrument uses a commercially available sigma-delta ( $\Sigma -\Delta$ ) capacitance-to-digital converter (CDC) chip with a capacitance sensing resolution down to 4 aF. We demonstrate this methodology on large open-failed W2W interconnect chains with sub-micrometer hybrid-bonded interconnect pad dimensions and confirm our results by optical and transmission electron microscopy (TEM).

This article presents a full-wave method to characterize lossy conductors in an interconnect setting. To this end, a novel and accurate differential surface admittance operator for cuboids based on entire domain basis functions is formulated. By combining this new operator with the augmented electric field integral equation, a comprehensive broadband characterization is obtained. Compared with the state of the art in differential surface admittance operator modeling, we prove the accuracy and improved speed of the novel formulation. Additional examples support these conclusions by comparing the results with commerical software tools and with measurements.

This article presents the design, fabrication, experimental characterization, and modeling analysis of the chip-level hotspot targeted liquid impingement jet cooling for high-power electronics. The hotspot targeted jet impingement cooling concept is successfully demonstrated with a chip-level jet impingement cooler with a 1-mm nozzle pitch and 300- $\mu \text{m}$ nozzle diameter fabricated using high-resolution stereolithography (additive manufacturing). The computational fluid dynamics (CFD) modeling and experimental analysis show that the improved hotspot targeted cooler design with fully open outlets can reduce the on-chip temperature difference by 70% compared with the full array cooler at the same pumping power of 0.03 W. The local heat transfer coefficient can achieve $15\times 10^{4}$ W/m2 K with a local flow rate per nozzle of 40 mL/min, requiring a pump power of 0.6 W. The benchmarking study proves that the hotspot targeted cooling is much more energy-efficient than uniform array cooling, with lower temperature difference and lower pump power.

In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented. A backside-PDN configuration contains dense microthrough silicon vias ( $\mu $ TSVs) and power/ground metal stack on the backside of the die. This approach separates the PDN from a conventional signaling network of the back-end-of-the-line (BEOL) and improves power integrity and core utilization. We benchmark this technology with conventional front-side BEOL PDN configurations. Owing to the lower resistivity compared with Cu metal lines for advanced technology nodes, we use ruthenium (Ru)-based buried power rail for PDN modeling. Our analysis shows that the steady-state IR-drop reduces by more than $4\times $ in the backside-PDN configuration, and a simultaneous switching noise analysis shows a significant reduction in transient droops. The framework results are validated with a place-and-route (P&R)-based physical implementation flow. We quantify the area improvement in the actual flow and observe 25%–30% improvement in the backside-PDN configuration. From a PDN modeling framework, the PDN results follow a trend similar to the ones obtained from the block-level P&R of the given configurations. Moreover, we investigate the impacts of package-to-die interconnect pitch, metal–insulator–metal cap density, and input pulse on the PDN performance. In addition, we perform thermal modeling to analyze the thermal implications of the backside-PDN configuration. From a thermal modeling perspective, there is negligible influence from a dielectric bonding layer in the backside-PDN configuration.

This paper describes optical and electron beam based fault isolation approaches for short and open defects in nanometer-scale through-silicon via (TSV) interconnects. Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in a scanning electron microscope (SEM). The results are confirmed by transmission electron microscopy (TEM) cross-sectioning.

This paper reports on 3D phase field simulations of IMC growth in Co/Sn and Cu/Sn solder systems. In agreement with experimental micrographs, we obtain uniform growth of the CoSn3 phase in Co/Sn solder joints and a non-uniform wavy morphology for the Cu6Sn5 phase in Cu/Sn solder joints. Furthermore, simulations were performed to obtain an insight in the impact of Sn grain size, grain boundary versus bulk diffusion, IMC/Sn interface mobility and Sn grain boundary mobility on IMC morphology and growth kinetics. It is found that grain boundary diffusion in the IMC or Sn phase have a limited impact on the IMC evolution. A wavy IMC morphology is obtained in the simulations when the grain boundary mobility in the Sn phase is relatively large compared to the interface mobility for the IMC/Sn interface, while a uniform IMC morphology is obtained when the Sn grain boundary and IMC/Sn interface mobilities are comparable. For the wavy IMC morphology, a clear effect of the Sn grain size is observed, while for uniform IMC growth, the effect of the Sn grain size is negligible.

The chip-level bare die direct liquid impingement jet cooling is regarded as a highly efficient cooling solution for high-performance applications. Furthermore, it shows potential to be integrated inside the chip package. In previous studies, we demonstrated this cooling concept using a prototype fabricated with mechanical micromachining using polymers. With the improvement of fabrication resolution, additive manufacturing or 3-D printing technology enables the fabrication of low-cost polymer microjet coolers with complex internal 3-D geometries and allows easy customization of the cooler design. In this paper, a chip-level impingement jet cooler with a $4 \times 4$ jet array and 575- $\mu \text{m}$ nozzle diameter is fabricated with high-resolution stereolithography, and assembled directly on the top of the bare die. The modeling study shows that the pressure drop in the 3-D printed cooler is reduced by 24% compared to the micromachined (MM) cooler with the same nozzle dimensions thanks to an improved more complex internal geometry. The fabrication quality and tolerances of the printed cooler are evaluated using optical measurements, scanning acoustic microscope (SAM) inspection, and cross-sectional analysis, showing a measured average nozzle diameter of 575 $\mu \text{m}$ compared to the designed nozzle diameter of 600 $\mu \text{m}$ . Moreover, the 3-D computational fluid dynamics (CFD) simulations used in this paper are experimentally validated by chip temperature measurements. The achieved minimal thermal resistance of 3-D printed $4 \times 4$ cooler is 0.16 cm $^{2}\cdot \text{K}$ /W for a flow rate of 1000 mL/min. The benchmarking study shows the cooler size can be reduced by a factor of 6.5 by using the 3-D printing technology compared to the MM cooler.

ispartof: ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY vol:8 issue:6 pages:P346-P350 ispartof: location:MEXICO, Cancun status: published

Silicon carbon nitride (SiCN) compounds have aroused great interest as dielectric materials for direct bonding because of the high thermal stability and high bond strength, as well as its Cu diffusion barrier properties. While wafer-to-wafer direct bonding, including the dielectric deposition step, is generally performed at high temperature (>350 °C), applications such as heterogeneous chips and DRAMs would require wafer-to-wafer direct bonding at lower temperature (

Package level bare die jet impingement cooling on the chip backside has been previously demonstrated as a highly efficient jet cooling solution for high power devices, by eliminating the thermal interface material. However, bare die jet impingement cooling is a disruptive cooling technology requiring direct access to the backside of the semiconductor device. A less disruptive cooling implementation in which the impingement cooling is applied on the lid is now investigated as an intermediate step. In this work, the first comparison of the cooling performance with the liquid micro-jet array impingement cooling on lidded and bare die package is conducted and experimentally characterized for polymer coolers fabricated by additive manufacturing. The thermal characterization is performed on a 2.5D integrated system that contains two advanced thermal test dies. In addition, besides the reference cooler with vertical coolant supply channel, an improved design of 3D printed fluid delivery manifold with lateral inlet/outlet channels is introduced and benchmarked. The experimental and numerical comparison show that the cooler with the lateral feeding manifold requires 60% less pumping power with respect to the vertical feeding manifold for the same high thermal performance while reducing the overall thickness of the cooling solution by a factor of 2.

Jet impingement cooling with distributed outlet configuration is regarded as an efficient cooling solution for high performance systems. This work develops the Nusselt number Nu ¯ f - R e d and pressure drop k -factor correlations for microscale multi-jet impingement cooling with alternating feeding and draining jets. An extensive design of experiments (DOE) of unit cell modeling-based simulations is used for the correlation fitting. In order to understand the flow and thermal behavior, the impact of single variables including the inlet diameter, outlet diameter, jet-to-target distance and nozzle length is studied systematically. On the other hand, this work firstly shows the predictive model with k - R e d , including the impact of nozzle length t/L, cavity height H/L and inlet diameter ratio d i /L. Finally, the extracted correlations are experimentally validated, both with experimental data of different jet impingement demonstrators, as well as with the literature experimental data.

The metal–insulator–semiconductor capacitor formed by a through-silicon via (TSV) with its insulating layer and the p-type Si substrate may show an anomalous inversion behavior in the ${C}$ – ${V}$ characteristic. The dominant cause is the presence of positive charges in the backside (BS) passivation layer. In this paper, a dedicated test structure is proposed and characterized to confirm this hypothesis. Furthermore, a charge-free oxide/nitride BS passivation layer for preventing the anomalous ${C}$ – ${V}$ inversion, proposed in our previous work, is validated by experimental results on TSV structures manufactured up to the complete BS metallization processing.

Liquid microjet impingement cooling has shown the potential to be the solution for heat removal from electronic devices such as very-large-scale integration (VLSI) chips. The post-impingement dynamics of the jet, specifically the interaction between the liquid fronts on the surface engendered by the jets is a critical criterion improving the heat transfer characteristics. While some seminally important experimental studies have investigated this attribute, the amount of accurate data and analysis is limited by the shortcomings of real-life experiments. In this article, numerical investigations into the fluid dynamics and heat transfer in microjet cooling systems are carried out. Specifically, this paper addresses the question regarding the necessary fidelity of the simulations. Different Reynolds-averaged Navier&ndash, Stokes (RANS) models are compared to the Large Eddy Simulations (LES) simulation and the potential fidelity of different eddy-viscosity-based closures is clearly shown. Recommendations are made regarding the RANS closures that should give the best performance. It is demonstrated that the transition Shear Stress Transport (SST) model and k - &omega, SST model both show excellent ability to predict the local or average Nu, and also local level pressure coefficient f with less than 5% difference in the range of 30 &lt, Red &lt, 4000, compared with the reference LES model. For the experimental measurements in the range of 130 &lt, 1400, the LES model, transition SST model and k - &omega, SST model all show less than 25% prediction error. Moreover, it is shown that the validity of the unit cell assumption for the temperature and flow distribution depends on the flow rate.

© 1986-2012 IEEE. A high-efficiency three-dimensionally (3-D) shaped polymer multi-jet impingement cooler based on cost-efficient fabrication techniques is introduced for the cooling of high-power applications. State-of-the-art highly efficient multi-jet cooling solutions rely on expensive Si or ceramic fabrication techniques, while low-cost cooling solutions have been proposed for less performant single-jet impingement. In this paper, we present the concept, modeling, design, fabrication, experimental characterization, and benchmarking with literature data of a multi-jet impingement based liquid cooling solution, fabricated using low-cost polymer fabrication techniques, targeted to directly cool the backside of high-power devices. For the modeling study, unit cell model and full system level models are used to study the nozzle array scaling trends and thermal and fluidic jet-to-jet interactions. Furthermore, design guidelines for high-power electronics cooling are provided, including geometry selections, material selection, and fabrication techniques. Based on the design guidelines and cooling concept, this paper demonstrates a 3-D-shaped polymer impingement cooler with a 4 × 4 nozzle array, showing a very good thermal performance with low required pumping power. The multi-jet cooler can achieve heat transfer coefficients up to 6.25 × 10 4 W/m 2 ·K with a pump power as low as 0.3 W. The benchmarking study confirms furthermore that multi-jet cooling is more efficient than single-jet cooling and that direct cooling on the backside of the semiconductor device is more efficient than cooling the substrate or base plate. ispartof: IEEE TRANSACTIONS ON POWER ELECTRONICS vol:34 issue:7 pages:6601-6612 status: published

High efficiency direct liquid jet impingement cooling with locally distributed outlets is very promising in high power electronic devices. In order to elucidate the flow-thermal interaction for micro-scale jet impingement cooling, sensitive temperature measurements with high spatial and temporal resolution are required. In this work, a programmable thermal test chip with 832 heater cells with 75% heater uniformity and 3232 array of temperature sensors is introduced. The detailed measured temperature maps for different power dissipation patterns allow the in-depth study of the thermal performance of liquid jet impingement coolers and the detailed experimental validation of complex CFD models. The modeling and measurement study is applied to two jet impingement cooling implementations: 1) a single jet cooler with a 2 mm diameter nozzle, and 2) a multi-jet cooler with a 4×4 array of 500 µm inlet nozzles and distributed outlet nozzles. For both cooler configurations, the temperature measurements and CFD modeling results are investigated and compared for uniform and hot spot power dissipation patterns. ispartof: APPLIED THERMAL ENGINEERING vol:152 pages:308-318 status: Published online

This paper demonstrates the application of GHz-SAM for the detection of local non-bonded regions between micron-sized Cu-pads in a wafer-to-wafer hybrid bonded sample. GHz-SAM is currently the only available non-destructive failure analysis technique that can offer this information on wafer level scale, with such high resolution.

© 2018 IEEE. Liquid jet impingement cooling is a very efficient cooling technology for high performance devices. Previous studies demonstrated that polymers can be used as a cost effective alternative for Si for the fabrication of impingement coolers. The recent developments in additive manufacturing or 3D printing technology enable the potential to fabricate low cost polymer coolers with complex internal channels. In this paper, the use of 3D printing is discussed for the fabrication of a chip level polymer impingement cooler. The paper presents the cooler design, the manufacturability aspects and the characterization of several 3D printed coolers with different nozzles arrays. The challenges and opportunities for the use of 3D printing for this applications are discussed. A methodology to provide design guidelines for 3D printed liquid impingement jet coolers is elaborated. ispartof: pages:2389-2396 ispartof: 2018 IEEE 68th Electronic Components and Technology Conference vol:2018-May pages:2389-2396 ispartof: 2018 IEEE 68th Electronic Components and Technology Conference location:San Diego date:29 May - 1 Jun 2018 status: Published online

© 2017 IEEE. A novel 3D-shaped polymer multi-jet impingement cooler based on low cost fabrication techniques is introduced for high performance applications. This paper presents the modeling study, design, fabrication, experimental characterization and benchmarking of this cooling concept, showing a very good thermal performance with low required pumping power. ispartof: pages:733-736 ispartof: 2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) pages:733-736 ispartof: 63rd IEEE Annual International Electron Devices Meeting (IEDM) location:San Francisco: CA date:2 Dec - 6 Dec 2017 status: published

© 2016 IEEE. 3D interposers are one of just a few ways of making electronic systems faster and more powerful, but their design can be complex. This paper presents a optimization flow to assist the design of silicon interposers with the highest bandwidth density possible. Using the methodology described in this paper, simulations have shown that chip-to-chip links on a silicon interposer can achieve bandwidth densities between 250Gbps/mm and 4.5Tbps/mm depending on a wide range of parameters such as interconnect length, interlayer dielectric (ILD) material and micro-bump pitch. ispartof: pages:1-6 ispartof: 2016 6TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC) issue:1 pages:1-6 ispartof: Electronic System-Integration Technology Conference (ESTC) location:Grenoble France date:13 Sep - 15 Sep 2016 status: published

© 2016 IEEE. The introduction and use of ultra low-k dielectric materials in an attempt to achieve better die performance brought new challenges to the wafer singulation / dicing process. Ultra low-k dielectric materials can easily get damaged during conventional blade dicing due to their brittleness. Thus, there is a need to investigate alternative or more advanced dicing techniques that can deliver successful dicing processes without inducing stress or damage. Apart from looking at the compatibility of the different dicing techniques with (ultra) low-k dielectric materials, the integration of these different dicing techniques into the different 3D-Technology configurations was also investigated. This paper reports on the post dicing results and the challenges for 3D technology for the following different dicing technologies: blade dicing, laser grooving + blade dicing, laser grooving + plasma dicing, stealth dicing, plasma dicing, and laser full cut dicing. ispartof: pages:1247-1258 ispartof: 2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) vol:2016-August pages:1247-1258 ispartof: 66th IEEE Electronic Components and Technology Conference (ECTC) location:Las Vegas: NV date:31 May - 3 Jun 2016 status: published

The relevance of accurate prediction of the thermal behavior of microelectronic systems has been increasing since the introduction of 3D-ICs. Different modeling strategies have been implemented to this scope, aiming both to increase accuracy and to reduce computational time. In this paper, a transient fast thermal model methodology for packaged 3D stacked ICs is presented. It can be considered as a multi-scale strategy whose core is constituted by a highly resolved, convolution based algorithm. This allows to compute the temperature increase due to a generic, time varying, power map in a stack configuration. On top of this, the time dependent package thermal spreading and capacitive effect is included via correction profiles. These corrections are based on the ratio between the thermal responses of the package and of the stack configurations to uniform, impulsive, power dissipation at different time steps. Validation with respect to finite element method results shows good accuracy. An error metric, to estimate a priori the need to include the package impact on top of the convolution based approach, has also been developed. Alternative but similar algorithms, which place themselves in between the solutions with and without the package impact, both from an accuracy and from a computational time point of view, are also shortly presented in this work. ispartof: IEEE Transactions on Components, Packaging and Manufacturing Technology vol:6 issue:3 pages:424-431 status: published

In this study, the role of electrodeposition chemistry on thermo-mechanical behavior of different Cu-films is examined. For this study, three different Cu electrodeposition chemistries were analyzed using Time-of-Flight Secondary Ion Mass Spectroscopy (TOF-SIMS), Focused Ion Beam (FIB), Laser Scanning method, Electron Backscattered Diffraction, and the Nano-indentation techniques. It is found that the level of impurity in Cu-films, resulting from the used electrodeposition additives, has a significant impact on their microstructural and thermo-mechanical behavior. Cu-films having high impurity content showed residual stress levels that are three times higher than the less impure Cu-films. This implies that the use of such impure electrodeposition chemistry for the filling of TSVs will result in high residual stresses in the Cu–TSV, thus inducing higher stresses in Si, which could be a reliability concern. Therefore, the choice of the used electrodeposition chemistry for the filling of TSVs should not be limited only to the achievement of a void free Cu–TSV, as consideration ought to be given to their thermo-mechanical response.

© 2015 IEEE. High speed TSV signals can penetrate through the dielectric liner material, transfer in the silicon substrate and degrade the performance of FEOL devices. In this paper we investigate TSV noise coupling to active device including both FinFET and planar transistors. Calibrated TCAD models are used to perform time domain analysis and understand the mechanisms of substrate noise interaction with active device. Parametric simulations are performed in order to understand the tradeoffs among different design parameters. The results demonstrate superior substrate noise immunity of FinFETs over equivalent planar transistors. In addition we show that a scaled TSV diameter, a novel TSV architecture with thick polymer liner, placing the substrate contact closer to active device and a TSV guard ring helps to mitigate the TSV noise. Finally the importance of electromagnetic coupling effects on Keep Out Zone (KOZ) extraction is illustrated. ispartof: pages:1-4 ispartof: 2015 INTERNATIONAL CONFERENCE ON IC DESIGN & TECHNOLOGY (ICICDT) pages:1-4 ispartof: 2015 IEEE International Conference on Integrated Circuit Design & Technology (ICICDT) location:BELGIUM, Leuven 2015 status: published

© 2015 IEEE. Through Silicon vias (TSVs) are a key breakthrough in 3D technology to shorten global interconnects and enable the heterogeneous integration. However, TSVs also introduce an important source of noise coupling arising from electrical coupling between TSVs and the active devices. This paper investigates the TSV noise coupling to active devices including both FinFETs and planar transistors based on two-port S-parameter measurements up to 40 GHz. The measurements clearly show that nFinFETs have better noise coupling immunity than planar nNMOSFETs. The dominant coupling mechanisms were also identified for both types of active devices. Moreover, calibrated TCAD models were developed. We show that via-last TSV architectures with thick liners ('donut TSVs') and scaled TSV diameters reduce the noise coupling to active devices. Finally, both coupling and stress induced saturation current variations as a function of TSV to active devices distance were investigated. This allows us to propose a novel model for the TSV Keep Out Zone (KOZ) including electromagnetic coupling effects. ispartof: pages:260-265 ispartof: 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) vol:2015-July pages:260-265 ispartof: 2015 Electronic Components & Technology Conference location:CA, San Diego date:26 May - 29 May 2015 status: published

© 2015 IEEE. In this work the mechanical stress induced in 3D stacks by different packaging process steps is studied. The 3D stacks used in this work are assembled using two identical dies containing a number of stress sensors which are designed and manufactured in 65nm technology. It is observed that the contribution of the package substrate and the die-attach process to the redistribution of mechanical stress inside the 3D stacked IC is more significant than the one of the EMC and that the influence of packaging on the shape and amplitude of local stress around the inter-die interconnects (micro-bumps) is not significant. These observations are supported by the measurements of stress done using micro-Raman spectroscopy and are correlated with the results of finite element modeling and with optical warpage measurements of different packaging configurations. ispartof: pages:354-361 ispartof: IEEE vol:2015-July pages:354-361 ispartof: 2015 Electronic Components & Technology Conference (ECTC) location:CA, San Diego date:26 May - 29 May 2015 status: published

A thorough thermal analysis of integrated circuits (ICs) is essential to prevent temperature driven reliability issues, which might cause the failure of microelectronic devices. The classical analysis approach is based on finite element methods (FEM). However, in the last decades, other computational methodologies have been developed with the aim to obtain results more quickly and at a reasonable accuracy. In this paper, a transient fast thermal model (TFTM) methodology for 3DICs based on 3D-convolution and fast Fourier transform is presented. This methodology allows to quickly and accurately predict the temporal evolution of the chip temperature distribution, due to power dissipation that can be non-uniform both in time and space, in all tiers of the 3D package. In the first part of the paper the computational methodology is derived and described. Next, results are presented and validated with respect to conventional FEM simulations, showing good accuracy and computational time reduction. A realistic case, wherein different load switching scenarios are compared for a commercial floor-plan, is analyzed as an example of the applicability of the presented methodology. The speed of this algorithm, based on 3D-convolution, is compared with the one of previous work based on 2D-convolution and subsequent time superposition. ispartof: pages:107-112 ispartof: Thermal Measurement, Modeling & Management Symposium (SEMI-THERM), 2015 vol:2015-April pages:107-112 ispartof: SemiTherm, 31st Thermal Measurement, Modeling & Management Symposium location:San Jose, CA, USA date:15 Mar - 19 Mar 2015 status: published

Recent results of the autonomous sensor research program HUMAN++ will be summarized in this paper. The research program aims to achieve highly miniaturized and (nearly) autonomous sensor systems that assist our health and comfort. Although the application examples are dedicated to human monitoring/assistance, the necessary technology development for this program is generic and can serve many wireless sensor applications. This multi-disciplinary program combines research on wireless ultra-low-power communications, research on 2D/3D integration and packaging platforms, energy scavenging techniques, as well as low-power and ultra-low-power sensor circuit design. An example sensor system is the wearable wireless EEG system. © 2006 Elsevier Ltd. All rights reserved.

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.

In this paper, a generalized deembedding technique is presented. It provides a multimodal characterization for microwave devices fed with planar guiding structures of arbitrary configurations. Instead of the conventional scattering matrix, the proposed technique leads to the multimodal scattering matrix. This matrix describes all possible kinds of mutual coupling between the different modes present on the feeding ports. In order to achieve this task, the feeding planar guiding structures are analyzed a priori using a full-wave two-dimensional solver. The generalizability of the proposed deembedding technique is demonstrated by characterizing a couple of coplanar-waveguide-based discontinuities. The results show that the proposed technique provides a rigorous and a detailed characterization.

In this paper, a generalized two-dimensional formulation for solving planar guiding structures is presented. The formulation is capable of analyzing guiding structures consisting of an arbitrary number of slots and strips with arbitrary width, thickness, and conductivity in a full-wave regime. Integral equations solved with the method of moments in the spatial domain are used in the analysis. All information related to the fundamental modes of the guiding structure are available from the presented theory. This information includes (for each mode) the propagation constant, electric and magnetic current distribution, modal power, and the characteristic impedance. Numerical results for a number of planar guiding structures are presented, which validate the proposed theoretical formulation.

Thermal aware design of integrated circuits is essential to avoid reliability issues and failures especially in 3D-technology where active dies are placed on top of each other and more heat is dissipated on the same area available for cooling compared to conventional 2D-packages. A certain number of parameters can be selected to reduce temperature and temperature gradient. This paper is mainly focusing on the thermal impact of the die-to-die interface layer. This consists of adhesive material and arrays of interconnection structures. Besides being used for electrical die-die connections, they can be added to locally improve the low thermal conductivity of the adhesive. Short computational time is preferred for the thermal analysis of different designs: this is why various compact thermal models (CTMs) strategies have been developed. The one presented here, for the steady state temperature evaluation of two dies stacks, is based on convolution and fast Fourier transform. A novel correction methodology is introduced to deal with the material non-homogeneity in the interface layer. Case analyses, as the interface material thermal impact or the maximum achieved temperature as a function of the amount of interconnections, are presented in the paper and can be quickly and easily performed with this CTM. ispartof: pages:98-106 ispartof: Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2014 IEEE Intersociety Conference on pages:98-106 ispartof: ITHERM location:Orlando, FL USA date:27 May - 30 May 2014 status: published

Degraded liner/barrier integrity is observed in 3D Cu through silicon via systems using a sub-atmospheric chemical vapor deposition O3/tetraethyl orthosilicate (TEOS) oxide liner and a physical vapor deposition Ta barrier. By analyzing the data of thermal desorption spectroscopy and Fourier transform infrared spectroscopy, the source of the degradation is found to be outgassed hydrogen from the liner. To overcome this hydrogen induced degradation, three alternative liner/ barrier schemes are proposed and validated: 1) a capped O3/TEOS liner, 2) a metal barrier that is resistant to hydrogen, and 3) a denser oxide liner. ispartof: Applied Physics Letters vol:104 issue:14 pages:1-3 status: published

In the current trend toward portable applications, high-Q integrated inductors are gaining a lot of importance. Using thin-film multilayer or multichip-module-deposition technology, high-Q circular inductors for RF and microwave applications may be integrated efficiently. Their quality factors may go up to over 100. In this paper, an accurate analytical model for such multiturn circular spiral inductors embedded in a thin-film multilayer topology is presented. Starting from the geometrical parameters, the model provides an accurate prediction of the inductance value, Q factor and frequency behavior of the inductor. This allows a "first-time-right?" realization of the integrated component and provides opportunities for fast optimization of the inductors. Finally, the presented high-Q inductors have been used in various integrated RF and microwave subsystems for wireless applications, of which a number are discussed at the end of this paper.

A variety of microelectromechanical system devices requires encapsulation of their crucial fragile parts in a hermetically sealed cavity for reasons of protection. Hermeticity of the cavity and controllability of the ambient (gas pressure and gas composition) can be critical to the device performance. In order to minimize damage during handling, the cavity is preferably realized at the same time the device is fabricated, i.e., at wafer level. This paper reports the development of a hermetic packaging technique satisfying all the above. The method is referred to as the indent-reflow-sealing (IRS) technique, which relies on a multiple-chip fluxless solder-based joining technique and seal. Key process steps are the creation of an indent in the solder, the plasma pretreatment of the bonding surfaces, the pre-bonding (or sticking) of the chips and, the closing of the indent during a low-temperature (220/spl deg/C-350/spl deg/C) solder reflow in a clean controlled ambient using a designated oven. As opposed to other methods, the IRS method allows a greater flexibility with respect to the choice of the sealing gas and pressure, thereby offering a very hermetic seal and compatibility with low-cost high-throughput batch fabrication techniques. Flip-chip assemblies based on SnPb (67/37) solder and Au as the top surface metallization, have been reflowed in a forming gas ambient and have next been characterized on shear strength, hermeticity, and susceptibility to thermal stresses. The method has been successfully implemented in the process flow of an electromagnetic microrelay for the realization of the cavity housing the electrical contacts.

In this paper, the design, fabrication, and characterization of planar antenna arrays in the MCM-D technology are presented. The arrays are fed by coplanar feeding networks built using coplanar-waveguide lines. 2/spl times/2 and 4/spl times/4 arrays of slot dipoles designed to work in K-band, around 25 GHz, are also presented. The analysis was carried out both theoretically and experimentally. The results include the return loss, radiation patterns, and antenna gain. The proposed arrays are compatible with the driving electronics technology, enjoying high-impedance bandwidth, low cross polarization, high gain, and high radiation efficiency.

In this paper, the design and realization of coplanar Lange couplers integrated in a multilayer thin-film multichip module deposition (MCM-D) technology is discussed. The MCM-D technology has been well established for the interconnection of high-speed digital circuits, and is now being recognized to be very useful for the integration and interconnection of microwave components. In this way, passive structures, such as spiral inductors, filters, and couplers, may be realized efficiently and more cost effective in MCM-D compared to monolithic microwave integrated circuits. The presented coplanar Lange couplers have been designed using an equivalent coupled-line model. A general and computationally efficient method for the determination of the required modal characteristic impedances and the related geometrical parameters in a microwave multilayer coupled-line topology is presented. Also, a way to calculate the optimum coupled line length is given. Using the described method, coplanar Lange couplers have been realized and then measured. Comparison between the measurement results and HP Momentum simulations show good agreement and indicate the feasibility of designing and integrating such components in MCM-D.

Multislot planar transmission lines are analyzed using a mixed-potential integral-equation formulation solved by the method of moments. Closed-form Green's functions for horizontal magnetic filaments are obtained using the discrete complex image in conjunction with the two-level approximation scheme. The calculations are applied on the specific case of the multislot lines built in the microwave multichip-module deposition technology. The effect of the thin dielectric films on the propagation and the dispersion characteristics is investigated. This effect was found to be significant and mode dependent. Numerical results for the modal currents and dispersion curves are also presented.