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Non-planar Fin Field Effect Transistors (FinFET) are already present in modern devices. The evolution from the well-established 2D planar technology to the design of 3D nanostructures rose new fabrication processes, but a technique capable of full characterization, particularly their dopant distribution, in a representative (high statistics) way is still lacking. Here we propose a methodology based on Medium Energy Ion Scattering (MEIS) to address this query, allowing structural and compositional quantification of advanced 3D FinFET devices with nanometer spatial resolution. When ions are backscattered, their energy losses unfold the chemistry of the different 3D compounds present in the structure. The FinFET periodicity generates oscillatory features as a function of backscattered ion energy and, in fact, these features allow a complete description of the device dimensions. Additionally, each measurement is performed over more than thousand structures, being highly representative in a statistical meaning. Finally, independent measurements using electron microscopy corroborate the proposed methodology.

The use of plasma immersion ion implantation (PIII) is a relevant approach for the development of advanced solar cells technologies at lower cost (€/W p ). In this paper, we report on the development of homogeneous boron (B) doping of n-type crystalline silicon (cSi) substrate by the PIII technique. Using diborane (B 2 H 6 ) as gas precursor, various doping profiles were identified fitting the requirements for boron-doped emitters in n-type PERT solar cells. Particularly, saturation current density (J 0e ) of 50 fA/cm 2 were achieved on symmetrical samples for a 94 Ω/sg textured B-emitter passivated with SiO 2 /SiN stack. Bifacial n-type Passivated Emitter Rear Totally-diffused (n-PERT) solar cells were fabricated using the PIII technology and conversion efficiencies up to 19.8% on 239 cm 2 Cz-Si wafers were obtained. As a consequence, these results indicate that PIII can compete with beamline technology but will have lower running cost. It is therefore a promising technology to create high efficiency cSi solar cells.

International audience

International audience; The interaction of a propagating crack in implanted silicon with self-emitted acoustic waves is studied and reveals the generation of periodic patterns on wafers surfaces after separation. The measurement and identification of the acoustic waves have been experimentally achieved showing the emergence of dominant shear waves acoustic frequencies related to the crack velocity. The surface modifications are made of roughness modulations at large scale due to periodic deviations of the crack front. A physical mechanism explaining the pattern formation is proposed accounting for the observed wavelengths.

In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer.

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The Smart CutTM technology has been used for LiTaO3 layer transfer. A 3-inch full wafer single-crystal LiTaO3 layer onto a carrier wafer comprising a metallic electrode is reported.

The formation and detailed characterisations of a 200 mm germanium-on-insulator substrate made from germanium bulk material as donor wafer using the Smart Cut TM technology is reported. Detailed characterisations of final GeOI structures are presented: final roughness, defectivity evaluation, thickness measurement, and electrical characterisation.

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low- ${k}$ (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted.