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INTERNET BUSINESS NEWS-(C)1995-2019 M2 COMMUNICATIONS Health Quest Systems Inc., a four-hospital health system operating in New York's Hudson Valley and northwest Connecticut, and IBM Watson Health (NYSE: IBM) have entered [...]

For many years now, IBM and others have sponsored competitions between human experts and computers. While some might dismiss the value of these events, they do serve as milestones for [...]

The IBM soft-error Monte Carlo model SEMM-2 is a new general-purpose simulation platform developed for single-event-effect (SEE) analysis of advanced CMOS (complementary metal-oxide semiconductor) technologies. The current status and major features of this system are presented in this paper, including the physics model modules for the relevant atomic and nuclear processes, the construction and application of databases, and the simulation methodologies used to solve general transport problems. SEE analysis can be carried out for a large class of radiation subatomic particles in arbitrarily complex geometries and material composition of the integrated circuit designs.

We are inspired by the beauty and simplicity of self-organizing materials and the promise they hold for enabling continued improvements in semiconductor technology. Self assembly is the spontaneous arrangement of individual elements into regular patterns; under suitable conditions, certain materials self organize into useful nanometer-scale patterns of importance to higher-performance microelectronics applications. Polymer self assembly is a nontraditional approach to patterning integrated circuit elements at dimensions and densities inaccessible to traditional lithography methods. We review here our efforts in IBM to develop and integrate self-assembly processes as high-resolution patterning alternatives and to demonstrate targeted applications in semiconductor device fabrication. We also provide a framework for understanding key requirements for the adoption of polymer self-assembly processes into semiconductor technology, as well as a discussion of the ultimate dimensional scalability of the technique.

The Cell Broadband Engine[TM] (Cell/B.E.) processor is the first implementation of the Cell Broadband Engine Architecture (CBEA), developed jointly by Sony, Toshiba, and IBM. In addition to use of the Cell/B.E. processor in the Sony Computer Entertainment PLA YSTA TION[R]3 system, there is much interest in using it for workstations, media-rich electronics devices, and video and image processing systems. The Cell/B.E. processor includes one PowerPC[R] processor element (PPE) and eight synergistic processor elements (SPEs). The CBEA is designed to be well suited for a wide variety of programming models, and it allows for partitioning of work between the PPE and the eight SPEs. In this paper we show that the Cell/B.E. processor can outperform other modern processors by approximately an order of magnitude and by even more in some cases.

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers. This process provides the shortest distance between the stacked layers ([10.sup.8] vias/[cm.sup.2]), and extremely aggressive wafer-to-wafer alignment (submicron) capability.

Magnetic random access memory (MRAM) technology, based on the use of magnetic tunnel junctions (MTJs), holds the promise of improving on the capabilities of existing charge-based memories by offering the combination of nonvolatility, speed, and density in a single technology. In this paper we review rapid-turnaround methods which have been developed or applied in new ways to characterize MRA M chips at various stages during processing, with particular emphasis on the MTJs. The methods include current-in-plane tunneling (CIPT), Kerr magnetometry, vibrating sample magnetometry (VSM), and conducting atomic force microscopy (CAFM). Use of the methods has enabled rapid learning with respect to the materials used for the MTJs, as well as tuning o/the MTJ geometry in terms of size and shape and of the patterning methods employed. Examples of the use of each of the methods are presented along with interpretation of the data via critical operating parameters.

Other submitted technologies with a notable potential are: aPriori Cost Management Platform (aPriori Technologies Inc., Concord, Mass.) targets the need for real-time, predictive cost assessments throughout product development. Use the […]

The IBM eServer[TM] BladeCenter[R] system was conceived in the fall of 1999 by members of the IBM xSeries[R] server brand technical team (at the time, called the Netfinity[R] brand). It was a new idea, and for some, too revolutionary to consider. After considerable end-user feedback, technical refinement, and internal discussion and debate, the concept was developed into a leadership server product. This paper provides a brief historic overview of the development of the architecture and blade servers, and a technical description of the BladeCenter system and technology.

WHAT'S THE NEXT BIG THING? That should be the perfect question for the senior vice president in charge of technology and manufacturing at the world's premier technology corporation. For nearly […]

Historically, development tools have been tied to a specific operating system. Yet, some vendors have seen success in building products that target multiplatforms. A new phenomenon, a modular open-source project […]

As long as paper forms--checks, invoices and legal documents--remain a convenient and cost-effective manner of conveying information, banks can hardly expect to remove paper from the financial system. That's where […]

AS WE APPROACH the pervasive-computing vision, embedded appliances will take on a more comprehensive role, allowing users to act on information from any place, at any time, and on and [...]

In 2001, IBM delivered to the marketplace a high-performance UNIX[R]-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-[micro]m pads on 200-[micro]m centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm x 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

The design and performance of land grid array (LGA) sockets are discussed with respect to high-performance server applications. Motivations for the use of this technology are presented, and the specific challenges associated with its application are discussed from a mechanical perspective. A variety of mechanical performance considerations are identified for LGA socket technologies, and a detailed evaluation of competing socket-actuation designs is presented using finite element structural analysis. Some design approaches are shown to suffer from excessive mechanical flexure, which can consume the allowable range of motion of the contact, resulting in excessive contact load variation within the LGA. Statistical considerations for the mechanical deflections and tolerances that contribute to range-of-motion consumption are developed using Monte Carlo techniques, and a parametric study of the mechanical design variables that influence contact load variation within the LGA is presented.

This paper provides an overview of the power, packaging, and cooling aspects of the IBM eServer z900 design. The semiconductor processor chips must be supported and protected in a mechanical structure that has to provide electrical interconnects while maintaining the chip junction temperature within specified limits. The mechanical structure should be able to withstand shock and vibrations during transportation or events such as earthquakes. The processor chips require electrical power at well-regulated voltages, unaffected by the ac-line voltage and load current fluctuations. The acoustical and electromagnetic noise produced by the hardware must be within the limits set by national regulatory agencies, and the electronic operations must be adequately protected from disruption caused by electromagnetic radiation. For high availability, the power, packaging, and cooling hardware must have redundancy and the ability to be maintained while the system is operating. This paper first overviews the packaging hardware, followed by a description of the first- and second-level packaging, which includes the mother board and the multichip module. Thermal management is discussed from the point of view of both the multichip module and the overall system. Power conversion, management, and distribution are presented next. Finally, the design aspects involved with meeting the requirements of electromagnetic compatibility, acoustics, and immunity to shock, vibration, and earthquakes are discussed.

The paper describes the need for early analysis tools to enable developers of today's system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic[R] Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs and outline how this performance analysis capability can be integrated into an overall environment for efficient SoC design.

The IBM S/390[R] G4 CMOS system, first shipped in 1997, was the first high-end system to use refrigeration. The decision to employ refrigeration cooling instead of other cooling options such as high-flow air cooling or various water-cooling schemes focused on the potential system performance improvement obtainable by lowering coolant temperatures using a refrigeration system. This paper reviews the historical background of refrigeration from its use in the early 1800s to its implementation in computer systems in the early 1990s. The advantages and disadvantages of using refrigeration in the cooling of computer systems are examined. The advantages have outweighed the disadvantages, leading to the first use by IBM of refrigeration in cooling the S/390 G4 server. The design of the refrigeration system for the S/390 G4 system is described in detail, and some of the key parametric studies that contributed to the final design are described.

System performance of an IBM RS/6000[R] workstation was improved by cooling to sub-ambient temperatures the CMOS circuits of a single-chip module (SCM) mounted on a card. However, when refrigeration temperatures are sufficiently low, the temperature of all or a portion of the card on which the module is mounted can fall below the environmental dew point, resulting in unwanted condensation. Strategically placed heaters can maintain the temperature of the card surface above the dew point, but at the expense of increasing the total heat load the refrigeration unit must remove from the system. A 3D finite element analysis was used to investigate some of the key parameters that affect the thermal packaging design of a refrigeration-cooled low-temperature processor module with the objective of preventing condensation on exposed module card surfaces with minimal power input to the added heaters.

This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM third-generation embedded dynamic random-access memory (DRAM) for the IBM Blue Logic[R] 0.11-[micro]m application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamental DRAM core function, user interface, test, and diagnosis. Macro operation and organization are detailed and contrasted with traditional DRAM designs. The use of BIST, a key enabler for embedded DRAM, is discussed while highlighting innovations required by the embedded DRAM.

This paper describes the methodology employed by the IBM Microelectronics Division for the design of its Blue Logic[R] application-specific integrated circuits (ASICs) and system-on-a-chip (SoC) designs. This methodology is used by both IBM ASIC and SoC designers, as well as OEM customers. A key focus of the IBM ASIC/SoC methodology, outlined in the first section of this paper, is the first-time-right methods of design and verification that maximize correct operation of the chip upon product integration. The second section of this paper describes advances in methodology that deal with the physical effects of shrinking device geometries and enable design using the performance and density capabilities available in the new technologies, and methodology advances that have improved design turnaround time (TAT) for large, complex designs. Upcoming nanometer-level technologies present new opportunities to integrate systems on a single chip, including functional components of mixed libraries and mixed analog and digital design. The final section of this paper outlines strategies that are enabling SoC design at these levels.

The density and performance of advanced silicon technologies have made system-on-a-chip ASICs possible. SoCs bring together a diverse set of functions and technology features on a single die of enormous complexity. The physical design of these complex ASICs requires a rich set of functional elements that integrate efficiently with a set of design flows and tools productive enough to meet product requirements successfully, without consuming more time or design resources than a simpler design. The architecture described, including functional libraries and physical design conventions, enables the creation of multiple SoC ASIC designs from a common infrastructure that addresses silicon integration, electrical robustness, and packaging challenges. An implementation strategy follows from this design infrastructure that includes hierarchical design concepts, placement, routing, and verification processes.

The IBM eServer zSeries[TM] FCP (Fibre Channel Protocol for SCSI) channel provides "Linux[TM] for zSeries" the capability to access storage devices using SCSI and FCP protocols, thus enabling it to make use of distributed storage. Leveraging the zSeries-unique virtualization approach for industry-standard storage devices as well, the zSeries FCP channel provides unique value in UNIX[R] and Linux environments. This paper describes the major differences between traditional and distributed storage attachments of zSeries systems. Furthermore, it describes the implementation of the zSeries FCP channel, its unique capabilities and characteristics, and how it is implemented by Linux for zSeries.

This paper describes the concept, architecture, and implementation of the hardware configuration module within the support element of the IBM eServer z900. For the z900 project, this base system firmware component has been redesigned to obtain a software structure with a clear, simple, and scalable architecture that is suitable for future extensions to the z900. To achieve the desired flexibility, an object-oriented framework has been developed which supports the auto-sensing and configuration of hardware components as well as their status representation and management. The new configuration concept is based on a rule approach in which, for each sensed physical part in the system, a configuration rule specifies the object hierarchy to be instantiated upon it, including attributes and interconnections to other system parts. Furthermore, the concept and architecture of the framework are built upon a hardware object model (HOM) that has been designed to allow for further integration of key business logic of the z900 service subsystem and hardware support code.

The IBM eServer zSeries[TM] Model 900, or z900, has been designed with major enhancements for hardware reliability, availability, and serviceability (RAS) in support of the zSeries RAS strategy, the eServer self-management technologies, and the z900 design objective of continuous reliable operation. The eServer self-management technologies enable the server to protect itself, to detect and recover from errors, to change and configure itself, and to optimize itself, in the presence of problems and changes, for maximum performance with minimum outside intervention. From the RAS perspective, the longstanding RAS strategy for the IBM S/390[R] and now the zSeries has provided an excellent foundation for self management. This paper describes the z900 RAS enhancements and how they strengthen the RAS strategy building blocks and provide a basis for autonomic computing.

An IBM eServer zSeries[TM] system uses various types of microcode (firmware) that implement functions such as the execution of complex instructions in the CPUs, I/O operations performed by the system assist processors (SAPs), the management of logical partitions (LPARs), and control by the support element (SE). Each microcode component must be verified by itself and in conjunction with the others. Tight development schedules and a very limited supply of expensive engineering hardware make it desirable to perform this verification in a simulation environment. For the development of the z900, a new microcode simulator, the z/CECSIM (Central Electronic Complex Simulator), was successfully implemented. Several microcode components are connected in a single simulation environment, thereby allowing an unprecedented amount of development, integration, and testing without the use of engineering hardware, z/CECSlM creates a virtual zSeries CEC on VM/ESA[R] or z/VM[TM] that allows the simulation of zSeries microcode. It executes the instruction stream as completely as possible on the underlying hardware. Only instructions that are newly introduced with the system being developed or that perform a microcode-internal function are simulated. Additional software models mimic the behavior of I/O and coupling channels. An optional SE connection allows verification of interactions between the CEC and its support element.

The IBM eServer z900 microprocessor is a seventh-generation zSeries[TM] (formerly S/390[R]) CMOS design which has achieved 1.3-GHz operation. This paper describes the 0.18-/[micro]m bulk CMOS, seven-level copper metal process and the high-frequency circuit, integration, and design methodologies developed to achieve this operation. The microprocessor was floorplanned to closely mimic the flow of the microarchitecture pipeline and reduce the communication delay overhead between units. Novel circuit techniques were used in the implementation of the arrays and cache hit detection logic to save power and reduce circuit complexity without sacrificing performance. A four-dimensional gate library and novel synthesis algorithms were developed to yield synthesized control implementations with the performance characteristics of a fully custom circuit design.

The IBM eServer z900 has an overall system I/O bandwidth which is three times that of IBM S/390[R] G5/G6 servers, necessitating the use of Self-Timed-Interface (STI)-to-Peripheral-Component-Interface (PCI) bridge chips to exploit this bandwidth. The chips are used to form a layer between the networking attachments of the z900 and its main storage complex. The layer adapts the high-speed point-to-point packet-oriented STI interface of the z900 to its multi-drop PCI bus structure. This paper describes a method for verifying the functionality of the STI-to-PCI bridge chips by implementing a hierarchical indexing method to support all address dispatching, data management, and data integrity checking. The method is at the core of the random-element-level verification methodology to support all data movement mainline testing of the z900. Monitors, checkers, and drivers were developed and integrated as part of the overall methodology to verify all external interfaces.