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Through Silicon Via (TSV) is considered as the near-future solution to realize low-power and high-performance 3D-Integrated Circuits (3D-ICs) and 3D-Network-on-Chips (3D-NoCs). However, the lifetime reliability issue of TSV due to its fault sensitivity and the high operating temperature of 3D-ICs, which also accelerates the fault-rate, is one of the most critical challenges. Meanwhile, most current works focus on detecting and correcting TSV defects after manufacturing without considering high-temperature nodes’ impact on lifetime reliability. Besides, the recovery for defective clusters is also challenging because of costly redundancies. In this work, we present HotCluster: a hotspot-aware self-correction platform for clustering defects in 3D-NoCs to help understand and tackle this problem. We first give a method to predict normalized fault rates and place redundant TSV groups according to each region’s fault rate. In our particular medium fault-rate (normalized to the coolest area), HotCluster reduces about 60% of the redundancies in comparison to the uniformly distributed redundancies while having a higher ratio of router working in a normal state. Furthermore, HotCluster integrates both online (weight-based) and offline (max-flow min-cut offline method) mapping algorithms to help the system correct the faulty TSV clusters. The experimental results show that both the max-flow min-cut offline method and weight-based online mode with a redundancy of 0.25 exhibits less than 1% of routers disabled under 50% defect-rates.

For most Internet-of-Things (IoT) applications, embedded processors typically execute lightweight tasks such as sensing and communication. The typical IoT program senses some information and sends them via a channel, usually a wireless channel with an RF circuit. These IoT nodes often require a system with networking capabilities and a low-power harvester implementation. This brief presents a sub- $\mu \text{W}$ 8-bit processor which is suitable for such IoT applications. The processor implements the Open8 Instruction Set Architecture (ISA) with an 8-bit datapath and 16-bit bus addressing. The chip contains the processor and a 4-KB of Static Random-Access-Memory (SRAM), and is fabricated by the 65-nm Silicon-On-Thin-Box (SOTB) process. The SOTB process is one of the Fully-Depleted Silicon-On-Insulator (FD-SOI) technology. Hence, the ability to control biasing voltages is one of its key advantages to achieve low-power. The experimental results show that the power consumption at the reverse-body bias can reach down to 50-nW with 0.5-V supply voltage and 32-KHz operating clock frequency. The completed microcontroller consists of the Open8 processor, 32-KB of Read-Only-Memory (ROM), 4-KB of SRAM, Serial Peripheral Interface (SPI), SPI programmer, debug module, General-Purpose In-Outs (GPIOs), and UART. The system was tested using an XC7A100T Xilinx Field-Programmable Gate Array (FPGA); it yielded 1.8% of the total FPGA utilization.

The authors present a novel wideband two‐dimensional voltage‐controlled attenuator (VCA). The proposed design employs both stacked‐FET configuration and distributed structure to achieve wideband performance, high power, and high dynamic range simultaneously. A systematic design methodology is also illustrated along with a fabricated prototype to verify the concept. The chip fabricated in a 0.15‐μm Gallium Arsenide (GaAs) process exhibiting a measured power at 1‐dB compression (P1dB) of 25.5 dBm with a corresponding dynamic range of 32 dB. The insertion loss ranges from 2 to 5 dB over the bandwidth from 2 to 40 GHz. Furthermore, the chip is not only very compact (0.84 mm2), but it also requires only a single positive supply voltage, which makes it more appealing to highly integrated wireless applications.

As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Network-on-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles).

Deep Learning (DL) has contributed to the success of many applications in recent years. The applications range from simple ones such as recognizing tiny images or simple speech patterns to ones with a high level of complexity such as playing the game of Go. However, this superior performance comes at a high computational cost, which made porting DL applications to conventional hardware platforms a challenging task. Many approaches have been investigated, and Spiking Neural Network (SNN) is one of the promising candidates. SNN is the third generation of Artificial Neural Networks (ANNs), where each neuron in the network uses discrete spikes to communicate in an event-based manner. SNNs have the potential advantage of achieving better energy efficiency than their ANN counterparts. While generally there will be a loss of accuracy on SNN models, new algorithms have helped to close the accuracy gap. For hardware implementations, SNNs have attracted much attention in the neuromorphic hardware research community. In this work, we review the basic background of SNNs, the current state and challenges of the training algorithms for SNNs and the current implementations of SNNs on various hardware platforms.

In this paper, a PCA and ANN-based face recognition system is proposed and implemented on a Coarse Grain Reconfigurable Computing (CGRC) platform. Our work is quite distinguished from previous ones in two aspects. First, a new hardware-software co-design method is proposed, and the whole face recognition system is divided into several parallel tasks implemented on both the Coarse-Grained Reconfigurable Architecture (CGRA) and the General-Purpose Processor (GPP). Second, we analyzed the source code of the ANN algorithm and proposed the optimization solution to explore its multi-level parallelism to improve the performance of the application on the CGRC platform. The computation tasks of ANN are dynamically mapped onto CGRA only when needed, and it's quite different from traditional Field Programmable Gate Array (FPGA) methods in which all the tasks are implemented statically. Implementation results show that our system works correctly in face recognition with a correct recognition rate of approximately 90.5%. To the best of our knowledge, this work is the first implementation of PCA and ANN-based face recognition system on a dynamically CGRC platform presented in the literature.

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To enhance the reliability of TSV connections, using error correction code to detect and correct faults automatically has been demonstrated as a viable solution.This paper presents a 2D Parity Product Code (2D-PPC) for TSV fault-tolerance with the ability to correct one fault and detect, at least, two faults. In an implementation of 64-bit data and 81-bit codeword, 2D-PPC can detect over 71 faults, on average. Its encoder and decoder decrease the overall latency by 38.33% when compared to the Single Error Correction Double Error Detection code. In addition to the high detection rates, the encoder can detect 100% of its gate failures, and the decoder can detect and correct around 40% of its individual gate failures. The squared 2D-PPC could be extended using orthogonal Latin square to support extra bit correction.

As one of the most promising technologies to reduce footprint, power consumption and wire latency, Three Dimensional Integrated Circuits (3D-ICs) is considered as the near future for VLSI system. Combining with the Network-on-Chip infrastructure to obtain 3D Networks-on-Chip (3D-NoCs), the new on-chip communication paradigm brings several advantages. However, thermal dissipation is one of the most critical challenges for 3D-ICs, where the heat cannot easily transfer through several layers of silicon. Consequently, the high-temperature area also confronts the reliability threat as the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Black’s model. Apparently, 3D-NoCs and 3D ICs must tackle this fundamental problem in order to be widely used. However, the thermal analyses usually require complicated simulation and might cost an enormous execution time. As a closed-loop design flow, designers may take several times to optimize their designs which significantly increase the thermal analyzing time. Furthermore, reliability prediction also requires both completed design and thermal prediction, and designer can use the result as a feedback for their optimization. As we can observe two big gaps in the design flow, it is difficult to obtain both of them which put 3D-NoCs under thermal throttling and reliability threats. Therefore, in this work, we investigate the thermal distribution and reliability prediction of 3D-NoCs. We first present a new method to help simulate the temperature (both steady and transient) using traffic values from realistic and synthetic benchmarks and the power consumption from standard VLSI design flow. Then, based on the proposed method, we further predict the relative reliability between different parts of the network. Experimental results show that the method has an extremely fast execution time in comparison to the acceleration lifetime test. Furthermore, we compare the thermal behavior and reliability between Monolithic design and TSV-based design. We also explore the ability to implement the thermal via a mechanism to help reduce the operating temperature.

HEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC&rsquo, s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW, this is important factor for handheld applications.

High-Efficiency Video Coding (HEVC), also known as H.265 and MPEG-H Part 2, is the newest video coding standard developed to address the increasing demand for higher resolutions and frame rates. In comparison to its predecessor H.264/AVC, HEVC achieved almost double of compression performance that is capable to process high quality video sequences (UHD 4K, 8K; high frame rates) in a wide range of applications. Context-Adaptive Baniray Arithmetic Coding (CABAC) is the only entropy coding method in HEVC, whose principal algorithm is inherited from its predecessor. However, several aspects of the method that exploits it in HEVC are different, thus HEVC CABAC supports better coding efficiency. Effectively, pipeline and parallelism in CABAC hardware architectures are prospective methods in the implementation of high performance CABAC designs. However, high data dependence and serial nature of bin-to-bin processing in CABAC algorithm pose many challenges for hardware designers. This paper provides an overview of CABAC hardware implementations for HEVC targeting high quality, low power video applications, addresses challenges of exploiting it in different application scenarios and then recommends several predictive research trends in the future.

Deep Neural Networks (DNNs) have been successfully applied to various real-world machine learning applications. However, performing large DNN inference tasks in real-time remains a challenge due to its substantial computational costs. Recently, Spiking Neural Networks (SNNs) have emerged as an alternative way of processing DNN’fs task. Due to its eventbased, data-driven computation, SNN reduces both inference latency and complexity. With efficient conversion methods from traditional DNN, SNN exhibits similar accuracy, while leveraging many state-of-the-art network models and training methods. In this work, an efficient neuromorphic hardware architecture for image recognition task is presented. To preserve accuracy, the analog-to-spiking conversion algorithm is adopted. The system aims to minimize hardware area cost and power consumption, enabling neuromorphic hardware processing in edge devices. Simulation results have shown that, with the MNIST digit recognition task, the system has achieved $\times 20$ reduction in terms of core area cost compared to the state-of-the-art works, with an accuracy of 94.4%, core area of 15 $\mu m^{2}$ at a maximum frequency of 250 MHz.

The soft error rates per single-bit due to alpha particles in sub-micron technology is expectedly reducedas the feature size is shrinking. On the other hand, the complexity and density of integrated systems are accelerating which demand ecient soft error protection mechanisms, especially for on-chip communication. Using soft error protection method has to satisfy tight requirements for the area and energy consumption, therefore a low complexity and low redundancy coding method is necessary. In this work, we propose a method to enhance Parity Product Code (PPC) and provide adaptation methods for this code. First, PPC is improved as forward error correcting using transposable retransmissions. Then, to adapt with dierent error rates, an augmented algorithm for configuring PPC is introduced. The evaluation results show that the proposed mechanism has coding rates similar to Parity check’s and outperforms the original PPC.Keywords Error Correction Code, Fault-Tolerance, Network-on-Chip. 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The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of the reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing the reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

International audience; Connected devices are getting attention because of the lack of security mechanisms in current Internet-of-Thing (IoT) products. The security can be enhanced by using standardized and proven-secure block ciphers as advanced encryption standard (AES) for data encryption and authentication. However, these security functions take a large amount of processing power and power/energy consumption. In this paper, we present our hardware optimization strategies for AES for high-speed ultralow-power ultralow-energy IoT applications with multiple levels of security. Our design supports multiple security levels through different key sizes, power and energy optimization for both datapath and key expansion. The estimated power results show that our implementation may achieve an energy per bit comparable with the lightweight standardized algorithm PRESENT of less than 1 pJ/b at 10 MHz at 0.6 V with throughput of 28 Mb/s in ST FDSOI 28-nm technology. In terms of security evaluation, our proposed datapath, 32-b key out of 128 b cannot be revealed by correlation power analysis attack using less than 20 000 traces.

This paper presents a proposal and implementation of a multi-mode full-reconfigurable router for Network-on-Chip (NoC). First, the router supports a hybrid packet-switching architecture that is dynamically reconfigurable to exchange between wormhole and virtual cut-through switching schemes at run-time. Therefore, it reaches a higher average performance than wormhole switching, while decreasing the implementation cost in comparison with the virtual cut-through switching. Second, the router is equipped a Quality-of-Services (QoS)-driven arbiter. Therefore, the proposed solution not only guarantees the guaranteed-throughput service without reserving resources but also enhances the average performance for the best-effort service by using network resources efficiently based on the priority inheritance arbitration mechanism. Third, the router is enhanced with the dynamically deadline-aware rerouting mechanism. In contention situation, the router can configure the routing computation unit to reroute the packet to another path so as to reduce the waiting interval of the blocked packets. The router was designed at the Register Transfer Level and modeled using VHDL language and then synthesized with Xilinx Virtex-7 FPGA technology. The experimental results prove that the proposed router is reliable and can improve the average performance of different QoS loads significantly compared with the generic routers while the area and power overhead are acceptable.

In this paper, we present a novel router architecture for implementing a Reconfigurable Network-on-Chip (RNoC) at high-level design using SystemC. The RNoC is an adaptive NoC-based system-on-chip providing a dynamic reconfigurable communication mechanism. By adding a virtual port – named Routing Modification port – into the conventional router architecture, the network router is able to route communication data flexibly whenever the target routing path is blocked, by unwanted defects or intently by a software programme to meet the requirements of applications. The proposed architecture has been modeled in SystemC/C++, simulated and verified within a 2D mesh 5×5 network platform. In normal communication mode, the static XY routing algorithm is used while the West-First algorithm with a proposed prohibited router surrounding technique is applied in reconfiguration mode. Experimental results are also reported to compare the performance of the network architecture in different operation modes as well as with other works.

H.264 is the most popular video coding standard with high potent coding performance. For its efficiency, the H.264 is expected to encode real-time and/or high-definition video. However, the H.264 standard also requires highly complex and long lasting computation. To overcome these difficulties, many efforts have been deployed to increase encoding speed. Besides, with the revolution of portable devices, multimedia chips for mobile environments are more and more developed. Thus, power-oriented design for H.264 video encoders is currently a tremendous challenge. This paper discusses these trends and presents an overview of the state of the art on power features for different H.264 hardware encoding architectures. We also propose the VENGME’s design, a particular hardware architecture of H.264 encoder that enables applying low-power techniques and developing power-aware ability. This low power encoder is a four-stage architecture with memory access reduction, in which, each module has been optimized. The actual total power consumption, estimated at Register-Transfer-Level (RTL), is only 19.1 mW.

Thanks to the rapid evolution of semiconduc-tor technology, System-on-Chip (SoC) paradigm has be-come one of the most common design methodologies for quickly developing embedded systems to meet the high demands of embedded applications. In this paper, we present the design and implementation on a SoC platform targeted to controlling and monitoring applications. This proposed platform is composed of a 32-bit processor and a dozen of common hardware interfaces, providing the programmability and connectivity to peripheral devices such as memories, Lan network, monitor, keyboard, ADC, DAC, or other I/O device. In addtion, to increase the flexibility of the system and to rapidly develop end-user applications, we also deploy an application-specific software framework with the robustness of a lightweight kernel and real-time applet management. The system model has finally been validated through the realization of a remote control camera system.

Thanks to many novel coding tools, H.264/AVC has become the most efficient video compression standard providing much better performance than previous standards. However, this standard comes with an extraordinary computational complexity and a huge memory access requirement, which make the hardware architecture design much more difficult and costly, especially for realtime applications. In the framework of H.264 codec hardware architecture project, this paper presents an efficient architecture of Forward Transform and Quantization (FTQ) for H.264/AVC codecs in mobile applications. To reduce the hardware implementation overhead, the proposed design uses only one unified architecture of 1-D transform engine to perform all required transform processes, including discrete cosine transform and Walsh Hadamard transform. This design also enables to share the common parts among multipliers that have the same multiplicands. The performance of the design is taken into consideration and improved by using a fast architecture of the multiplier in the quantizer, the most critical component in the design. Experimental results show that our architecture can completely finish transform and quantization processes for a 4:2:0 macroblock in 228 clock cycles and the achieved throughput is 445Msamples/s at 250MHz operating frequency while the area overhead is very small, 147755μm2 (approximate 15KGates), with the 130nm TSMC CMOS technology.

Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.

International audience; The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these network architectures. To test the SoCs, the main challenge is to reach into the embedded cores (i.e, the IPs). In this case, the DFT techniques that integrate test architectures into the SoCs to ease the test of these SoCs are really favoured. In this paper, we present a new methodology for testing NoC architectures. A modular, generic, scalable and configurable DFT architecture is developed in order to ease the test of NoC architectures. The target of this test architecture is asynchronous NoC architectures that are implemented in GALS systems. The proposed architecture is therefore named ANOC-TEST and is implemented in QDI asynchronous circuits. In addition, this architecture can be used to test the computing resources of the networked SoCs. Some initial results and conclusions are also given

The Internet of Things (IoT) has been fostered by accelerated advancements in communication technologies, computation technologies,sensor technologies, artificial intelligence, cloud computing, and semiconductor technologies. In general, IoT contains cloud computing to do data processing, communication infrastructure including the Internet, and sensor nodes which can collect data, send them through the network infrastructure to the Internet, and receive controls to react to the environment. During its operations, IoT may collect, transmit and process secret data, which raise security problems. Implementing security mechanisms for IoT is challenging because IoT organizations include millions of devices integrated at multiple layers, whereas each layer has different computation capabilities and security requirements. Furthermore, sensor nodes in IoT are intended to be battery-based constrained devices with limited power budget, limited computation, and limited memory footprint to reduce costs. Implementing security mechanisms on these devices even encounters more challenges. This work is therefore motivated to focus on implementing data encryption to protect IoT sensor nodes and systems with the consideration of hardware cost, throughput and power/energy consumption. To begin with, a ultra-low-power block cipher crypto-accelerator with configurable parameters is proposed and implemented in ST 28nm FDSOI technology in SNACk test chip with two cryptography modules: AES and PRESENT. AES is a widely used data encryption algorithm for the Internet and currently used for new IoT proposals, while PRESENT is a lightweight algorithm which comes up with reduced security level but requires with much smaller hardware area and lower consumption. The AES module is a 32-bit datapath architecture containing multiple optimization strategies supporting multiple security levels from 128-bit keys up to 256-bit keys. The PRESENT module contains a 64-bit round-based architecture to maximize its throughput. The measured results indicate that this crypto-accelerator can provide medium throughput (around 20Mbps at 10MHz) while consumes less than 20uW at normal condition and sub-pJ of energy per bit. However, the limitation of crypto-accelerator is that the data has to be read into the crypto-accelerator and write back to memory which increases the power consumption. After that, to provide a high level of security with flexibility and configurability to adapt to new standards and to mitigate to new attacks, this work looks into an innovative approach to implement the cryptography algorithm which uses the new proposed In-Memory-Computing SRAM. In-Memory Computing SRAM can provide reconfigurable solutions to implement various security primitives by programming the memory's operations. The proposed scheme is to carry out the encryption in the memory using the In-Memory-Computing technology. This work demonstrates two possible mapping of AES and PRESENT using In-Memory Computing., L'Internet des objets (IoT : Internet-of-Things) a été favorisé par les progrès accélérés dans les technologies de communication, les technologies de calcul, les technologies de capteurs, l'intelligence artificielle, l'informatique en nuage et les technologies des semi-conducteurs. En générale, l'IoT utilise l'informatique en nuage pour traitant les données, l'infrastructure de communication (y compris l’Internet) et des nœuds de capteurs pour collecter des données, de les envoyer de l'infrastructure du réseau à l’Internet, et de recevoir des commandes pour réagir à l'environnement. Au cours de ses opérations, l'IoT peut collecter, transmettre et traiter des données secrètes ou privées, ce qui pose des problèmes de sécurité. La mise en œuvre des mécanismes de sécurité pour l'IoT est un défi, car les organisations de l’IoT incluent des millions de périphériques intégrés à plusieurs couches, chaque couche ayant des capacités de calcul et des exigences de sécurité différentes. En outre, les nœuds de capteurs dans l'IoT sont conçus pour être des périphériques limités par une batterie, avec un budget de puissance, des calculs et une empreinte mémoires limités pour réduire les coûts d’implémentation. L'implémentation de mécanismes de sécurité sur ces appareils rencontre même plus de défis. Ce travail est donc motivé pour se concentrer sur l’implémentation du cryptage des données afin de protéger les nœuds et les systèmes de capteurs IoT en tenant compte du coût matériel, du débit et de la consommation d’énergie. Pour commencer, un crypto-accélérateur de chiffrement de bloc ultra-basse consommation avec des paramètres configurables est proposé et implémenté dans la technologie FDSOI ST 28 nm dans une puce de test, qui est appelée SNACk, avec deux modules de cryptographie : AES et PRESENT. L’AES est un algorithme de cryptage de données largement utilisé pour l’Internet et utilisé actuellement pour les nouvelles propositions IoT, tandis que le PRESENT est un algorithme plus léger offrant un niveau de sécurité réduit mais nécessitant une zone matérielle beaucoup plus réduite et une consommation très bas. Le module AES est une architecture de chemin de données 32 bits contenant plusieurs stratégies d'optimisation prenant en charge plusieurs niveaux de sécurité, allant des clés 128 bits aux clés 256 bits. Le module PRESENT contient une architecture à base arrondie de 64 bits pour optimiser son débit. Les résultats mesurés pendant cette thèse indiquent que ce crypto-accélérateur peut fournir un débit moyen (environ 20 Mbits/s au 10 MHz) tout en consommant moins de 20 µW dans des conditions normales et une sous-pJ d’énergie par bit. Cependant, la limitation du crypto-accélérateur réside dans le fait que les données doivent être lues dans le crypto-accélérateur et réécrites en mémoire, ce qui augmente la consommation d'énergie. Après cela, afin de fournir un haut niveau de sécurité avec une flexibilité et une possibilité de configuration pour s’adapter aux nouvelles normes et pour atténuer les nouvelles attaques, ces travaux portent sur une approche novatrice de mise en œuvre de l’algorithme de cryptographie utilisant la nouvelle SRAM proposée en mémoire. Le calcul en mémoire SRAM peut fournir des solutions reconfigurables pour mettre en œuvre diverses primitives de sécurité en programmant les opérations de la mémoire. Le schéma proposé consiste à effectuer le chiffrement dans la mémoire en utilisant la technologie Calcul en Mémoire (In-Memory-Computing). Ce travail illustre deux mappages possibles de l'AES et du PRESENT à l'aide du calcul en mémoire.

Power consumption for Systems-on-Chip induces strong constraints on their design. Power consumption affects the system reliability, cooling cost, and battery lifetime for Systems-on-Chips powered by battery. With the pace of semiconductor technology, power optimization has become a tremendous challenging issue together with Silicon area and/or performance optimization, especially for mobile applications. Video codec chips are used in various applications ranging for video conferencing, security and monitoring systems, but also entertainment applications. To meet the performance and power consumptions constraints encountered for mobile applications, video codecs are favorably preferred to be implemented in hardware rather than in software. This hardware implementation will lead to better power efficiency and real-time requirements. Nowadays, one of the most efficient standards for video applications is the H.264 Advanced Video Coding (H.264/AVC) which provides better video quality at a lower bit-rate than the previous standards. To bring the standard into commercial products, especially for hand-held devices, designers need to apply design approaches dedicated to low-power circuits. They also need to implement mechanisms to control the circuit power consumption. This PhD thesis is conducted in the framework of the VENGME H.264/AVC hardware encoder design. The platform is split in several modules and the VENGME Entropy Coder and bytestream Network Abstraction Layer data packer (EC-NAL) module has been designed during this PhD thesis, taking into account and combining several state-of-the-art solutions to minimise the power consumption. From simulation results, it has been seen that the EC-NAL module presents better power figures than the already published solutions. Then, the VENGME H.264 encoder architecture has been analyzed and power estimations at RTL level have been performed to extract the platform power figures. Then, from these power figures, it has been decided to implement power control on the EC-NAL module. This latter contains a FIFO whose level can be controlled via an appropriate scaling of the clock frequency on the NAL side, which leads to the implementation of a Dynamic Frequency Scaling (DFS) approach based on the control of the FIFO occupancy level. The control law has been implemented in hardware (full-custom) and the closed-loop system stability has been studied. Simulation results show the effectiveness of the proposed DVS strategy that should be extended to the whole H.264 encoder platform., La consommation d'énergie des systèmes sur puces induit des contraintes fortes lors de leur conception. Elle affecte la fiabilité du système, le coût du refroidissement de la plateforme, et la durée de vie de la batterie lorsque le circuit est alimenté par des batteries. En fait, avec la diminution de la tailles de la technologie des semi-conducteurs, l'optimisation de la puissance consommée est devenue un enjeu majeur, au même titre que le coût lié à la surface silicium et l'optimisation des performances, en particulier pour les applications mobiles. Des puces codec vidéo dédiées ont été utilisés dans diverses applications telles que les systèmes de vidéoconférence, de sécurité et de surveillance, ou encore et des applications de divertissement. Pour répondre aux contraintes des applications mobiles en termes de performance et de consommation énergétique, le codec vidéo est généralement implémenté en matériel plutôt qu'en logiciel, ce qui permet de garantir les contraintes d'efficacité énergétique et de traitement en temps réel. L'une des normes les plus efficaces pour les applications vidéo est aujourd'hui la norme H.264 Encodage Vidéo Avancé (H.264/AVC), qui offre une meilleure qualité vidéo à un débit binaire plus bas que les normes précédentes. Pour pouvoir effectivement intégrer cette norme dans des produits commerciaux, en particulier pour les appareils mobiles, lors de la conception du codec vidéo en matériel, les concepteurs devront utiliser des approches spécifiques de conception de circuits basse consommation et implanter des mécanismes de contrôle de la consommation. Cette thèse de doctorat s'est déroulée dans le cadre de la conception de l'encoder matériel au format H.264, appelé plateforme VENGME. La plateforme est découpée en différents modules et le module EC-NAL a été développé durant la thèse, en prenant en compte différentes solutions apparues dans la littérature pour minimiser la consommation de ce module. Les résultats en simulation montrent que le module EC-NAL présente de meilleurs résultats d'un point de vue consommation que ses concurrents de la littérature. L'architecture de la plateforme VENGME a ensuite été analysée, et des simulations au niveau RTL ont été menées pour évaluer sa consommation globale. Il en est ressorti une possibilité de diminuer encore plus la consommation de la plateforme matérielle en contrôlant la fréquence de certains modules. Cette approche a été appliquée au module EC-NAL qui possède en interne une FIFO. Dont le niveau peut être contrôlé en ajustant la fréquence d'horloge du côté du sous-module NAL. Cela a donc conduit à implémenter une approche d'adaptation automatique de la fréquence en fonction du niveau de remplissage de la FIFO. Le contrôleur a été implémenté en matériel et la stabilité du système bouclé a été étudiée. Les résultats en simulation montrent l'intérêt de la démarche adoptée qui devra être étendue à l'ensemble de la plateforme.