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Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture. The parallel in‐memory computing provided by neuromorphic computing has the potential to significantly improve latency and power consumption. Key to analog neuromorphic computing hardware are memristors, providing non‐volatile multistate conductance levels, high switching speed, and energy efficiency. Ferroelectric tunnel junction (FTJ) memristors are prime candidates for this purpose, but the impact of the particular characteristics for their performance upon integration into large crossbar arrays, the core compute element for both inference and training in deep neural networks, requires close investigation. In this work, a W/HfxZr1−xO2/TiN FTJ with 60 programmable conductance states, a dynamic range (DR) up to 10, current density >3 A m−2 at Vread = 0.3 V and highly nonlinear current–voltage (I–V) characteristics (>1100) is experimentally demonstrated. Using a circuit macro‐model, the system level performance of a true crossbar array is evaluated and a 92% classification accuracy of the modified nation institute of science and technology (MNIST) dataset is achieved. Finally, the low on conductance in combination with the highly nonlinear I–V characteristics enable the realization of large selector‐free crossbar arrays for neuromorphic hardware accelerators. [ABSTRACT FROM AUTHOR]

Ferroelectric HfxZr1–xO2 (HZO) is typically achieved by crystallization of an amorphous thin film via rapid thermal processing (RTP) at time scales of seconds to minutes. For integration on III–V semiconductors, this approach can severely degrade the sensitive HZO/III–V interface. To evaluate whether a reduced thermal budget can improve the interface quality, millisecond duration thermal anneals are utilized using a flash lamp annealer (FLA) on HZO/InAs capacitors. Through thorough electrical characterization such as polarization hysteresis, endurance, and capacitance‐voltage measurements, as well as synchrotron‐based chemical interface characterization, the FLA and RTP treatments are compared and the FLA results are found in lower interface defect density and higher endurance, but also have generally lower remanent polarization (Pr) compared to RTP. Additionally, ways to achieve high Pr and low interface defect density using multiple lower energy flashes, as well as by pre‐crystallization during the ALD growth step are investigated. Using FLA, Pr exceeding 20 µC cm−2 is achieved, with extended endurance properties compared to RTP treatment and a considerably decreased defect density, indicative of a higher quality HZO/InAs interface. This work presents valuable insight into the successful integration of ferroelectric HZO on low thermal budget III–V semiconductors. [ABSTRACT FROM AUTHOR]

We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs. [ABSTRACT FROM AUTHOR]

InSb has the smallest bandgap and highest electron mobility among III‐V semiconductors and is widely used for photodetectors and high‐frequency electronic applications. Integration of InSb directly on Si would drastically reduce the fabrication cost and enable new applications, however, it is very challenging due to its 19% lattice mismatch with Si. Herein, the integration of single‐crystalline InSb microstructures on insulator‐covered Si through rapid melt growth (RMG) is reported and specifically provides details on the fabrication process. The importance of achieving high‐quality conformal capping layers at low thermal budget to contain the InSb melt is assessed when the sample is annealed. The importance of ensuring a pristine Si seed area to achieve single‐crystalline InSb is illustrated and demonstrated here for the first time. [ABSTRACT FROM AUTHOR]

Monolithic integration of III–V semiconductors with Silicon technology has instigated a wide range of new possibilities in the semiconductor industry, such as combination of digital circuits with optical sensing and high-frequency communication. A promising CMOS compatible integration process is rapid melt growth (RMG) that can yield high quality single crystalline material at low cost. This paper represents the study on ultra-thin InSb-on-insulator microstructures integrated on a Si platform by a RMG-like process. We utilize flash lamp annealing (FLA) to melt and recrystallize the InSb material for an ultra-short duration (milliseconds), to reduce the thermal budget necessary for integration with Si technology. We compare the result from FLA to regular rapid thermal annealing (seconds). Recrystallized InSb was characterized using electron back scatter diffraction which indicate a transition from nanocrystalline structure to a crystal structure with grain sizes exceeding 1 μm after the process. We further see a 100× improvement in electrical resistivity by FLA annealed sample when compared to the as-deposited InSb with an average Hall mobility of 3100 cm2 V−1 s−1 making this a promising step towards realizing monolithic mid-infrared detectors and quantum devices based on InSb. [ABSTRACT FROM AUTHOR]

We propose a capacitance measurement scheme that enables quantitative characterization of ferroelectric thin films integrated on semiconductors. The film defect density is estimated by measurements of the CV hysteresis and frequency dispersion, whereas important device parameters such as memory window and endurance can be extracted by a unidirectional CV method. The simple measurement scheme and the usage of metal-oxide-semiconductor capacitors rather than MOSFETs make the proposed methods suitable for the future optimization of ferroelectric field effect transistor and negative capacitance field effect transistor gate stacks. Specifically, we present data for the narrow bandgap semiconductor InAs and show that low temperature characterization is critical to reduce the influence of the minority carrier response; however, the methods should be transferrable to room temperature for semiconductors with a wider bandgap. Our results clearly indicate that the defect density of the HfxZr1−xO2 (HZO) films increases at the crystallization temperature, but the increase is modest and remains independent of the annealing temperature at even more elevated temperatures. It is also shown that the shrinkage of the memory window caused by field cycling is not accompanied by an increase in defect density. [ABSTRACT FROM AUTHOR]

Deposition, annealing, and integration of ferroelectric Hf x Zr 1 − x O 2 (HZO) thin films on the high-mobility semiconductor InAs using atomic layer deposition are investigated. Electrical characterization reveals that the HZO films on InAs exhibit an enhanced remanent polarization compared to films formed on a reference TiN substrate, exceeding 20 μ C / cm 2 even down to an annealing temperature of 370 ° C. For device applications, the thermal processes required to form the ferroelectric HZO phase must not degrade the high-κ/InAs interface. We find by evaluation of the capacitance–voltage characteristics that the electrical properties of the high-κ/InAs are not significantly degraded by the annealing process, and high-resolution transmission electron microscopy verifies a maintained sharp high-κ/InAs interface. [ABSTRACT FROM AUTHOR]