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ZnTe has a favorable band alignment with CdTe and is an ideal buffer between CdTe and metal contacts used in photovoltaics. Using metalorganic chemical vapor deposition, we report epitaxial growth of ZnTe thin films on 2D substrates, namely, single crystal graphene on amorphous SiO2/Si and freshly cleaved mica(001). Despite the large in-plane lattice mismatches between ZnTe and graphene (∼75%) and between ZnTe and mica(001) (∼17%), X-ray pole figure analyses show preferred epitaxial alignments with the out-of-plane orientation along [111] for ZnTe films on both substrates. For ZnTe on graphene, besides the primary in-plane orientation of [ 1 ¯ 10 ] ZnTe / / [ 1 1 ¯ ] graphene , two secondary in-plane orientations rotating ±25.28° away from the primary domain are found. A geometrical superlattice area mismatch (GSAM) model is implemented to explain the existence of the primary and secondary domains in ZnTe on graphene. For ZnTe on mica(001), only one in-plane orientational domain is found experimentally with the epitaxial relationship of [ 1 ¯ 10 ] ZnTe / / [ 100 ] mica (or [ 1 ¯ 10 ] ZnTe / / [ 2 1 ¯ 1 ¯ 0 ] mica if four-index notation is used for mica). However, the prediction of domain orientation between ZnTe and mica(001) based on the GSAM model slightly deviates from that observed experimentally. Furthermore, it should be noted that multiple order twinning domains of the primary domain are observed in both ZnTe films. While coexisting with the primary domain, each of the twinning domains is still epitaxially aligned with respect to the substrate. The in-depth understanding of ZnTe's epitaxial behaviors on graphene and mica(001) provides a valuable guidance for future studies on epitaxy of 3D zinc-blende overlayers on 2D hexagonal substrates. [ABSTRACT FROM AUTHOR]

Improvements in thermophotovoltaic devices can be achieved through longer minority carrier diffusion lengths, which fosters optical absorption in the p-layer. Reduced dependency on the influence of surface passivation can be achieved through thin emitter/thick base, n/p devices.

Epitaxial growth of n-type SiC was carried out using PH[sub 3] and N[sub 2] as the dopant precursors in a chemical vapor deposition system. Thermodynamic simulations were performed to analyze the gas phase composition at the growth conditions. It was shown that the incorporation behaviors of these two dopants are quite different. Compared to nitrogen, phosphorous incorporation has a weaker dependence on flow rate and has a limited site competition effect. Also, phosphorus incorporation for a given precursor flow decreases with temperature while that of nitrogen increases. It was also observed that phosphorous incorporation increases with decreasing C/Si when the ratio is between 0.8 and 3, which suggests phosphorous might incorporate into C site when C/Si is low. Variable temperature Hall measurements were used to characterize the doped layers. Two donor levels at 82-83 and 105-114 meV for phosphorous in 6H-SiC, 50-52 meV, and 78-80 meV for phosphorous in 4H-SiC were resolved. These results were compared to those from ion-implanted samples. [ABSTRACT FROM AUTHOR]

A two-step process for synthesizing stable Cs2SnI6perovskite thin films is reported in this letter. The two-step process includes the co-evaporation of two precursors SnI2and CsI onto a glass substrate, followed by a post thermal annealing process in iodine vapor. Using this technique, pure Cs2SnI6perovskite thin films were successfully synthesized without any wet process. These perovskite thin films are found to be stable under ambient conditions. They also show an electron mobility up to 509 cm2 V−1 s−1, which is higher than the mobilities of films prepared by solution processes reported in the literature. IMPACT STATEMENT A novel two-step dry process to synthesize phase-pure, air-stable Cs2SnI6perovskite thin film with higher electron mobility than that of the films prepared by the solution process. [ABSTRACT FROM AUTHOR]

This paper reports on the use of 10B nano/microparticles in order to fill microstructures of deep trenches fabricated in n-type Si (110) bulk wafers for the development of solid-state thermal neutron detectors. The high aspect-ratio trenches were fabricated in the wafer by wet etching, with a trench width of 3.5 to 6 µm and a maximum depth of 120 µm. Boron was diffused at a temperature of ~1000 °C in order to convert the entirety of the delicate Si microstructures into a p+-n junction diode. The deep trenches of the diode were completely filled with 10B nanoparticles using a simple room-temperature process involving the pumping and venting of a vacuum chamber containing the etched wafer with 10B nanoparticles atop. The simple filling process was reproduced consistently, and the best 2.5 x 2.5 mm² device demonstrated an intrinsic thermal neutron (En <0.5 eV) detection efficiency of 32.2 ± 1.5% under a self-biased condition. This result is promising as it demonstrates a complete, low-cost fabrication process for the development of efficient thermal neutron detectors. [ABSTRACT FROM AUTHOR]

This paper presents current-controlled negative resistance (CCNR) phenomena observed in ultrahigh voltage (BV $\geq $ 10 kV) 4H silicon carbide implanted anode p-i-n rectifiers. CCNR under forward bias is believed to be caused by the presence of a thin layer under the anode with a low carrier lifetime, preventing efficient hole injection and leading to poor conductivity modulation of the drift layer. [ABSTRACT FROM AUTHOR]

Bidirectional power transistors are essential components of several power electronics systems, such as matrix converters. In this paper, we present the operating principles, design considerations, and experimental characteristics of a novel planar gate 4H-SiC bidirectional insulated gate bipolar transistors. The impact of various drift layer and unit cell parameters on blocking, on-state, and switching performance has been evaluated by using numerical simulations, and critical performance tradeoffs have been discussed. Based on the optimized design, devices were fabricated on lightly doped free-standing n-type 4H-SiC wafers. Fabricated devices showed good conductivity modulation, with a forward voltage drop of 9.7 V at 50 A/cm2 at room temperature, which increased to 11.5 V at 150 °C. [ABSTRACT FROM AUTHOR]

van der Waals epitaxy (vdWE) facilitates the epitaxial growth of materials having a large lattice mismatch with the substrate. Although vdWE of two-dimensional (2D) materials on 2D materials have been extensively studied, the vdWE for three-dimensional (3D) materials on 2D substrates remains a challenge. It is perceived that a 2D substrate passes little information to dictate the 3D growth. In this article, we demonstrated the vdWE growth of the CdTe(111) thin film on a graphene buffered SiO2/Si substrate using metalorganic chemical vapor deposition technique, despite a 46% large lattice mismatch between CdTe and graphene and a symmetry change from cubic to hexagonal. Our CdTe films produce a very narrow X-ray rocking curve, and the X-ray pole figure analysis showed 12 CdTe (111) peaks at a chi angle of 70°. This was attributed to two sets of parallel epitaxy of CdTe on graphene with a 30° relative orientation giving rise to a 12-fold symmetry in the pole figure. First-principles calculations reveal that, despite the relatively small energy differences, the graphene buffer layer does pass epitaxial information to CdTe as the parallel epitaxy, obtained in the experiment, is energetically favored. The work paves a way for the growth of high quality CdTe film on a large area as well as on the amorphous substrates. [ABSTRACT FROM AUTHOR]

We experimentally demonstrate, for the first time, bi-directional 4H-SiC planar gate, insulated gate bipolar transistors fabricated on 250- \mu \textm thick, lightly doped free-standing substrates. On Si face, forward voltage drop (at 50 A/cm ^2) of 9.7 V was obtained at room temperature, with a differential ON-resistance of 140 \textm\Omega \cdot \text cm^2 , indicating good conductivity modulation. We have also demonstrated control over minority carrier injection in static characteristics of the BD-IGBTs by application of a back-gate bias. [ABSTRACT FROM PUBLISHER]

We experimentally demonstrate 4H-SiC n-channel, planar gate insulated gate bipolar transistors (IGBTs) on 180- \mu \textm thick lightly doped free-standing n− substrates with ion-implanted collector regions, and metal–oxide–semiconductor gates on (0001) and (000-1) surfaces. The IGBTs show an ON-state current density of 20 A/cm2 at a power dissipation of 300 W/cm2. The threshold voltages are measured to be 7.5 V and 10.5 V on Si-face and C-face, respectively. Both IGBTs show a small positive temperature coefficient of the forward voltage drop, which is useful for easy parallelization of devices. [ABSTRACT FROM PUBLISHER]

In this paper, the design of a low noise charge sensitive preamplifier, suitable for high capacitance solid-state neutron detector arrays, is described. Noise considerations related to arraying multiple detectors in either series or parallel are also presented. Using the designed preamplifier, an energy resolution of 12 keV FWHM in Si is achieved with 1 nF equivalent detector capacitance and 10~\mu\S shaping time. Additionally, a novel preamplifier topology, which utilizes a capacitance canceling input stage, is presented. Detailed analysis of the capacitance cancelling stage is discussed with special consideration given to its use with a charge sensitive preamplifier. Up to a 15% decrease in noise is demonstrated using the capacitance cancelling technique. [ABSTRACT FROM AUTHOR]

A multiple deposition and etching process has been developed to enable high fill factor boron deposition in high aspect ratio holes fabricated in a (100) silicon substrate. The boron deposition was carried out using low-pressure chemical vapor deposition and the etching was done by inductively coupled plasma reactive ion etching technique. The boron deposition processes were carried out under different conditions in order to find a baseline process condition. The boron etching processes done under different conditions with the photoresist as the mask are also discussed. Finally, the fabricated neutron detector with the highest fill factor was characterized for the thermal neutron detection efficiency. [ABSTRACT FROM AUTHOR]

Metalorganic vapor phase epitaxy (MOVPE) of (211)B CdTe on (211)Si using intermediate Ge and ZnTe layers has been achieved for use as substrates for the growth of HgCdTe infrared detector materials. The best (211)B CdTe films grown in this study display a low X-ray diffraction (XRD) rocking-curve full-width-at-half-maximum (FWHM) of 64 arcs for a 12 µm thick layer and Everson etch pit density (EPD) of 3x105cm-2. In order to reduce the threading dislocation density further, growth on patterned layer has been investigated using Si3N4 as the mask. In order to achieve selective nucleation on patterned layer, process parameters were first developed. A circular pattern was used to study the anisotropy during growth and to identify the optimum orientation for parallel stripe growth windows. The optimum growth window was then used for the growth of completely merged layers (© 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

High-voltage (4-6 kV) 4H-SiC-based bipolar junction transistors were designed, fabricated, and characterized. Various design and process optimization techniques to improve the ON state and the forward blocking performance of these devices were studied and incorporated. Using the conventional base contact implantation process, devices with blocking voltages up to 4 kV and specific on-resistance (Ron,sp) values higher than the unipolar limit (37 mΩ · cm²), with a current gain of ten in the active region, were experimentally demonstrated. A novel selective growth of p-contact-based process was developed and implemented. This, coupled with improvements in the termination design, resulted in enhancing the blocking voltage capability to 6 kV while simultaneously lowering the Ron,sp to below the unipolar limit (28 mΩ · cm² and current gain of four in the active region), for the same starting material. Evidence for the presence of conductivity modulation (for the first time) in high-voltage SiC BJTs was also shown experimentally. [ABSTRACT FROM AUTHOR]

In an effort to improve the silicon carbide (SiC) substrate surface, a new electrochemical mechanical polishing (ECMP) technique was developed. This work focused on the Si-terminated 4H-SiC (0001) substrates cut 8° off-axis toward >1120<. Hydrogen peroxide (H2O2) and potassium nitrate (KNO3) were used as the electrolytes while using colloidal silica slurry as the polishing medium for removal of the oxide. The current density during the polishing was varied from 10 µA/cm² to over 20 mA/cm². Even though a high polishing rate can be achieved using high current density, the oxidation rate and the oxide removal rate need to be properly balanced to get a smooth surface after polishing. A two-step ECMP process was developed, which allows us to separately control the anodic oxidation and removal of formed oxide. The optimum surface can be achieved by properly controlling the anodic oxidation current as well as the polishing rate. At higher current flow (>20 mA/cm²), the final surface was rough, whereas a smoother surface was obtained when the current density was in the vicinity of 1 mA/cm². The surface morphology of the as-received wafer, fine diamond slurry (0.1 µm) polished wafer, and EMCP polished wafer were studied by high-resolution atomic force microscopy (AFM). [ABSTRACT FROM AUTHOR]

Organometallic vapor phase heteroepitaxy of CdTe on (100) oriented GaAs substrates is described in this letter. It is shown that high quality CdTe layers can be grown on GaAs substrates over the temperature range 350–440 °C by this process. Growth under different temperatures and reactant partial pressures is described. Conditions are outlined for obtaining optimum photoluminescence properties, with suppression of the defect level associated with the cadmium vacancy. Electron channeling data are presented to indicate that excellent epitaxy is achieved by this process. The orientation of the epitaxial layer is found to be the same as that of the substrate. [ABSTRACT FROM AUTHOR]

Detectors operating at 2 μm are important for several applications including optical communication and atmospheric remote sensing. In this letter, fabrication of 2 μm photodetectors using an InGaSb substrate is reported. The ternary substrates were grown using vertical Bridgmann technique and Zn diffusion was used to fabricate p–n junction diodes and photodiodes. Dark current measurement reveals that the breakdown voltage is in the 0.75 to 1 V range. Spectral response measurements indicated a 2 μm responsivity of 0.56 A/W corresponding to 35% quantum efficiency. Photodiode performance was compared to similar devices fabricated on binary substrates. [ABSTRACT FROM AUTHOR]

We report here on the growth of Hg0.8Cd0.2Te on lattice-matched substrates of CdTe0.96Se0.04 by organometallic vapor phase epitaxy. Results are compared with those for comparable layers grown on CdTe substrates. It is shown that the use of lattice-matched substrates results in active layers of improved structural quality, as evidenced by the results of double-crystal x-ray diffraction measurements. A compositional uniformity of better than ±0.005 (in the Cd composition) was obtained over 1 cm ×2 cm area substrates, corresponding to a standard deviation of 0.0024. The thickness uniformity was better than ±0.7 μm for 12-μm-thick layers. These layers were deposited by the direct alloy growth, without the interdiffusion of separate layers of HgTe and CdTe. Both n- and p-type layers have been grown by suitable modification to the growth process. Mobility values in excess of 6×105 cm2/V s were obtained in n-type material (x=0.2), with an electron concentration below 1×1015 cm-3. With p-type layers, mobility values of 400 cm2/V s were obtained with a hole concentration of 1×1017 cm-3. [ABSTRACT FROM AUTHOR]

We report the continuous p-n junction formation in honeycomb structured Si diode by in situ boron deposition and diffusion process using low pressure chemical vapor deposition for solid-state thermal neutron detection applications. Optimized diffusion temperature of 800 °C was obtained by current density-voltage characteristics for fabricated p+-n diodes. A very low leakage current density of ∼2 × 10-8 A/cm2 at -1 V was measured for enriched boron filled honeycomb structured neutron detector with a continuous p+-n junction. The neutron detection efficiency for a Maxwellian spectrum incident on the face of the detector was measured under zero bias voltage to be ∼26%. These results are very encouraging for fabrication of large area solid-state neutron detector that could be a viable alternative to 3He tube based technology. [ABSTRACT FROM AUTHOR]

The electrical characteristics of Schottky diodes fabricated on n-type epi layers regrown over an n-drift layer and regrown over a drift layer with selective boron-implanted p-type regions have been evaluated and compared to those on virgin, as-grown commercial epi-drift layers. Slightly lower (0.1-0.2 eV) Schottky barrier heights and larger ideality factors (1.2 vs. 1.03) were extracted for the regrown diodes from forward current-voltage and capacitance-voltage measurements. Although more than 1-2 orders higher reverse leakage current were also observed, our epi-regrowth process is still considered adequate for novel power device realization. [ABSTRACT FROM AUTHOR]