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Carbyne nanocrystal (CN), as a kind of one-dimensional (1D) sp-hybridized carbon allotrope, has attracted much attention due to its excellent optical and transport properties. However, the lattice properties of 1D CNs under high temperature remain unclear. In our work, we investigate the stability and lattice properties of 1DCNs based on the atomic-bond-relaxation (ABR) approach and first-principles calculations. We find the change of transverse vibration frequencies and bond kinks induced by the thermal effect plays a significant role in the mechanical properties of 1D CNs. We establish a relationship between kink angle and phonon vibration modes, giving a deep inside into high frequency and low-frequency vibration behavior of 1D CNs. Our results indicate the phonon vibration modes modulated by kinks under applied temperatures can lead to a negative thermal expansion behavior in the axial direction of 1D CNs, suggesting an effective way to control the thermal properties of 1D CNs for practical applications.

In this work, for the first time, a machine learning behavioral modeling methodology based on gate recurrent unit (GRU) is developed and used to model and then analyze the kink effects (KEs) in the output reflection coefficient $(S_{22})$ and the short-circuit current gain $(h_{21})$ of an advanced microwave transistor. The device under test (DUT) is a 0.25- $\mu \text{m}$ gallium nitride (GaN) high electron mobility transistor (HEMT) on silicon carbide (SiC) substrate, which has a large gate periphery of 1.5 mm. The scattering (S-) parameters of the DUT are measured at a frequency up to 65 GHz and at an ambient temperature up to 200°C. The proposed model can accurately reproduce the KEs in $S_{22}$ and in $h_{21}$ , enabling an effective analysis of their dependence on the operating conditions, bias point and ambient temperature. It is worth noticing that the proposed transistor model shows also good performance in both interpolation and extrapolation test.

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Current–voltage characteristic curves of NFinFET are presented and fitted with modified current–voltage (I-V) formulas, where the modified term in the triode region is demonstrated to be indispensable. In the as-known I-V formula, important parameters need to be determined to make both the measured data and the fitting data as close as possible. These parameters include kN (associated with the sizes of the transistor and mobility), λ (associated with early voltage), and Vth (the threshold voltage). The differences between the measured data and the fitting data vary with the applied source–drain bias, proving that the mobility of the carriers is not consistently constant. On the other hand, a modified formula, called the kink effect factor, is negatively or positively added, simulating solitary heat waves or lattice vibration, which disturb the propagation of carriers and thus influence the source–drain current (IDS). The new statistical standard deviations (δ) are then found to be effectively suppressed as the kink effect is taken into account. [ABSTRACT FROM AUTHOR]

This work presents silicon-on-insulator (SOI) junction-less FETs (C-JLFET) with a pyramid P+ area within the buried oxide region (PP-JLFET). The Silvaco software analysis shows that the PP-JLFET with P+ area within the BOX layer has improved the ION/IOFF ratio of ~ 1010 and causes the proposed device to be suitable for logic operations. The principal concept of this paper concentrates on enhancing the depletion region for obtaining a smaller off-current (IOFF) ~ 10–15. Although the on-current (ION) reduced slightly, but this decrement is very small value. Also, another purpose is to achieve a better self-heating effect (SHE), which is obtained by embedding a silicon pyramid P+ area with a larger thermal conductivity than the buried oxide region. SHE improves from 308 to 325 K in the proposed device versus the conventional JLFET. Effects including carrier density, lattice temperature, SHE, and kink effect have been investigated, and the PP-JLFET results demonstrate that the proposed device improves the device characteristics versus C-JLFET. [ABSTRACT FROM AUTHOR]

Mining backfill is increasingly used in underground mine stopes around the world. A good understanding of the stress distribution in backfilled stopes is a critical concern for the design of barricades, sill mats and side-exposed backfills. In this regard, several published numerical studies reported that the vertical stress versus depth curve can exhibit an increased pace with depth near stope bottom. This phenomenon, known as kink effect, can significantly affect the stress estimation for the design of barricades and base-exposed backfill. In addition, the mechanism of kink effect has never been fully investigated, nor considered in analytical solutions developed for evaluating the stresses in backfilled stopes. In this paper, the mechanism of kink effect is first analyzed and then taken into account in an analytical solution. It is found that the occurrence of kink effect mainly depends on yield or unyield state of backfill, which is in turn determined by the Poisson's ratio μ and internal friction angle φ of the backfill. A conceptual analytical solution is then proposed to evaluate the stress distribution in 2D backfilled stopes by considering the kink effect near the bottom. The proposed solution was first calibrated by a few numerical simulations performed with FLAC2D. The results showed that kink effect takes place, starting from the bottom of stope along a height equaling to 10th and 20th of the backfill's total thickness for the vertical and horizontal stresses, respectively. The calibrated analytical solution was further validated by additional numerical simulations with different backfill properties. [ABSTRACT FROM AUTHOR]

The origin of a greater decrease in kink drain voltage $V_{kink}$ in floating body PD-SOI MOSFETs with gate lengths shorter than $0.35 ~\mu m$ is newly revealed. The $V_{kink}$ formula as a function of the internal body voltage and $I_{DS}$ is derived by combining the modified impact ionization multiplication factor with the body-source junction I-V equation. The parameters in this formula are extracted from the measured data of $I_{B}$ vs. $V_{BS}$ and ${- I}_{B}/I_{DS}$ vs. $V_{DS}$ in the body contacted devices. By calculating the formula using the extracted parameters, it is newly found that a decrease of the drain-source saturation voltage at a shorter channel is a primary cause for the short-channel effect on $V_{kink}$ reduction.

In this paper, kink effect observed in the output characteristics of the AlInN/GaN-on-Si high electron mobility transistor (HEMT) after subjecting the Si-substrate to positive/negative bias stress has been studied. The charge distribution in the different buffer layers of the wafer in the presence of different substrate-bias stress has been discussed in detail. It is concluded that the induced kink is due to the trapping/de-trapping of charge carriers through acceptor-like deep levels present in the GaN buffer layer. TCAD simulations have been performed to understand the electric-field distribution within the device layers, which is strongly related to the observed kink phenomenon. Two types of traps, acceptor-like (Ea1 = 0.52 eV) and donor-like (Ea2 = 0.44 eV), were extracted from temperature-dependent drain current transient analysis using back-gating experiment. It is concluded that a carbon-induced deep acceptor-like trap is responsible for the observed kink effect.

In this study, we present some design suggestions for all-polymer solar cells by utilizing device simulation. The polymer solar cell under investigation is formed by a photoactive film of a blend comprising PBDB-T as a polymer donor and PZT as a polymerized small molecule acceptor. The initial cell is based on a fabricated cell whose structure is ITO/PEDOT:PSS/PBDB-T:PZT/PFN-Br/Ag, which has a power conversion efficiency (PCE) of about 14.9%. A calibration procedure is then performed by comparing the simulation results with experimental data to confirm the simulation models, and the material parameters, implemented in the SCAPS (Solar Cell Capacitance Simulator) simulator. To boost the open circuit voltage, we investigate a group of hole transport layer (HTL) materials. An HTL of CuI or P3HT, that may replace the PEDOT:PSS, results in a PCE of higher than 20%. However, this enhanced efficiency results in a minor S-shape curve in the current density-voltage (J-V) characteristic. So, to suppress the possibility of the appearance of an S-curve, we propose a double HTL structure, for which the simulation shows a higher PCE with a suppressed kink phenomenon due to the proper band alignment. Moreover, the designed cell is investigated when subjected to a low light intensity, and the cell shows a good performance, signifying the cell's suitability for indoor applications. The results of this simulation study can add to the potential development of highly efficient all-polymer solar cells. [ABSTRACT FROM AUTHOR]

Current–voltage characteristic curves of NFinFET are presented and fitted with modified current–voltage (I-V) formulas, where the modified term in the triode region is demonstrated to be indispensable. In the as-known I-V formula, important parameters need to be determined to make both the measured data and the fitting data as close as possible. These parameters include kN (associated with the sizes of the transistor and mobility), λ (associated with early voltage), and Vth (the threshold voltage). The differences between the measured data and the fitting data vary with the applied source–drain bias, proving that the mobility of the carriers is not consistently constant. On the other hand, a modified formula, called the kink effect factor, is negatively or positively added, simulating solitary heat waves or lattice vibration, which disturb the propagation of carriers and thus influence the source–drain current (IDS). The new statistical standard deviations (δ) are then found to be effectively suppressed as the kink effect is taken into account.

As a transmitter power amplifier (PA), the electrical output characteristics of gallium nitride (GaN) high electron mobility transistors (HEMTs) are closely related to the drain current versus drain voltage (${I}_{d}$ – ${V}_{d}$) characteristics. Any abnormalities in the ${I}_{d}$ – ${V}_{d}$ characteristics will seriously affect device performance. Therefore, many groups have investigated the kink effect of GaN HEMTs. One of the commonly used measurement methods of the kink effect is the ${I}_{d}$ – ${V}_{d}$ forward and reverse sweep. In this study, we used the same method for Al2O3/Si3N4–AlGaN/GaN metal–insulator–semiconductor HEMT (MIS HEMT) devices. We found that not only did the kink effect occurred but ${I}_{d}$ also increased abnormally during the reverse sweep and after a series of electrical measurements. At the end of the forward sweep, impact ionization caused by a high ${V}_{d}$ generated electron–hole pairs and some holes accumulated under the gate region, which caused the negative shift of the threshold voltage (${V}_{\text{Th}}$), leading to an abnormal increase in ${I}_{d}$ during the reverse sweep. [ABSTRACT FROM AUTHOR]

We present a new silicon on insulator (SOI) laterally diffused metal oxide semiconductor (SOI-LDMOS) transistor for high power operations. Our main idea is to amend the electric field between the gate and drain area. By reducing the electric field, the created holes due to impact ionization will be amended, and the number of generated holes in the channel significantly reduces. In this work, we modify the shape of the drift region. The form of the drift area alters from the rectangular shape to the M-shape. Therefore, the M-shape drift region is extended into the buried oxide (BOX), and so we called the proposed structure as M-shape drift SOI-LDMOS (MSD-SOI-LDMOS). Due to embedding a triple N-type silicon layer into the BOX layer, we achieve two goals. First, at the higher electric field, these layers absorb the created holes due to impact ionization. Second, the impact of self-heating reduces because of silicon's higher thermal conductivity than the BOX layer. Results have shown that the proposed structure performs better with a higher breakdown voltage of about 116 V and a low specific on-resistance of about 31.2 mΩ/cm−2. [ABSTRACT FROM AUTHOR]

In this work, the kink effect (KE), typically visible in S22, is analyzed and modeled. Two different modeling techniques: equivalent circuit modeling (ECM) method and machine learning method which based on support vector regression (SVR) technique are presented and compared, when applied to the S22 behavior of a Gallium Nitride (GaN) high electron mobility transistor (HEMT). The device under test (DUT) has a width of 8 × 125 μm, with a gate feature size of 0.25 μm. The proposed method identifies the effect that the bias voltage and extrinsic elements have on the S22 kink shape. Additionally, compared to ECM, the SVR model attains a superior fitting accuracy across the complete frequency band. [ABSTRACT FROM AUTHOR]

Within the relativistic mean field approximation, we analyse the kink effect (KE) in the evolution of the charge radius isotope shift of lead isotopes as a function of the neutron number N. We show that if the interactions between neutron and proton states responsible for the KE are assumed to be proportional either to the overlaps of their corresponding wave functions or to those of their corresponding probability density distributions, it is not possible, by themselves, to explain the KE. However, we find that the small component of the single-particle Dirac spinors plays a relevant role in the kink formation. By considering the contribution of the N − 126 valence neutrons to the proton central potential, we can explain the generation of the KE and why neutrons in the 1 i 11 / 2 orbital are more kinky than when they are in the 2 g 9 / 2 orbital. [ABSTRACT FROM AUTHOR]

In this study, we present some design suggestions for all-polymer solar cells by utilizing device simulation. The polymer solar cell under investigation is formed by a photoactive film of a blend comprising PBDB-T as a polymer donor and PZT as a polymerized small molecule acceptor. The initial cell is based on a fabricated cell whose structure is ITO/PEDOT:PSS/PBDB-T:PZT/PFN-Br/Ag, which has a power conversion efficiency (PCE) of about 14.9%. A calibration procedure is then performed by comparing the simulation results with experimental data to confirm the simulation models, and the material parameters, implemented in the SCAPS (Solar Cell Capacitance Simulator) simulator. To boost the open circuit voltage, we investigate a group of hole transport layer (HTL) materials. An HTL of CuI or P3HT, that may replace the PEDOT:PSS, results in a PCE of higher than 20%. However, this enhanced efficiency results in a minor S-shape curve in the current density-voltage (J-V) characteristic. So, to suppress the possibility of the appearance of an S-curve, we propose a double HTL structure, for which the simulation shows a higher PCE with a suppressed kink phenomenon due to the proper band alignment. Moreover, the designed cell is investigated when subjected to a low light intensity, and the cell shows a good performance, signifying the cell’s suitability for indoor applications. The results of this simulation study can add to the potential development of highly efficient all-polymer solar cells.

This article presents the study of trapping effects in AlGaN/GaN high electron mobility transistors (HEMTs). Conventional methods like temperature-dependent capacitance-voltage (CV) and pulsed-IV (PIV) have been employed to quantify the traps present in the device layers. Apparent threshold voltage (VTH) instability as well as lag in the drain current after pulsing are evident. The kink in the drain current has been taken up to observe the trapping signature for devices with two different gate lengths. A modified drain and gate pumping methodology which has been designated as pre-measurement run (PMR) has been presented to get a deeper insight into the kink effect in these devices. Constant maximum field (CMF) PMR shows substantial change in the drain current, whereas negligible change for variable maximum field (VMF) PMR is observed, which confirms the dominant impact of trapping within the heterostructure and field assisted detrapping through Poole-Frenkel emission. Multiple traps have also been identified within the epitaxial layers with the E2 trap (Ea (activation energy) = 0.69 eV) which can be held responsible for the kink observed in the DC characteristics as observed from pulsed drain lag characteristics. [ABSTRACT FROM AUTHOR]

Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18μm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10μm/10μm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.

Four-terminal poly-Si thin-film transistors (TFTs), with a counter-doped body terminal connected to the floating channel, can suppress both dc and dynamic hot-carrier (HC) degradation of TFTs. With 3-D TCAD simulation, we clarify the underlying mechanisms of the suppression effect and analyze its dependence on the position and width of the body terminal. Under dc HC condition, a wider body terminal or that closer to the drain collects more holes generated from impact ionization in the drain depletion region and suppresses the parasitic bipolar junction transistor effect, subsequently reduces the kink current more effectively. Under dynamic HC condition, the body terminal injects holes at the end of the falling time of the gate pulse, partially removes the non-equilibrium state, significantly relieves the transient maximum electric field in the drain depletion region, thus suppresses the dynamic HC degradation. A wider body terminal can inject more holes and the holes injected by that closer to the drain diffuse to drain depletion region first, thus suppress the dynamic HC degradation better.

In this article, a new metal-semiconductor field-effect transistor (MESFET) is introduced by amending the carrier distribution in the active regions of the device for radio frequency applications (RF). A quasi-two-dimensional material beta gallium oxide (β-Ga2O3) semiconductor is used as a fundamental material. To amend the carrier distribution, a tunnel diode (TD- β GO) is employed at the bottom of the source and the channel regions in the buried oxide (BOX) layer of MESFET. In our work, parameters such as the breakdown voltage, the self-heating effect, the kink effect, the parasitic capacitance, the power gains, the noise figure, and the carrier’s concentration are obtained and compared with the conventional structure. As a result of employing the tunnel diode, the TD-β GO MESFET has better characteristics in comparison with the C-β GO MESFET though the drain current at the saturation region in the TD- ${\beta }$ GO structure is reduced. [ABSTRACT FROM AUTHOR]

In this investigation, extensive simulations were performed for an AlGaN/GaN Dual-Gate MISHEMT configuration using ATLAS TCAD to optimize the device design for high power switching applications. We conducted a simulation study for the breakdown characteristics of a Dual-Gate AlGaN/GaN (DG)-MISHEMT with different gate lengths as explained in this paper. The optimized device with 0.25 µm gate length exhibits an breakdown voltage > 700 V and an cut-off frequency of 50 GHz when gate2 (G2) is attached to the source and bias is applied at gate1 (G1). We studied the impact on a breakdown characteristics and the frequency performance of different dimensions such as distance between the two gates (LGG), gate1-to-source distance (LG1S) and gate1-to-drain distance (LG1D). The optimized device design was further used to study the scattering-parameters for different gate combinations. Further improvement in breakdown voltage and Johnson's figure of merit (fT × VBR) is achieved for the DG-MISHEMT with HfO2–Al2O3 as gate insulator. [ABSTRACT FROM AUTHOR]

We report sub-micron channel length ($0.5~\mu \text{m}$), low-temperature polysilicon (LTPS) thin-film transistor (TFT) using blue laser annealing (BLA) for ultra-high-resolution displays. The TFTs exhibited negligible kink effect in output characteristics with excellent negative bias temperature stability. Protrusion-free BLA LTPS is evident from the transmission electron microscopy (TEM) image. Technology computer-aided design (TCAD) simulation reveals that the protruded LTPS with grain boundaries has ~1.4 times higher electric field than protrusion-free LTPS. This causes high impact generation rate of ${3.76}\times {10}^{{14}}$ cm−3s−1 ~8 times) compared to ${4.64}\times {10}^{{13}}$ cm−3s−1 for protrusion-free LTPS TFTs. It is demonstrated that protrusion-free LTPS can achieve kink-free, sub-micron short channel devices. [ABSTRACT FROM AUTHOR]

In this work, GaN|AlGaN high electron mobility transistor (HEMT) structures are investigated, grown on semi-insulating SiC substrates by molecular beam epitaxy and metal–organic chemical-vapor deposition techniques. This paper reports on the kink effect and hysteresis effect observed in AlGaN|GaN high electron mobility transistors (HEMTs) on SiC substrate. It is well known that trapping effects can limit the output power performance of microwave HEMTs, which is particularly true for the wide band gap devices. A detailed study is presented of FT-DLTS and CDLTS measurements performed on AlGaN|GaN HEMTs. It is demonstrated that the kink effect is directly correlated to shallow traps, and a remarkable correlation exists between deep levels observed by CDLTS and FT-DLTS and the presence of parasitic effects such as kink and hysteresis effects. [ABSTRACT FROM AUTHOR]

A cryogenic investigation of the Kink effect with drain-source bias sweeping process during output characteristics is suggested. An exhaustive study of the field effect dependence on the emission rate from hole traps in AlGaN/GaN HEMT transistors has been realized by means of current DLTS spectroscopy (I-DLTS). We have found that the Kink effect was induced by impact ionization of electron trapped in acceptor-like deep levels with activation energies at about 0.85 eV overhead the valence band of the GaN buffer layer. Using I-DLTS method, three holes traps, labeled A, H1, and H5, have been distinguished. The H1 deep level might correspond to the carbon substituting the N site (CN) which is supposed to be the main cause of the Kink effect. The major H5 trap seems to be gallium vacancy complex (VGa–ON). For the hole trap H1, the phonon-assisted tunneling emission is the dominant mechanism for holes to escape from the trapping centers while for the H5 trap their field dependence shows a classical pure tunneling effect. [ABSTRACT FROM AUTHOR]

This study examines the appearance of a kink effect phenomenon in the I $_{\mathbf {D}}$ -V $_{\mathbf {D}}$ electrical characteristics of low-temperature polycrystalline Si thin-film transistors (LTPS TFTs) after high-current-induced hot-carrier stress (HCS). During HCS, electron–hole pairs were generated in the channel near the drain terminal owing to impact ionization. Next, the electrons were repelled towar the source by the drain electric field, thereby inducing the floating body effect, which lowered the source barrier. In addition, a dual-gate-structured LTPS was found to inhibit the electrical degradation caused by HCS. The COMSOL simulation indicated that in the dual-gate structure, holes at the upper and lower margins of the channel were inverted and inhibited the degradation caused by the floating body effect. Therefore, the use of dual-gate LTPS TFTs could facilitate high-current gate-on-array circuit applications in display panels. [ABSTRACT FROM AUTHOR]

The raised source/drain (RSD) structure is one of thin film transistor designs that is often used to improve device characteristics. Many studies have mentioned that the high impact ionization rate occurring at a drain side can be reduced, owing to a raised source/drain area that can disperse the drain electric field. In this study, we will discuss how the electric field at the drain side of an RSD device is reduced by a vertical lightly doped drain (LDD) scheme rather than a RSD structure. We used different raised source/drain forms to simulate the drain side electric field for each device, as well as their output characteristics, using Integrated Systems Engineering (ISE-TCAD) simulators. Different source and drain thicknesses and doping profiles were applied to verify the RSD mechanism. We found that the electric fields of a traditional device and uniform doping RSD structures are almost the same (~2.9 × 105 V/cm). The maximum drain electric field could be reduced to ~2 × 105 V/cm if a vertical lightly doped drain RSD scheme was adopted. A pure raised source/drain structure did not benefit the device characteristics if a vertical lightly doped drain design was not included in the raised source/drain areas.

The kink effect, long observed in GaN high electron mobility transistors (HEMTs), is investigated with the Fermi kinetics transport hot electron simulation method. Fermi kinetics assigns piecewise Fermi-Dirac electron distributions to the conduction band valleys determined by the GaN electronic band structure and computes their behavior according to the thermodynamics of ideal Fermi gases. Charge fluxes are determined from moments of the Boltzmann equation, including nonparabolic electron densities of states and group velocities, as well as phonon and ionized impurity scattering. The model has been further generalized to include field-enhanced tunneling ionization of deep traps. Comparing simulations with measured data suggests that the kink effect could be caused by field-enhanced ionization of deep AlGaN barrier traps beneath the gate and close to the GaN/AlGaN interface. Further simulations indicate hot electrons may play key roles in both the trap emission and capture processes. [ABSTRACT FROM AUTHOR]

Cryogenic characterisation and modelling of 0.18μm CMOS technology (1.8 and 5 V) is presented in this Letter. Several P‐type MOS and N‐type MOS transistors with different width to length ratios were extensively characterised under various bias conditions at temperatures ranging from 300 K down to 4.2 K. The authors extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. A simple subcircuit was built to correct the kink effect. The RMS error of test results and modelling results is <3%. [ABSTRACT FROM AUTHOR]

The drain conductance oscillations are simultaneously observed in the trigated and double-gated poly-Si junctionless (JL) nanowire thin-film transistors (TFTs). The strongest oscillations appear at ${V} _{\text {GS}}$ of 1 V and $V_{\text {DS}}$ of 4–5 V/6–7 V in 0.35- $\mu \text{m}$ /5- $\mu \text{m}$ poly-Si JL nanowire TFTs. To explain the drain conductance oscillations, in addition to the separated sub-bands and Coulomb blockade effect, the space-charge-potential barrier/grain boundary (GB) potential barrier in the channel and the kink effect in the output characteristics should be considered. The space-charge-potential barrier is affected by the unstable trapped electrons at GB and leads to the drain conductance oscillations. Due to the kink effect, an anomalous increase of the current in the output characteristics can enhance the conductance oscillations. Moreover, the channel of the double-gated device shows higher degree of crystallinity by solid-phase crystallization. Compared with the trigated device without solid-phase crystallization, less GB potential barriers in the channel of the double-gated device lead to a higher mobility in the channel, and these electrons can easily destroy the stability of the trapped electrons at the GBs, resulting in the stronger drain conductance oscillations. Therefore, the physical mechanisms are proposed to understand the drain conductance oscillations well in poly-Si JL nanowire TFTs. [ABSTRACT FROM AUTHOR]

This paper evaluates the applicability of pulsed I–V measurements as a tool for accurately extracting nonlinear gallium nitride (GaN)-based heterojunction field-effect transistor (HFET) models. Two wafers with the identical layer structure but different growth conditions have been investigated. A series of I–V measurements was performed under dc and pulsed conditions demonstrating a dramatic difference in the kink effect and current collapse (knee walkout) suggesting different trapping behaviors. However, when radio frequency (RF) I–V waveform measurements, utilizing active harmonic load–pull, were used to study the impact of these traps on the RF performance, both wafers gave good overall RF performance with no significant difference observed. This absence of correlation between pulsed I–V measurement results and RF performance raises a question about the applicability of pulsed I–V measurements alone as a tool for extracting nonlinear device models in the case of GaN HFETs. [ABSTRACT FROM AUTHOR]

The anomalous kink effect was investigated in n-type low-temperature polycrystalline silicon thin-film transistors with the source-contacted bottom-shield-metal (SBSM) layer on a polyimide substrate. Using experiments and technology computer-aided design simulation, it was found that the SBSM layer plays a critical role in the anomalous kink effect. The SBSM layer modulated the carrier concentration within the lightly doped drain (LDD) region according to the applied drain voltage ($\text{V} _{\text{DS}}$). In addition, this carrier modulation caused changes in the lateral electric field at simultaneously the channel/LDD junction and the LDD/n+ junction. Thus, multiple kink effects, different from the conventional kink effect, occurred in two different $\text{V} _{\text{DS}}$ regions with different slopes depending on the LDD length ($\text{L}_{\text{LDD}}$) and the overlap length ($\text{L}_{\text{BSM}}$) between the LDD region and the SBSM layer in the drain region. We propose a novel asymmetric design to suppress the SBSM-induced anomalous kink effect in all $\text{V}_{\text{DS}}$ regimes. This design has the following requirements with respect to $\text{L}_{\text {LDD}}$ and $\text{L}_{\text {BSM}}$ at the drain region: $\text{L}_{\text {BSM}}$ greater than $1.0~\mu \text{m}$ , $\text{L}_{\text {LDD}} - \text{L}_{\text {BSM}}$ (LLDD) greater than $1.0~\mu \text{m}$ , and $\text{L}_{\text {BSM}}$ equal to half of $\text{L}_{\text {LDD}}$. [ABSTRACT FROM AUTHOR]

We report on a floating buffer model to explain “kink,” a hysteresis in the output characteristics of Fe-doped AlGaN/GaN HEMTs observed at low drain bias. Unintentionally doped background carbon can make the GaN buffer p-type allowing it to electrically float. We further note that reverse bias trap-assisted leakage across the junction between the 2DEG and the p-type buffer can provide a mechanism for hole injection and buffer discharging at just a few volts above the knee, explaining the “kink” bias dependence and hysteresis. We show that HEMTs with a different background carbon have dramatically different kink behaviors consistent with the model. Positive and negative magnitude drain current transient signals with 0.9-eV activation energy are seen, corresponding to changes in the occupation of carbon acceptors located in different regions of the GaN buffer. The observation of such signals from a single trap calls into question conventional interpretations of these transients based on the bulk 1-D deep-level transient spectroscopy (DLTS) models for GaN devices with floating regions. [ABSTRACT FROM AUTHOR]

Results specific to power amplifiers (PAs) designed using a SOI EDNMOS transistor free of kinks in ID-VD plane and high breakdown voltage are presented. The suppression of the drain current kink and improvement in breakdown voltage are achieved by the omission of the N+ source implant step. Instead, the source junction is realized by an optimized NLDD implant step only, allowing the formation of an under-source body contact. This approach is highly suitable for integration with RF switch and low-noise amplifiers on the same thin film SOI substrate. The improved channel conductance is found to give rise to highly linear amplitude and phase characteristics under high power conditions when the optimized EDNMOS device is used standalone as a PA. [ABSTRACT FROM AUTHOR]

Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling effect. For the first time, thanks to the availability of body contacts, the body potential is probed to evidence the impact of majority carrier accumulation and drain pulse duration on the kink effect onset. [ABSTRACT FROM AUTHOR]

In this paper, a novel step gate-overlapped lightly doped drain (GOLDD) with raised source/drain (RSD) structure (SGORSD) is proposed for TFT electronic device application. The new SGORSD structure could obtain a low electric field at channel near the drain side owing to a step GOLDD design. Compared to the conventional device, the SGORSD TFT exhibits a better kink effect and higher breakdown performance due to the reduced drain electric field (D-EF). In addition, the leakage current also can be suppressed. Moreover, the device stability, such as the threshold voltage shift and drain current degradation under a high gate bias, is improved by the design of SGORSD structure. Therefore, this novel step GOLDD structure can be a promising design to be used in active-matrix flat panel electronics. [ABSTRACT FROM AUTHOR]

Low power consumption has become one of the major requirements for most microelectronic devices and systems. Increasing power dissipation may lead to decreasing system efficiency and lifetime. The BULK metal oxide semiconductor field-effect transistor (MOSFET) has relatively high power dissipation and low frequency response due to its internal capacitances. Although the silicon-on-insulator (SOI) MOSFET was introduced to resolve these limitations, other challenges were introduced including the kink effect in the current-voltage characteristics. The selective buried oxide (SELBOX) MOSFET was then suggested to resolve the problem of the kink effect. The authors have previously investigated and reported the characteristics of the SELBOX structure in terms of kink effect, frequency, thermal and static power characteristics. In this paper, we continue our investigation by presenting the dynamic power characteristics of the SELBOX structure and compare that with the BULK and SOI structures. The simulated fabrication of the three devices was conducted using Silvaco TCAD tools in 90 nm complementary metal oxide semiconductor (CMOS) technology. Simulation results show that the average dynamic power dissipation of the CMOS BULK, SOI and SELBOX are compatible at high frequencies with approximately 54.5 µW. At low frequencies, the SOI and SELBOX showed comparable dynamic power dissipation but with lower values than the BULK structure. The difference in power dissipation between the SELBOX and BULK is in the order of nano watts. This power difference becomes significant at the chip level. For instance, at 1 MHz, SOI and SELBOX exhibit an average dynamic power consumption of 0.0026 µW less than that of the BULK structure. This value cannot be ignored when a chip operates using thousands or millions of SOI or SELBOX MOSFETs.

In this paper, the effect of electron irradiation fluence on direct current (DC) and radio frequency (RF) of InP-based high electron mobility transistors (HEMTs) was investigated comprehensively. The devices were exposed to a 1 MeV electron beam with varied irradiation fluences from 1 × 1014 cm−2, 1 × 1015 cm−2, to 1 × 1016 cm−2. Both the channel current and transconductance dramatically decreased as the irradiation fluence rose up to 1 × 1016 cm−2, whereas the specific channel on-resistance (Ron) exhibited an apparent increasing trend. These changes could be responsible for the reduction of mobility in the channel by the irradiation-induced trap charges. However, the kink effect became weaker with the increase of the electron fluence. Additionally, the current gain cut-off frequency (fT) and maximum oscillation frequency (fmax) demonstrated a slightly downward trend as the irradiation fluence rose up to 1 × 1016 cm−2. The degradation of frequency properties was mainly due to the increase of gate-drain capacitance (CGD) and the ratio of gate-drain capacitance and gate-source capacitance (CGD/CGS). Moreover, the increase of Ron may be another important factor for fmax reduction.

A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and drain regions. The modified source region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified drain region causes high breakdown voltage (462 V) and low specific on-resistance ( 5.1~\text m\Omega \cdot ~\text cm^2) . Also, the drift region with lower doping density than drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance. [ABSTRACT FROM PUBLISHER]

Double gate silicene field effect transistor is investigated using Density Functional Theory (DFT) and Non-Equilibrium Green's Function (NEGF) formalism. The results suggest that with an increase in gate bias, bandgap is introduced in silicene which results in reduction in device current. The increase in silicene bandgap is also related to the reduction in channel length. It is observed that drain to source current (I DS ) saturates on increasing drain to source voltage (V DS ). On increasing V DS beyond saturation region, at some value of V DS kink effect is seen which is due to switching in the type of carriers at the drain end due to ambipolar channel. Transconductance (g m ) is seen to reduce with reduction in channel length, however, g m improves with reduced oxide thickness due to better gate controllability. The output characteristics do not change much with oxide thickness. [ABSTRACT FROM AUTHOR]

This study presents an improved large signal model that can be used for high electron mobility transistors (HEMTs) and field effect transistors using measurement-based behavioural modelling techniques. The steps for accurate large and small signal modelling for transistor are also discussed. The proposed DC model is based on the Fager model since it compensates between the number of model’s parameters and accuracy. The objective is to increase the accuracy of the drain-source current model with respect to any change in gate or drain voltages. Also, the objective is to extend the improved DC model to account for soft breakdown and kink effect found in some variants of HEMT devices. A hybrid Newton’s–Genetic algorithm is used in order to determine the unknown parameters in the developed model. In addition to accurate modelling of a transistor’s DC characteristics, the complete large signal model is modelled using multi-bias s-parameter measurements. The way that the complete model is performed is by using a hybrid multi-objective optimisation technique (Non-dominated Sorting Genetic Algorithm II) and local minimum search (multivariable Newton’s method) for parasitic elements extraction. Finally, the results of DC modelling and multi-bias s-parameters modelling are presented, and three-device modelling recommendations are discussed. [ABSTRACT FROM PUBLISHER]

In plastic OLED (POLED) displays, bottom shield metal (BSM) layer is applied to eliminate the effect of mobile charges within plastic substrate. However, this BSM causes the abnormal kink effect, which is significantly different from the conventional LTPS TFTs with LDD. In the study, we investigated the abnormal kink effect in n-type LTPS TFTs with BSM, especially, which is contacted by source electrode. Using experiments and TCAD simulation, we confirmed and analyzed that this kink characteristic is induced by source contacted BSM and strongly dependent on Active-Buffer layer thickness, LDD length, and BSM length. [ABSTRACT FROM AUTHOR]

The synthesis of 1,4-disubstituted-[1,2,3]-triazoles involving the addition of aryl azide to terminal acetylenes and ethyl acetoacetate are employed in the preparation of a series of non-linear mesogens having ester and imine as linking units. The structures of final compounds and their intermediates are characterized by FTIR, ¹HNMR and 13CNMR spectroscopy. Optical microscopy and differential scanning calorimetry confirm structural information of liquid crystal phases of mesogens. The final compounds reveal preferentially well-defined threaded nematic phases. In addition, they show weak fluorescence in solution with poor quantum yields and a Stokes shift of around 70 nm. [ABSTRACT FROM AUTHOR]

A new multiple-gate poly-Si thin-film transistor (TFT) with a bottom field plate (FP) is proposed. The FP disperses the high current density away from the top corner of the spacer channel with the highest electric field, leading to an improved kink effect. Moreover, owing to an inversion layer induced by the FP at the bottom region of spacer poly-Si channel, a higher on-state current is achieved. In addition, the electric field near drain area is reduced, leading to a lower off-state current. Overall, the new multiple-gate poly-Si TFT shows improved characteristics as compared with the counterpart without a bottom FP. [ABSTRACT FROM PUBLISHER]

In this letter, a high-current kink effect free Z-gate polycrystalline silicon (poly-Si) thin-film transistor (ZG-TFT) is proposed and demonstrated. The ZG-TFT, which is formed by a raised source/drain (RSD) region and a split channel (SC) structure, reveals better device performance. Our experimental results show that the ON-current of ZG-TFT is about two times higher than that of a conventional single top gate TFT, and the leakage current is greatly reduced simultaneously. In addition, the high drain electric field is considerably reduced by the RSD structure, and the SC design can further effectively suppress the kink effect. Therefore, a better ON/OFF current ratio and a higher drain breakdown voltage can be achieved. [ABSTRACT FROM PUBLISHER]

We developed bottom-gate poly-Si TFTs (BGPs) using ELA for high resolution AMOLED. The BGPs based on our novel process to solve the disconnection of poly-Si during ELA crystallization have better reliability characteristics such as breakdown voltage (BV) and kink effect compared with the conventional top-gate poly-Si TFTs. [ABSTRACT FROM AUTHOR]

To integrate the function of finger‐print recognition within the OLED display panel, a light‐shield (LS) metal layer is incorporated underneath the buffer layer to form fingerprint image on the sensor based on the principle of puncture‐forming picture. Since the LS metal layer is underneath the LTPS TFT, it has some impact on the IV performance of the p‐type LTPS TFT. It has been shown that the floating LS layer causes the kink effect on the output characteristics curves of the p‐type TFT. Upon putting bias on the LS layer, the threshold voltage (Vth) shifting has been observed as well as the eliminating of the kink effect caused by the floating LS layer. The Vth shifting effect may be explained by the substrate bias effect. The biased LS layer may increase the uniformity of the threshold voltage throughout the whole panel, gives better image quality. [ABSTRACT FROM AUTHOR]

Nanoscale MOSFETs Gate-Recessed Channel (GRC) device with a silicon channel thickness (tSI) as low as 2.2 nm was first tested at room temperature for functionality check, and then tested at low temperature (77 K) for I–V characterizations. In spite of its FD-SOI nanoscale thickness, the GRC device has surprisingly exhibited a Kink Effect in the output characteristics at 77 K. The anomalous Kink Effect can be explained by the increase of the lateral electric field in the drain junction with the channel extension zone when lowering the temperature. [ABSTRACT FROM AUTHOR]

In this paper, critical electrical characteristics of a nanoscale low-voltage partially-depleted silicon-on-insulator (PD-SOI) MOSFET have been improved in terms of floating body effect, short channel effects, subthreshold swing, leakage current, self-heating effect, voltage gain, parasitic bipolar device effect, parasitic capacitance, and unilateral power gain. The heart of the proposed structure is a dual tunnel diode formed by a heavily doped P-type L-shaped trench. The accumulated holes are effectively released by the tunnel current of the dual tunnel diode. The proposed structure is found to be free of kink effect. Other substantial parameters of the proposed structure have been improved owing to L-shaped trench. Comparing the proposed structure with a conventional SOI (C-SOI), the proposed structure is considered as an undeniable contender in nanoscale integrated applications. [ABSTRACT FROM AUTHOR]

This brief presents a nanoscale low-voltage partially depleted silicon-on-insulator (SOI) structure with improved electrical performance. The brain of the proposed structure is a dual tunnel diode (DTD) composed of a heavily doped p-type L-shaped trench. The accumulated holes are effectively released by the tunnel current of DTD, thus reducing the critical kink effect. Compared with a conventional SOI, the proposed structure is considered as an efficient rival in nanoscale-integrated applications. [ABSTRACT FROM AUTHOR]