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Compute-in-memory (CIM) is an attractive solution to address the “memory wall” challenges for the extensive computation in deep learning hardware accelerators. For custom ASIC design, a specific chip instance is restricted to a specific network during runtime. However, the development cycle of the hardware is normally far behind the emergence of new algorithms. Although some of the reported CIM-based architectures can adapt to different deep neural network (DNN) models, few details about the dataflow or control were disclosed to enable such an assumption. Instruction set architecture (ISA) could support high flexibility, but its complexity would be an obstacle to efficiency. In this article, a runtime reconfigurable design methodology of CIM-based accelerators is proposed to support a class of convolutional neural networks running on one prefabricated chip instance with ASIC-like efficiency. First, several design aspects are investigated: (1) the reconfigurable weight mapping method; (2) the input side of data transmission, mainly about the weight reloading; and (3) the output side of data processing, mainly about the reconfigurable accumulation. Then, a system-level performance benchmark is performed for the inference of different DNN models, such as VGG-8 on a CIFAR-10 dataset and AlexNet GoogLeNet, ResNet-18, and DenseNet-121 on an ImageNet dataset to measure the trade-offs between runtime reconfigurability, chip area, memory utilization, throughput, and energy efficiency.

The requirement of multilevel cell (MLC) resistive random access memory (RRAM) for computing is different than that for MLC storage. It generally requires a linearly spaced conductance median and an ultratight conductance distribution, as the column current are summed up for analog computation. In this article, 3-bit per cell RRAM that is suitable for accurate inference of a deep neural network (DNN) is demonstrated, with ultratight conductance distribution ( $5.3 \times $ and $4.4 \times $ , respectively, compared to the 3-bit per cell RRAM used as MLC storage.

The multilevel resistive random access memory (RRAM)-based synaptic array can enable parallel computations of vector–matrix multiplication for machine learning inference acceleration; however, any conductance drift of the cell may induce an inference accuracy drop because the analog current is summed up along the column. In this article, the read disturb-induced conductance drift characteristic is statistically measured on a test vehicle based on 2-bit HfO2 RRAM array. The drift behavior of four states is empirically modeled by a vertical and lateral filament growth mechanism. Furthermore, a bipolar read scheme is proposed and tested to enhance the resilience against the read disturb. The modeled read disturb and proposed compensation scheme are incorporated into a VGG-like convolutional neural network for CIFAR-10 data set inference.

In-memory computing with analog nonvolatile memories can accelerate the in situ training of deep neural networks. Recently, we proposed a synaptic cell of a ferroelectric transistor (FeFET) with two CMOS transistors (2T1F) that exploit the hybrid precision for training and inference, which overcomes the challenges of nonlinear and asymmetric weight update and achieves nearly software comparable training accuracy at the algorithm level. In this paper, we further present the circuit-level benchmark results of this hybrid precision synapse in terms of area, latency, and energy. The corresponding array architecture is presented and the array-level operations are illustrated. The benchmark is conducted by multilayer-perceptron (MLP) + NeuroSim framework with comparison to other capacitor-assisted (e.g., 3T1C + 2PCM) hybrid precision cell. The design tradeoffs and scalability are discussed between different implementations.

Different from the multilevel cell (MLC) memory where the crossover between tail bits matters, any drift of the conductance of the synaptic device induced by read disturb may aggregate, as the analog current is summed up along the column. In this work, we experimentally measured the conductance drift on 2-bit HfO 2 RRAM array based on 1-transsitor-1-resistor (1T1R) test vehicle. The drift behavior of different states is modeled by vertical and lateral filament growth and saturation. The device model is incorporated into a VGG-like convolutional neural network algorithm for CIFAR-10 dataset. Read voltage should be minimized to 0.3V or below to maintain the inference accuracy.

Compute-in-memory (CIM) with emerging non-volatile memories (eNVMs) is time and energy efficient for deep neural network (DNN) inference. However, challenges still remain for in-situ DNN training with eNVMs due to the asymmetric weight update behavior, high programming latency and energy consumption. To overcome these challenges, a hybrid precision synapse combining eNVMs with capacitor has been proposed. It leverages the symmetric and fast weight update in the volatile capacitor, as well as the non-volatility and large dynamic range of the eNVMs. In this paper, in-situ DNN training architecture with hybrid precision synapses is proposed and benchmarked with the modified NeuroSim simulator. First, all the circuit modules required for in-situ training with hybrid precision synapses are designed. Then, the impact of weight transfer interval and limited capacitor retention time on training accuracy is investigated by incorporating hardware properties into Tensorflow simulation. Finally, a system-level benchmark is conducted for hybrid precision synapse compared with baseline design that is solely based on eNVMs.

A novel ferroelectric semiconductor junction (FSJ) based two-terminal memristor is demonstrated as a synaptic device for the first time. In this novel FSJ device, a metal-ferroelectric semiconductor (FS)-metal crossbar structure is used, instead of a metal-ferroelectric insulator-metal structure for a conventional ferroelectric tunnel junction (FTJ), so that an ultra-thin ferroelectric insulator is not required. Meanwhile, the FSJ also offers energy efficiency advantage over the conventional filament-based resistive random access memory (RRAM) device because the conductance of the FSJ scales with the junction area. Experimentally, a ferroelectric semiconductor α-In 2 Se 3 based crossbar FSJ (c-FSJ) as a synaptic device is demonstrated. Ferroelectric resistive switching is clearly observed in both planar FSJ (p-FSJ) by in-plane polarization switching and c-FSJ by out-of-plane polarization switching. Conductance potentiation and depression in the c-FSJ are measured and benchmarked at both original size and projected to 32 nm node with different synaptic devices. α-In 2 Se 3 c-FSJ shows good on-line learning accuracy (~92 %), low latency and energy consumption due to the short write pulse width and large R ON .

A versatile multiphysics simulation packet for investigating different resistive random acces memories (RRAMs) is developed in this paper. Heat transfer, electrical conduction, and ion migration in such heterogeneous structure are all taken into consideration. Three fully coupled partial differential equations are solved using our self-developed finite-difference algorithm, where Scharfetter–Gummel method is adopted to simulate ion migration with fast convergence achieved. This packet is validated in comparison with the commercial software based on the finite-element method. With its implementation, complete and clear pictures for crosstalk effect in vertically integrated RRAM are captured and compared, where the effects of key physical and geometrical factors are characterized and understood. Some useful suggestions to mitigate its unfavorable influences are given.

Resistive random access memory (RRAM) is a promising candidate for next generation nonvolatile memory technology. In this paper, electrothermal simulation in 3-D RRAM arrays is performed by using our in-house developed finite difference algorithm, which is validated by comparing the simulated temperature distribution with its counterpart obtained by commercial software. Both crossbar RRAM array and vertical RRAM array are studied comprehensively with careful consideration of the temperature-dependent constitute parameters. Simulations show that the temperature and thermal crosstalk are sensitive to the size and shape of conductive filament, which can further limit the scaling potential of RRAM array through affecting its reliability, such as retention time, current leakage, and so on. Scaling behavior of 3-D RRAM array is studied, and optimization guidance for reducing thermal crosstalk is proposed. The fabrication inaccuracy resulted cell offset has also been examined for investigation of thermal crosstalk.

On-chip learning with compute-in-memory (CIM) paradigm has become popular in machine learning hardware design in the recent years. However, it is hard to achieve high on-chip learning accuracy due to the high nonlinearity in the weight update curve of emerging nonvolatile memory (eNVM) based analog synapse devices. Although digital synapse devices offer good learning accuracy, the row-by-row partial sum accumulation leads to high latency. In this paper, the methods to solve the aforementioned issues are presented with a device-to-algorithm level optimization. For analog synapses, novel hybrid precision synapses with good linearity and more advanced training algorithms are introduced to increase the on-chip learning accuracy. The latency issue for digital synapses can be solved by using parallel partial sum read-out scheme. All these features are included into the recently released MLP + NeuroSimV3.0, which is an in-house developed device-to-system evaluation framework for neuro-inspired accelerators based on CIM paradigm.

At UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS), we have been developing a fine pitch heterogeneous wafer-scale platform with a single level of hierarchy called the silicon interconnect fabric (Si-IF). The Si-IF is a platform for heterogeneous integration of different bare dies at fine pitch (2 to 10 µm) and close proximity (

Low throughput has been a critical issue in extreme ultraviolet (EUV) patterning due to the difficulty in increasing light source power. This limitation has driven the need for photoresists with better throughput which unfortunately come with higher line edge roughness (LER). In this work, the possibility of relaxing LER requirements for metal layer patterned by EUV lithography (EUVL) is studied. Single patterning and litho-etch litho-etch (LELE) patterning with EUVL are considered. To assess the impact of LER on design yield, analytical and simulation based modeling approaches are developed, which consider the LER induced metal wire shorts/opens and the enhanced time dependent dielectrics breakdown (TDDB) for metal wires with different geometries. The impact of LER on wire delay is studied by Elmore’s delay model.

Memory is very important in the present era of Internet of Thing (IoT) and Big Data, while Resistive Random Access Memory (RRAM) is a key member in the family of non-volatile memory. However, in the development of high density RRAM memory array, self-heat effect (SHE) as well as thermal crosstalk must be understood and controlled during its operation. In this paper, simulation of electrothermal effects in both single RRAM cell and 3×3×3 array are performed using our in-house developed algorithm, which is validated in comparison with that of commercial software COMSOL. Further on, hybrid effects of different geometrical and material parameters on the memory performance are characterized and addressed.