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This work presents the low frequency noise and the electric performances in terms of output/transfer characteristics, threshold voltage, and short channel effect in both NMOS and PMOS transistors for 0.1 μm technologies. For the last one there are two architectures based either on a surface mode of operation (surface channel) or on a buried one (buried channel) featuring either a P+ or a N+ polysilicon gate material. The impact of the channel length on the noise characteristics as well as on the output/transfer characteristics is studied. We find that the 1/f noise can be interpreted in terms of carrier number fluctuations for both N and P channel MOSFETs for surface and buried mode of operation. The oxide trap density Nt is therefore evaluated, demonstrating an overall good oxide quality.

A detailed characterization of the gate and drain current characteristics has been carried out on NMOS transistors featuring ultra-thin gate oxides (1.2–2.3 nm). A quasi-analytical model of both gate and drain currents has been worked out and validated in ohmic and saturation regions. The impact of gate current on MOSFET operation has been shown to be critical for large area devices but of less importance for nominal devices, indicating that, down to 1.2 nm, the gate oxide thinning is not detrimental to the device functionality.

This paper reports the Capacitance–Voltage (C–V) characterization of gate oxide in the 20 A thickness range, dealing especially with quantum and polysilicon effects. In the first part, the basis of Poisson–Schrodinger modeling is summarized. The extraction procedure of doping level, flat band voltage, threshold voltage, and oxide thickness is presented. A simple method to extract the polysilicon doping level and to correct for polysilicon effect on C(V) curves is proposed. These parameter extraction procedures are illustrated by experimental data obtained on both NMOS and PMOS transistors.

The characterization of LF noise and RTS fluctuations in 0.18μm CMOS devices is presented. It is found that the 1 f noise results from carrier number fluctuations for both N and P MOS devices. The slow oxide trap density deduced from the noise data lies around 1017/eV/cm3 in agreement with state-of-the-art gate oxides. Drain current RTS amplitude as large as 5–10% have been observed, being somewhat larger than for 0.35μm CMOS technology but comparable to those obtained in 0.25μm CMOS devices.

A detailed study of the low frequency noise in Si MOS devices from a 0.35 μ m CMOS technology is presented. The normalized drain current noise WLS I d /I d 2 has been systematically investigated at a fixed frequency and constant normalized drain current. In large area devices (>5–7 μ m 2 ), the noise is typically 1/f-like, whereas, in small area devices (≤1 μ m 2 ), the noise stems from the contribution of one or several RTS components. In large area devices, the 1/f noise can easily be interpreted by a classical carrier number fluctuation model. A multi-RTS component scheme has to be employed in the case of small area devices.