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This article reports signal processing and circuit techniques for direct RF signal modulation. A pulse-encoded transition (PET) technique is introduced to reduce undesired harmonic distortion (HD) and adjacent channel leakage ratio (ACLR) generated by the direct RF modulation. To enable PET RF switching, two variations of a high-power, stacked-FET switch modulator, an 8- and 12-device stack, are designed in 45-nm silicon on insulator (SOI) CMOS. The switch design uses a tapering design to significantly improve power handling with minimal impact to switching speed. The modulators have $P_{1\,{\mathrm{ dB}}} $ values between 34 and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1-GHz carrier. The input referred third order intercept point (IIP3) is between 46 and 61 dBm. Additionally, ACLR measurements of up to −50 dBc are demonstrated using the proposed PET technique at 30-dBm output power. To the best of our knowledge, this is record power handling and ACLR for a CMOS switch. [ABSTRACT FROM AUTHOR]

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

An image-selection, two-element transceiver is presented that operates over a large fractional bandwidth (FBW) covering both 71–76 and 81–86 GHz while requiring only 3 GHz of local oscillator (LO) tuning range at the RF mixer. A bidirectional sliding-intermediate frequency (IF) Weaver architecture allows operation in either transmit (TX) or receive (RX) modes. The sliding IF and narrow LO tuning range allow wideband image rejection using only a single-stage polyphase filter. The circuit is implemented in a 90-nm SiGe BiCMOS process and the RF and LO circuitry consume at most 150 and 250 mW, respectively. Measurements show less than ±0.75-dB gain variation over 10 GHz in the TX mode and less than ±1-dB variation over 10-GHz bandwidth in the RX mode. With 16- and 64-quadrature-amplitude modulation (QAM), the error vector magnitude is below −22 and −28.5 dB at the data rates of 12 and 9 Gb/s, respectively. [ABSTRACT FROM AUTHOR]

This paper reports the generation, amplification, and radiation of modulated signals at 45 GHz using a single-chip CMOS power amplifier coupled to a 2\, \times \,2 antenna array. Using digital predistortion, complex constellations were demonstrated for wide modulation bandwidth, which allows high data rates to be transmitted in a spectrally efficient manner. After predistortion, a 98-MS/s 1024-QAM signal with peak-to-average power ratio of 7 dB was demodulated with an error vector magnitude of 1.3%. The measured equivalent isotropically radiated power was 26.2 dBm. The corresponding average RF power produced by the CMOS chip, considering a simulated antenna gain of 12 dB, was 14.2 dBm. [ABSTRACT FROM PUBLISHER]

This paper presents a reconfigurable mixed-signal-processing circuit for high-speed pulse compression radar (PCR). Mixed-signal design techniques incorporate calibration and adaptation to improve the performance of a PCR receiver. Adaptive bandwidth PCR is an important feature for maximizing the dynamic range of a low-power radar system. The baseband signal processor includes a variable gain amplifier, 4-bit digital-to-analog converter, high-speed analog correlator, passive integrator, a 4-bit flash analog-to-digital converter, and a multi-range delay-locked loop. This proposed system is fabricated in 90-nm CMOS and can be configured to work from 50 Mb/s to 1 Gb/s with 2/3/5/7-bit Barker codes. The proposed calibration techniques improve the sidelobe reduction to 15.6 dB at 1 Gb/s. The total power consumption is 42 mW at the peak rate of 1 Gb/s for 15-cm range resolution. [ABSTRACT FROM PUBLISHER]

A low-power, 40-Gb/s optical transceiver front-end is demonstrated in a 45-nm silicon-on-insulator (SOI) CMOS process. Both single-ended and differential optical modulators are demonstrated with floating-body transistors to reach output swings of more than 2\,VPP and 4\,VPP, respectively. A single-ended gain of 7.6 dB is measured over 33 GHz. The optical receiver consists of a transimpedance amplifier (TIA) and post-amplifier with 55 dB\cdot\Omega of transimpedance over 30 GHz. The group-delay variation is \pm 3.9 ps over the 3-dB bandwidth and the average input-referred noise density is 20.5 \pA/\sqrt\Hz. The TIA consumes 9 mW from a 1-V supply for a transimpedance figure of merit of 1875 \Omega/pJ. This represents the lowest power consumption for a transmitter and receiver operating at 40 Gb/s in a CMOS process. [ABSTRACT FROM AUTHOR]

A broadband amplifier is realized with cascaded stagger-tuned stages that are equalized for high bandwidth and low gain ripple. The staggered frequency response is demonstrated to improve the transimpedance limit of active circuits. The staggered response is demonstrated with a Darlington feedback amplifier and a constructive wave amplifier, which achieves low group delay. The broadband amplifier is implemented in a 0.12-\mu\ m SiGe BiCMOS process and achieves a 3-dB bandwidth of 102 GHz. The gain is 10 dB with 1.5-dB gain-ripple and group-delay variation under \pm6 ps over the entire 3-dB bandwidth. The chip occupies an area of 0.29 \ mm^2 including the pads and consumes 73 mW from a 2-V supply. [ABSTRACT FROM PUBLISHER]

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for inter-symbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6 Gb/s and 600 mVpp output swing, a power budget of 3 mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24 mW, a budget of 4 mW/Gb/s. [ABSTRACT FROM AUTHOR]

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase-and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10-12 BER from 30 to 52 ps at 10 Gb/s. [ABSTRACT FROM AUTHOR]

We present a method for predicting data-dependent jitter (DDJ) introduced by a general linear time-invariant LTI system based on the system`s unit step response. We express the exact DDJ of a first-order system and verify the validity of the solution experimentally. We then propose a perturbation technique to generalize the analytical expression for DDJ. We highlight the significance of the unit step response in characterizing DDJ and emphasize that bandwidth is not a complete measure for predicting DDJ. We separate the individual jitter contributions of prior bits and use the result to predict the DDJ of a general LTI system. In particular, we identify a dominant prior bit that signifies the well-known distribution of deterministic jitter, the two impulse functions. We also show a jitter minimization property of high-order LTI systems. We verify our generalized analytical expression of DDJ for several real systems including an integrated CMOS 10-Gb/s trans-impedance amplifier by comparing the theory and measurement results. The theory predicts the jitter with as low as only 7.5% error. [ABSTRACT FROM AUTHOR]