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A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further power reduction. A 0.346 mum2 6T-SRAM bit-cell is used which is optimized for VCCmin, performance, leakage and area. The design operates at high-speed over a wide voltage range, and has a maximum frequency of 3.8 GHz at 1.1 V. The 16 KB Subarray was also used as the building block in on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology.

Embedded SRAM bit count is constantly growing limiting yield in systems-on-chip (SoCs). As technology scales into deep sub-100-nm feature sizes, the increased defect density and process spreads make stability of embedded SRAMs a major concern. This paper introduces a digitally programmable detection technique, which enables detection of SRAM cells with compromised stability [with data retention faults (DRFs) being a subset]. The technique utilizes a set of cells to modify the bitline voltage, which is applied to a cell under test (CUT). The bitline voltage is digitally programmable and can be varied in wide range, modifying the pass/fail threshold of the technique. Programmability of the detection threshold allows tracking process variations and maintaining the optimal tradeoff between test quality and test yield. The measurement results of a test chip presented in the paper demonstrate the effectiveness of the proposed technique

We report a 153Mb SRAM design that is optimized for a 45nm high-K metal-gate technology (Mistry et al., 2007). The design contains fully integrated dynamic forward-body-bias to achieve lower voltage operation while keeping low the area and power overhead. The dynamic sleep design, which was developed at the 65nm node (Zhang et al., 2005), is further enhanced with op-amp-based active-feedback control and on-die programmable reference-voltage generator. The new sleep design reduces the effect of PVT variation, leading to further power reduction. The modular architecture of the design also enables the 16KB-subarray to be used directly as the building block for a 6MB L2 cache in the CoreTM 2 CPU (George, 2007). The design operates over 3.5GHz at 1.1V.

Stability testing of SRAMs has been time consuming. This paper presents a new programmable DFT technique for detection of stability and data retention faults in SRAM cells. The proposed technique offers extended flexibility in setting the weak overwrite test stress, which allows to track process changes without time-consuming post-silicon design iterations. Moreover, it does not introduce extra circuitry in the SRAM array and surpasses the data retention test in test time and detection capability

Reliable cell stability test of modern embedded SRAMs calls for DFT techniques with a flexible detection threshold. We present two programmable cell stability test and debug techniques that use partially discharged floating bit lines to apply a weak overwrite stress to a cell under test. The applied stress can be digitally adjusted to track the process variations or the desired pass/fail threshold. The proposed techniques are demonstrated to exceed the regular data retention test in both the defect coverage and detection range

SRAM cell stability has become an important design and test issue owing to significant process spreads, non-ideal operational conditions, and subtle manufacturing defects in scaled-down geometries. In this article, we carry out an extensive SRAM SNM sensitivity analysis and propose an SRAM cell stability fault model for weak cell detection. This fault model is used to design and verify a proposed digitally programmable design-for-test (DFT) technique targeting the weak cell detection in embedded SRAMs (eSRAM).

Comparative analysis of the conventional 6T and recently proposed loadless 4T CMOS SRAM cells is performed. Based on HSPICE simulations for 0.18-/spl mu/m technology, we compared the stability of the aforementioned cells to temperature and process (V/sub TH/, L/sub eff/, T/sub OX/) variations as well as the cells robustness in low-voltage operation. We found that at V/sub DD/ = 1.2 V the loadless 4T cell has a 20% higher static noise margin (SNM) and 1.5 times lower sensitivity to the V/sub TH/ fluctuations than the 6T cell. On the other hand, the 4T cell has a stronger read current degradation at reduced V/sub DD/. The analytical model for SNM calculation of the loadless 4T CMOS SRAM cell has been developed.

We present some design details and characterization results for a VGA CMOS image sensor designed for high sped inspection applications. The sensor has 16 analog outputs, which can each operate at 50 MHz data rate, and can capture images at 1600 frames per second. The image sensor has exposure control functionality, antiblooming capability and a on-rolling shutter architecture to implement snap-shot image capture mode. The pixel architecture incorporates 5 transistors on a 15.3 micron pitch with 50 percent fill factor.