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A simple and facile stereolithography 3D printing technique was utilized to fabricate piezoelectric photopolymer-based polyvinylidene fluoride (PVDF) blends. Different process variables, such as solvent (N,N-dimethylformamide, DMF) to PVDF ratio and PVDF solution to photopolymer resin (PR) ratio, were engineered to enhance the dispersion of the PVDF into the PR so as to achieve the maximum piezoelectric coupling coefficient. Our results demonstrate that a ratio of 1:10 (PVDF:DMF) and 2 wt%-PVDF/PR was optimal for the best dissolution of the PVDF, 3D printability, and piezoelectric properties. Under these conditions, the blend generated ±0.121 nA under 80 N dynamic loading excitation. We believe that the findings of this work would promote many further studies on the mass production of flexible piezoelectric polymer blends with higher quality finished surface and design flexibility.

Segmentation of the lung field is considered as the first and crucial stage in diagnosis of pulmonary diseases. In clinical practice, computer-aided systems are used to segment the lung region from chest X-ray (CXR) or CT images. The task of segmentation is challenging due to the presence of opacities or consolidation in CXR, which are typically produced by overlaps between the lung region and intense abnormalities caused by pulmonary diseases such as pneumonia, tuberculosis, or COVID-19. Recently, Convolution Neural Networks (CNNs) have been shown promising for segmentation and detection in digital images. In this paper, we propose a two-stage framework based on adapted U-Net architecture to leverage automatic lung segmentation. In the first stage, we extract CXR-patches and train a modified U-Net architecture to generate an initial segmentation of lung field. The second stage is the post-processing step, where we deploy image processing techniques to obtain a clear final segmentation. The performance of the proposed method is evaluated on a set of 138 CXR images obtained from Montgomery County’s Tuberculosis Control Program, producing an average Dice Coefficient (DC) of 94.21%, and an average Intersection-Over-Union (IoU) of 91.37%.

Infection during pregnancy is common and the developing fetal brain is vulnerable to vertical transmission due to immaturity of the fetal immune system. Infection is a major cause of multiple organ abnormalities, including the neuraxis, due to the neurotropism of the infectious agents. This review sets out to give an overview of fetal infection, review the general principles of the nature and timing of the infectious insult with respect to outcomes, review the neuroimaging of infection by ultrasound and magnetic resonance imaging (MRI), and review the various pathogens involved, including the two most common, cytomegalovirus (CMV) and Toxoplasma, and also other common viral and nonviral infections.

The observed initial gain degradation of AlGaAs/GaAs heterojunction bipolar transistors under current stress was investigated. The change in device characteristics is attributed to a dissociation of passivating hydrogen in the base layer during stress. The hydrogen passivation occurs during the implant isolation process. An activation energy of 0.75 eV was measured for the junction temperature dependence of the dissociation process.

We present a single-chip asynchronous multiprocessor optoelectronic bit-sliced arrayed (AMOEBA) crossbar switch. The AMOEBA switch addresses the challenge to produce a large-scale, nonblocking packet switch through dense integration of photonic devices directly onto silicon VLSI circuits. Optoelectronic-VLSI technology is used to integrate the switch fabric, routing controller, packet buffers, line interface circuits, and optoelectronic conversion devices on a single chip. We show how free-space optical interconnects and wavelength-and-space-division-multiplex networking on single-mode fibers can provide switched interconnection between multiple nodes in a distributed computing environment. An optomechanical transceiver package accomplishes the free-space-to-fiber interfacing. We report the implementation and testing of the key components of a 16-channel AMOEBA prototype switch with a potential capacity of 12.8 Gb/s (or 800 Mb/s/channel), and capable of switching 16 million packets per second.

We present the first high-speed optoelectronic very large scale integrated circuit (VLSI) switching chip using III-V optical modulators and detectors flip-chip bonded to silicon CMOS. The circuit, which consists of an array of 16/spl times/1 switching nodes, has 4096 optical detectors and 256 optical modulators and over 140K transistors. All but two of the 4352 multiple-quantum-well diodes generate photocurrent in response to light. Switching nodes have been tested at data rates above 400 Mb/s per channel, the delay variation across the chip is less than /spl plusmn/400 ps, and crosstalk from neighboring nodes is more than 45 dB below the desired signal. This circuit demonstrates the ability of this hybrid device technology to provide large numbers of high-speed optical I/O with complex electrical circuitry.

The reproducible fabrication of narrow (∼1.1 μm wide) mesas for InP-InGaAsP buried heterostructure lasers requires development of high quality stepper lithography and anisotropic dry etching of both the SiO 2 etch/regrowth mask and the underlying semiconductor. Using a contrast enhancement method we demonstrate production of 1.1 μm photoresist lines with excellent uniformity (≤7% variation in width) over 2 in. O wafers. High fidelity pattern transfer to the underlying SiO 2 is achieved using a low pressure (1 mTorr) electron cyclotron resonance (ECR) SF 6 /Ar discharge with low additional dc bias (-75 V) on the sample

We have fabricated vertical-cavity surface-emitting lasers (VCSELs) which, for the first time, effectively combine a shallow ion implanted aperture, for current confinement under a thin highly conducting lateral current injection layer, and an independent index guide for optical beam confinement (I/sup 2/-VCSELs). Both features are possible only because they are made before a top dielectric mirror is deposited and patterned, and are photolithographically defined for improved size reproducibility compared to oxide-confined designs. The devices emit near 980 nm and have optical power outputs of 1 mW at 2.5-mA input. The 12-VCSEL design also easily incorporates coplanar contacts allowing us to operate flip-chip bonded I/sup 2/-VCSEL's on silicon test chips at data rates of nearly 1 Gb/s.

We describe the first integration of vertical-cavity surface-emitting laser arrays with gigabit-per-second CMOS circuits via flip-chip bonding.

A repeater array consisting of clocked-sense-amplifier-based optical receivers driving receivers driving 850-nm optical modulators is used to demultiplex a 2.48-Gb/s optical signal into eight 311-Mb/s optical data streams. The synchronous detection provided by the clocked receivers allows 2.48-Gb/s signals to be demultiplexed despite a repeater bandwidth of roughly 350 MHz. The repeater array contains 16 elements, is fully functional, and is realized in a hybrid MQW/CMOS smart pixel optoelectronic VLSI technology. The CMOS circuits are made in a 0.35-/spl mu/m linewidth process. Total power dissipation for the entire array is 11.5 mW, and 120-fJ optical input signals are used.

In the past, hardware realization of digital signal processing elements have been based upon binary arithmetic concepts. Because of the dependence between digits in binary arithmetic operations, the hardware required to construct arithmetic elements is cumbersome. In the residue number system, arithmetic operations can be performed with complete independence between digits and a corresponding reduction in hardware complexity. In fact, using current technology, arithmetic operations can be carried out using arrays of look-up tables placed in high density ROMs. This paper discusses the application of the residue number system to realizing digital signal processing elements using such arrays and advantages and disadvantages over conventional realizations are discussed. Examples are given of recursive filter and FFT butterfly element realization.

This paper considers an implementation of the FFT based upon the residue number system. This system offers the advantages of using integer based arithmetic operations and a simple hardware realization involving table look-up arrays. The proposed architecture is such that rapid evolutionary changes in read-only-memory technology can be easily incorporated into the hardware realization. In this paper, a generalized expression for predicting RMS relative error that includes A/D quantization, integer normalization and scaling rounding considerations, has been derived. This analysis leads to the optimal choice of several parameters, which are related to error minimization and simplification of the hardware realization. The generalized expression derived with respect to the FFT can also be used to predict errors in high-speed convolution filters.

We introduce the concept of synchronous smart-pixel optical receivers, and present the first use of a clocked-sense amplifier as a smart-pixel optical receiver. Such a receiver uses the controlled application of positive feedback to obtain low-power compact digital amplification. We describe the design and simulation of two types of optical receivers based on a clamped bit-line sense amplifier (CBLSA), and a conventional sense amplifier (CSA). Both of these circuits have been realized in 0.8 micron-linewidth foundry CMOS with hybrid-bonded GaAs-AlGaAs MQW detectors and modulators attached to the circuit. Operation in excess of 750 Mb/s is demonstrated, within a layout area of 44 /spl mu/m/spl times/22 /spl mu/m, with a bias-dependent estimated power dissipation of 1 to 2 mW. Operation with one or two input beams is possible, with approximate minimum detected photocurrent levels at 320 Mb/s of 8 /spl mu/A (/spl sim/100 fJ) for single-beam operation and 2.5 /spl mu/A/beam (/spl sim/30 fJ/beam) for two-beam operation, all in the CBLSA-based circuit.

We have made two-beam smart-pixel optical receivers using a hybrid attachment of GaAs-AlGaAs multiple quantum-well (MQW) pin devices to foundry-fabricated 0.8-/spl mu/m linewidth CMOS circuits. Results from a repeater in which receiver output is coupled to a transmitter circuit driving a differential pair of MQW modulators are reported. When tested with high-contrast, directly-modulated laser diodes, an optical energy of 26 fJ (-21.5 dBm) in each beam is required to obtain a bit error rate of 1/spl times/10/sup -9/ at 622 Mb/s, and operation at this error rate is observed to 1 Gb/s. The described receiver (one of several we have made) has three amplification stages, with the first being of the transimpedance type. The reported receiver fits easily within a 45/spl times/25 /spl mu/m area, and the entire repeater circuit draws about 2 mA from a 5-V power supply, with the transmitter accounting for about 20 percent of the total.

We describe 8/spl times/8 arrays of smart pixels, designed and fabricated using MQW modulators and detectors flip-chip-solder-bonded to silicon CMOS circuits. The individual circuits implement 2 input, 1 output embedded control switching nodes. Four arrays from two different designs were fabricated and tested. For the array with the highest yield, 60 of 64 nodes functioned correctly at low speeds and were tested up to 250 Mb/s without re-adjusting individual bias voltages with the maximum speed of an individual node of 375 Mb/s. For the second-generation array, the center 4/spl times/8 section of the array was tested at data rates beyond 700 Mb/s with individual nodes having short term bit error rates below 10-/sup 11/.

We accomplish the integration of GaAs-AlGaAs multiple quantum well modulators directly on top of active silicon CMOS circuits. This enables optoelectronic VLSI circuits to be achieved and also allows the design and optimization of the CMOS circuits to proceed independently of the placement and the bonding of surface-normal optical modulators to the circuit. Using this technique, we demonstrate operation of a 0.8 micron CMOS transimpedance receiver-transmitter circuit at 375 Mb/s. >

We demonstrate integration of GaAs-AlGaAs multiple quantum well modulators to silicon CMOS circuitry via flip-chip solder-bonding followed by substrate removal. We obtain 95% device yield for 32/spl times/32 arrays of devices with 15 micron solder pads. We show operation of a simple circuit composed of a modulator and a CMOS transistor. >

The interactions between the CAD tools that are used to configure the routing resources of a field-programmable gate array (FPGA) and the design of the routing architecture itself are examined. Such an understanding is used to determine where to reduce the number of routing switches in the FPGA while maintaining routability. Experiments are used to study a switch block that was previously thought to have unacceptably low flexibility. It is shown that the performance of this switch block can be improved by adapting the global router to require less flexibility in the architecture, and by careful placement of physical pins on the logic blocks. It is demonstrated that the fewest routing switches are required when each logical pin appears on only one side of the logic cell rather than two or more. >

For several years we have been developing an optoelectronic/VLSI (OE/VLSI) chip technology based on flipchip bonding of GaAs optoelectronic chips onto CMOS silicon followed by substrate removal. Our optoelectronic devices are currently surface normal modulators, which also function as the input detectors. Finally, we have demonstrated an OE/VLSI switching chip with >140000 CMOS gates and 4352 modulators that operated with a clock rate of 400 Mbit/sec.

A two-beam optical repeater circuit operates to 1 Gb/s, consumes 10 mW, occupies about 1100 /spl mu/m/sup 2/, and is realized with a technology capable of providing thousands of optical inputs and outputs to foundry-grade VLSI silicon CMOS circuitry. The technology provides this capability by attaching GaAs/AlGaAs multiple-quantum-well (MQW) modulators and detectors to VLSI CMOS with flip-chip solder bonding. The main unique features are summarized.

We present a novel application of opto-electronic/VLSI technology to the AMOEBA switch: an Asynchronous Multiprocessor Opto-Electronic Bit-sliced Array switch. The AMOEBA switch is intended to function as a high-performance single-chip central switch on a data network serving multiple processors or computers. The purpose of the opto-electronic/VLSI chip is to provide byte-wide, switched optical interconnection at the processor clock rate.

We present AMOEBA: a single-chip asynchronous multiprocessor optoelectronic bit-sliced arrayed crossbar switch intended to provide switched interconnection between multiple processors in a distributed computing environment. AMOEBA relies on optoelectronic-VLSI integration, free-space optical interconnects, and wavelength-and-space-division multiplexed networking on single-mode fiber. We report the implementation and testing of a first generation, 16-channel prototype of the switch and a compact opto-mechanical transceiver package that accomplishes the free-space-to-fiber interfacing.

We present the first operation of an OE/VLSI compatible single-beam receiver-transmitter pair operating to 1 Gb/s. The circuits were realized in 0.35 micron CMOS and hybridized via a flip-chip bonding technique to an array of 850 nm MQW modulator/detectors.

Two-dimensional arrays of optical receivers become interesting as we try to pack more information into smaller spaces, as might be encountered in optical interconnect applications. We have realized a two-dimensional array of such receivers, and coupled their outputs off-chip both electrically and optically, by using a previously described hybrid process whereby multiple-quantum-well modulator/detectors are attached to CMOS circuits. We have demonstrated 622 Mb/s operation of receivers in the array, and found that roughly a 2.5 dB penalty is incurred for operation of nearly the whole array as compared to an isolated element at 311 Mb/s.

The efficacy of many system-designs based on free-space optical interconnects and smart-pixels, depends on the availability of a flexible, high-density, silicon-compatible, optoelectronic technology platform. To this end, we demonstrate the hybrid 3D integration of GaAs-AlGaAs 850nm multiple quantum well (MQW) detectors and modulators directly over active 0.8 /spl mu/m silicon CMOS circuits. To test this technique, a self electro-optic effect device (SEED) input-light detector was flip-chip bonded over a transimpedance receiver circuit, whose output was fed to a simple transmitter circuit and then to another SEED device that served as an output-light modulator.

We describe the parallel optical test of a photonic first-in-first-out (PFIFO) buffer memory based on flip-chip CMOS/SEED optoelectronic technology. The PFIFO detects pages of 4 by 8 binary bits, stores them in a 32 bit deep buffer memory, and transmits them in a 16 by 2 output modulator array. All 32 I/O and memory channels functioned, with an average input power of 40 microwatts and a minimum output contrast ratio of 2:1.

This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGaAs multiple-quantum-well modulators and detectors. The chip has been designed based on the HyperPlane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given.

Two techniques for fabricating through-wafer via holes in 2-4 mil thick GaAs substrates were examined. In the first, Ni or thick photoresist masks were used for patterning 30 μm diameter vias by ECR-rf dry etching using low pressure (10-20 mTorr), low bias (– 150V) BCI3/C12 discharges. Microwave enhancement of these discharges produced faster etch rates but a greater degree of isotropic material removal at a given pressure. Reducing the process pressure produces extremely anisotropic features with high aspect ratio. The BC13-to-C12 ratio must be kept to ≥5:1 to maintain the anisotropy. A novel laser drilling technique was also examined - in this case a Q-switched beam with high energy density was used to ablate material in each pass of the beam, producing a via in approximately 40 passes. This is a maskless procedure capable of producing any desired via hole pattern, but currently there is no selectivity for ablating GaAs over a front-side metal film.

Narrow (1 μm), deep (3.5 μm) laser mesas have been formed on 2”φ InP wafers using stepper lithography and dry etching techniques for both dielectric and semiconductor patterning. Contrast enhancement techniques produce excellent edge acuity and vertical sidewalls on the initial photoresist lines. Pattern transfer to the underlying SiO2 regrowth mask is achieved by ECR SF6/Ar dry etching at 1 mTorr and –100V, conditions which also retain the verticality of the mesa. The semiconductor is etched using an ECR Cl2/CH4/H2/Ar discharge at 0.3 mTorr and –80V, with the sample held at ∼ 150°C. The etch rate under these conditions is ∼1 μm/min, with a selectivity of ≥10:1 for the semiconductor over the dielectric mask. The smooth etched surface and low degree of damage make this process ideal for epitaxial regrowth. The uniformity of each process step is also acceptable (≤7%). Comparison of the elevated temperature Cl2/CH4/H2/Ar mixture with the more conventional room temperature CH4/H2 plasma chemistry will be given.

In this paper we will describe applications of a low temperature SiNx for the novel fabrication of lasers and FET's. Sidewall roughness which appears on dry etched semiconductor laser mesas is a common problem in laser fabrication. Protecting the sidewall with a low temperature PECVD SiNx can greatly reduce laser mesa roughness that occurs during dry etching of the mesa. Another application uses low temperature SiNx to extend the resolution of standard optical replication. Submicron gate fingers in field effect transistors can be fabricated by using this low-temperature SiNx deposition. By depositing SiNx on the photoresist gate pattern and etching back the SiNx leaving a sidewall, this will reduce the opening of gate features. Submicron gate length MESFETs have been demonstrated with this technique which showed comparable results to conventional submicron MESFETs fabricated with E-beam direct writing.

We report a highly reliable, sputtered WGe emitter contact for npn heterojunction bipolartransistors. A specific contact resistance of 7.5 × 10−7 Ω-cm2 and a transfer resistance of 4.0 × 10−2 Ωmm were obtained after 380°C, 1 min alloy. The contact was patterned by SF6 dry etching at low bias using a Au mask. This novel contact has comparable resistance to conventional AuGe-based metallization while having superior thermal stability. We have studied the dependence of contact properties on the post-deposition annealing conditions by transfer length method of electrical characterization and Auger analysis, and will also report long-term reliability results in comparison to AuGe-based metallization.

3569 Background: EPC2407 is a 4-aryl-chromene single isomer microtubulin inhibitor with vascular disrupting and apoptotic activity at nanomolar concentrations. In an earlier phase I study dosing by 1 hr infusions daily x3 on a 21 day cycle, DLT at 21 mg/m2 was pain at tumor sites and vasoconstriction with increases of BP and QTc. MTD was 13 mg/m2 over 1 hr (ASCO 2008, Abst 2531). All drug-related toxicities resolved within an hour of stopping the infusion. Prolonged infusion of EPC2407 to extend exposure of tumor vasculature was designed with administration of EPC2407 over 4 hrs for 3 consecutive days of a 21 day cycle. Eleven patients have received this schedule and their cancers included leiomyosarcoma, colo-rectal, ovary, hepatocellular (2), NSCLC, pancreas, carcinoid, hemangiopericytoma, larynx and small bowel. Results: Doses escalated from 13 to 30 mg/m2 over 4 hours, with MTD determined to be 24 mg/m2. DLTs at 30 mg/m2 were similar to those seen in the 1 hr infusion, with pain at tumor sites in 1 participant and asymptomatic ST depression in a second. Other toxicities were also similar and included transient hypertension. QTc increases were not significant and no new toxicities were encountered. T1/2 with 4 hr infusion was ∼2hr, also seen with 1 hr infusion. AUC and Cmax values were similar to that predicted from the 1 hr data except AUC at 13 mg/m2 was lower than expected. DCE-MRI was done at baseline and after infusion on day 3, cycle 1. Analysis to date of DCE-MRI data of 4 patients showed a median decrease of 40% in both tumor permeability (Ktrans) and tumor perfusion volume (Vp). The two patients with hepatocellular carcinoma had notable stable disease and clear clinical benefit. Both patients received 18 mg/m2 dose, with one receiving 7 cycles over 5 months, and the other still on study (cycle 6) with stable disease for at least 4 cycles. Conclusions: EPC2407 shows clinical promise, with infusion-associated toxicities characteristic of the VDA drug class but without sustained or cumulative toxicity. Studies combining EPC2407 with conventional cytotoxic/cytostatic regimens are being designed. [Table: see text]

2531 Background: EPC2407 is a 4-aryl-chromene single isomer microtubulin inhibitor which in preclinical models showed antitumor effects due both to direct tumor apoptosis and to tumor vascular endo...

14043 Background: Compounds which bind to colchicine-like sites of microtubules have contributed greatly to the armamentarium of cancer therapies. But new modes of administration of taxanes and potent new vascular disruption agent molecules such as combretastatin continue to challenge drug development for ways to improve the therapeutic index in this important class. EPC2407 is a novel 4-aryl chromene of nM anti-tumor potency; it is crossing the translational bridge based on an array of preclinical anti-tumor pharmacology and supported by multiple toxicology trials which included drug exposure data. Methods: Vascular disrupting agents demand careful preclinical workup. What we have done is summarized in the table below. This data is from cellular metabolic, cell proliferation, vascular endothelial, in vivo tumor, and animal toxicokinetic and safety studies. Results: Please see table below of the preclinical experiments. Conclusions: A Phase I clinical trial has been designed and initiated to replicate the safety margin shown by the analysis of preclinical drug exposure data. The critical safety issue for human dosing was the dose exposure which might produce the well known ECG abnormality of delayed repolarization or prolonged QTc. A dose related QTc effect was demonstrated in cynomolgus monkeys after a 2 min infusion which achieved acute plasma exposures higher than 3836 nM. These effects were dose related and persisted only through 4 short half-lives of the parent compound. Initial human analysis fails to show any prolongation of the QTc. [JW1] [JW1]THE END HERE, all else was draft. [Table: see text] No significant financial relationships to disclose.

Loaded and unloaded ring-oscillator circuits with an electrical and surface-normal 850 nm optical readout are fabricated using a hybrid 0.8 /spl mu/m silicon-CMOS/GaAs-AlGaAs MQW process. Measurements of the oscillation frequency of these circuits show total capacitance associated with the flip-chip-bonded optical MQW modulators as low as 52 fF.

We describe a smart-pixel circuit that permits the use of a GaAs/AlGaAs multiple quantum well diode to be used both as a detector for data input and a modulator for data output. The module provides the ability to double the number of inputs or outputs to the array and is well suited to cascaded optoelectronic system architectures that require bidirectional communition.

We present a 2-kbit, 50-Mpage/s, photonic first-in, first-out page buffer based on gallium arsenide/aluminium-gallium arsenide multiple-quantum-well diodes that are flip-chip bonded to submicrometer silicon complementary-metal-oxide-semiconductor circuits. This photonic chip provides nonvolatile storage (buffering), asynchronous-to-synchronous conversion, bandwidth smoothing, tolerance to jitter or skew, spatial format conversion, wavelength conversion, and independent flow control for the input and the output channels. It serves as an interface chip for parallel-accessed optical bit-plane data. It represents the first smart-pixel array that accomplishes the vertical integration of multiple-quantum-well modulators and detectors directly over active silicon VLSI circuits and provides over 340 transistors per optical input-output. Results from high-speed single-channel testing and real-time array operation of the photonic page buffer are reported.

A single-ended, asynchronous, transimpedance receiver-transmitter circuit with 5 mW power dissipation, is implemented in 0.8 /spl mu/m silicon CMOS. A hybrid flip-chip bonding technique is used to attach GaAs-AlGaAs MQW detectors and modulators to the circuit. Operation of the circuit at a sensitivity of -19.4 dBm (41 fJ) and a bit error rate

Transmission electron microscopy (TEM) and focused ion beam sputtering have been used for investigations of microstructure and defect formation in AlGaAs/GaAs heterojunction bipolar transistors. The use of focused ion beam sputtering to prepare nearly ideal thin membranes within the active region of transistors for cross‐sectional electron microscopy is described. Results are obtained from as‐fabricated devices, devices annealed at temperatures of 400 °C, and devices for which ‘‘aging’’ is accelerated by operating at high‐bias conditions and heating in combination. We find that electrical operation leads to significant microstructural changes which are distinct from those observed in devices which are annealed. TEM images of the metal/semiconductor contact reveal ‘‘metal spiking’’ and facetted structures associated with alloy interpenetration. Characterization of the semiconductor heterojunctions reveal precipitates at the emitter‐base junction. Mechanisms for the formation of these defects under high‐bia...

Self‐aligned processing of high efficiency power heterojunction bipolar transistors (HBTs) using implant isolation, selective wet and dry etching for mesa formation, plasma‐enhanced chemical vapor deposited SiNx for sidewall spacers and through‐wafer via connections is reported. GaAs/AlGaAs and GaAs/InGaP HBTs grown by metalorganic molecular beam epitaxy utilizing carbon for high, well‐confined base doping produced power‐added efficiencies of 63%, power gain of 10 dB and output power of 1.7 W at 4 GHz for twelve 2×15 μm2 double‐emitter finger devices (GaAs/AlGaAs) and 57% power‐added efficiency, power gain of 11.3 dB and output power of 0.6 W at 4 GHz (GaAs/InGaP), respectively.

The fabrication of through‐wafer via holes in GaAs substrates by plasma etching and laser drilling is reported. Using a low pressure (15–20 mTorr), low dc bias (−150 V) Cl2/BCl3 discharge with Cl2‐to‐BCl3 ratios ≤0.2, we are able to produce narrow (≤30 μm) via holes. This enables the use of a higher density of vias in closer proximity to the active GaAs power devices than can be achieved with normal diameter (100–150 μm) holes. Microwave enhancement of the plasma density using an electron cyclotron resonance source increases the GaAs vertical and lateral etch rates and requires use of low Cl2‐to‐BCl3 ratios in order to retain the anisotropic nature of the vias. Multiple pass (∼100 per hole) drilling of vias with a Q‐switched Nd‐YAG frequency doubled (532 nm), 30 mW laser has also successfully produced through‐wafer connections. This provides a maskless, versatile method for producting vias customized for a particular wafer, but is less developed than plasma etching.

A new technique is presented for calculating dielectric loss in microstrip lines. Numerical results for several different substrates are included. These are compared with other available results and experimental data.

High performance selfaligned InGaP/GaAs HBTs are reported. SIMS and TEM analysis indicate the presence of clean and abrupt InGaP/GaAs interfaces which are reflected in excellent DC performance. Using a base layer with a sheet resistance of 135 Ω/□, a DC current gain of 25 was obtained for 2×5 μm2 devices. Both cutoff frequency ft and maximum frequency of oscillation fmax are measured above 70 GHz. These are the highest values yet reported for HBTs containing InGaP.

An "electrically transparent fluid barrier" (ETFB) is proposed as a means of separating fluids of different conductivity for use in two- or three-dimensional field mapping experiments. The concept is demonstrated in the context of a conducting analog to the problem of the microstrip transmission line.