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International audience; Ion implantation is a suitable and promising solution for the massive industrialization of boron doping, which is a crucial process step for most next-generation solar cells based on crystalline silicon (c-Si). However, the use of ion implantation for boron doping is limited by the high temperature (in the 1050°C range) of the subsequent activation anneal, which is essential to dissolve the boron clusters and reach a high-emitter quality. In this work, we propose the use of plasma-immersion ion implantation (PIII) from B$_2$ H$_6$ gas precursor instead of the standard beamline ion implantation (BLII) technique to decrease this temperature down to 950°C. PIII and BLII boron emitters were compared with annealing temperatures ranging from 950°C to 1050°C. Contrary to BLII, no degradation of the emitter quality was observed with PIII implants annealed at 950°C along with a full activation of the dopants in the emitter. At 1000°C, emitter saturation current densities (J$_{0e}$) below 21 fA/cm$^2$ were obtained using the PIII technique regardless of the tested implanta-tion doses for sheet resistances between 110 and 160 $\Omega$/sq. After metallization steps, the metal/emitter contact resistances were assessed, indicating that these emitters were compatible with a conventional metallization by screen-printing/firing. The PIII boron emitters' performances were further tested with their integration in n-type passivated emitter rear totally diffused (PERT) solar cells fully doped by PIII. Promising results already show a conversion efficiency of 20.8% using a lower annealing temperature than with BLII and a reduced production cost. KEYWORDS annealing temperature, B$_2$ H$_6$ plasma, boron doping, n-type PERT solar cells, plasma-immersion ion implantation, silicon solar cells We report a new way to activate implanted boron emitter at low temperature that is the use of plasma-immersion ion implantation (PIII) from B$_2$H$_6$ plasma. A full activation of the emitter at 950°C was observed even for a high implantation dose corresponding to a sheet resistance of 112 $\Omega$/sq. Promising performances while being integrated in n-PERT solar cells fully doped by PIII were demonstrated with efficiency of 20.8% % using a lower annealing temperature than with BLII and a reduced production cost.

The use of plasma immersion ion implantation (PIII) is a relevant approach for the development of advanced solar cells technologies at lower cost (€/W p ). In this paper, we report on the development of homogeneous boron (B) doping of n-type crystalline silicon (cSi) substrate by the PIII technique. Using diborane (B 2 H 6 ) as gas precursor, various doping profiles were identified fitting the requirements for boron-doped emitters in n-type PERT solar cells. Particularly, saturation current density (J 0e ) of 50 fA/cm 2 were achieved on symmetrical samples for a 94 Ω/sg textured B-emitter passivated with SiO 2 /SiN stack. Bifacial n-type Passivated Emitter Rear Totally-diffused (n-PERT) solar cells were fabricated using the PIII technology and conversion efficiencies up to 19.8% on 239 cm 2 Cz-Si wafers were obtained. As a consequence, these results indicate that PIII can compete with beamline technology but will have lower running cost. It is therefore a promising technology to create high efficiency cSi solar cells.

Since several years, the use of Beamline ion implantation has been proven to allow optimization of doping profiles needed for the fabrication of crystalline silicon (c-Si) solar cells while simplifying the process flow. Nevertheless the cost and complexity of such tools, associated to the difficulty to keep a small thermal budget to make high quality Boron doping for N-type cells, has slowed down the industrial introduction of ion implantation in high volume solar cell fabrication fabs.Thanks to an implant time independent to the implanted surface, and a simple tool architecture, Plasma Immersion Ion Implantation (PIII) offers an economically efficient alternative to Beamline Ion Implantation.In this paper, after having presented PULSION®-Solar, the IBS PIII tool dedicated to solar cell fabrication, we will demonstrate state of the art characteristics on different cells type either on c-Si but also on multi crystal Si where the beneficial gettering capability allowed by POCl 3 is also obtained using PIII phosphorus implantation. We will also show how the PIII doping process, thanks to its unique energy distribution, can even be more efficient than beam line, especially for boron doping, allowing lower thermal budget and co-anneal with phosphorus, simplifying even more the process flow for n-type PERT solar cells.

Spectral sensitivity measurements versus temperature have been carried out on irradiated SiC p+n photodiodes, fabricated using two different doping processes: Aluminium standard implantation and Boron plasma immersion ion implantation. The spectral sensitivity of Al doped photodiodes increase for incident wavelength higher than 270 nm, and are very stable below. Boron doped irradiated photodiodes show a general increase of the photoresponse for all wavelengths. In both cases, an hysteresis effect is observable when with the temperature. Results are presented and discussed.

International audience; Production costs and energy efficiency are the main priorities for the photovoltaic (PV) industry (COP21 conclusions). To lower costs and increase efficiency, we are proposing to reduce the number of processing steps involved in the manufacture of N-type Passivated Rear Totally Diffused (PERT) silicon solar cells. Replacing the conventional thermal diffusion doping steps by ion implantation followed by thermal annealing allows reducing the number of steps from 7 to 3 while maintaining similar efficiency. This alternative approach was investigated in the present work. Beamline and plasma immersion ion implantation (BLII and PIII) methods were used to insert n-(phosphorus) and p-type (boron) dopants into the Si substrate. With higher throughput and lower costs, PIII is a better candidate for the photovoltaic industry, compared to BL. However, the optimization of the plasma conditions is demanding and more complex than the beamline approach. Subsequent annealing was performed on selected samples to activate the dopants on both sides of the solar cell. Two annealing methods were investigated soak and spike thermal annealing. Best performing solar cells, showing a PV efficiency of about 20%, was obtained using spike annealing with adapted ion implantation conditions.

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible

This paper presents a study of 4H-SiC UV photodetectors based on p+n thin junctions. Two kinds of p+ layers have been implemented, aiming at studying the influence of the junction elaborated by the ion implantation process (and the subsequent annealing) on the device characteristics. Aluminum and Boron dopants have been introduced by beam line and by plasma ion implantation, respectively. Dark currents are lower with Al-implanted diodes (2 pA/cm2 @ - 5 V). Accordingly to simulation results concerning the influence of the junction thickness and doping, plasma B-implanted diodes give rise to the best sensitivity values (1.5x10-1 A/W @ 330 nm).

In this paper, we communicate on the design, fabrication, and testing of optical modulators for Silicon-based photonic integrated circuits (Si-PICs) in the O-band (1.31 μm), targeting the 100GBASE-LR4 norm (4 wavelengths at 25 Gbit/s). The modulators have been conceived to be later coupled with hybrid-III-V/Si lasers as well as echelle grating multiplexer, to create a hetero-integrated optical transmitter on a silicon-on-insulator (SOI) platform. The devices are based on a Mach-Zehnder Interferometer (MZI) architecture, where a p-n junction is implanted to provide optical modulation through carrier depletion. A detailed study focusing on the best doping scheme for the junction, aimed at optimizing the overall transmitter performance and power-efficiency is presented. In detail, the trade-off between low optical losses and high modulation efficiency is tackled, with a targeted CMOS-compatible voltage drive of 2.5 V. Process simulations of the junction are realized for the doping profile optimization. Modulators of different lengths are also investigated to study the compromise between extinction ratio, insertion losses and bandwidth. Furthermore, coplanar-strip (SGS) travelling-wave electrodes are designed to maximize the bandwidth, to reach the targeted bit rate of 25 Gbit/s. Measurements show modulation efficiencies up to 19 °/mm (or 2.4 V.cm) for a 2.5 V input voltage, with doping-related losses below 1 dB/mm, in line with theoretical estimates, and well-suited to enhance the Si-PIC transmission and power-efficiency. Finally, an electro-optical (EO) bandwidth at 1.25 V bias is measured above 28 GHz.

7th International Workshop on Plasma-Based Ion Implantation, San Antonio, TX, SEP 17-19, 2003; International audience; The efficiency of plasma immersion ion implantation (PIII) is no more to prove for the realization of ultra shallow junctions (USJ) in semiconductor applications. Interest for the fabrication of submicrometer CMOS devices is well known, but the ability of PIII to implant quickly high doses at very low energy and low price makes it a good candidate for the Fabrication of solar cells. In this paper, we present results obtained by a semi-industrial prototype of PIII (PULSION(R)) designed by the French company IBS. First, metallic contamination, homogeneity, reproducibility, and SIMS profiles of ultra shallow junctions made by PULSION(R) BF3 implantation on 200-mm silicon wafers are presented. Results are compared with BF2+ implantations made on an AXCELIS NV-8200P beam line implanter and demonstrate the compatibility with semiconductor requirements. Then, results on solar cells with BF3 shallow junctions made by PIII are presented. The simulated and measured internal quality factor (IQE) with an improved behavior in blue wavelengths demonstrates the interest of PIII for this applications field. (C) 2004 Elsevier B.V. All rights reserved.

This paper deals with the thermal and morphological stabilization of nickel-based silicides and germanides using tungsten and fluorine implantation for 3D monolithic CMOS applications. The incorporation of few % of W and/or F at various steps of the salicide process can successfully address two major issues: the morphological degradation (agglomeration) of NiSi and NiGe layers on one side and the Ge diffusion outside the active regions on the other side. The paper highlights cumulative effects of Pt alloying together with the incorporation of F and W for delaying at higher temperatures the agglomeration phenomenon. It also deals with the strong reduction of Ge diffusion using W and F implantation. Implantation conditions (dose, energy) and schemes (implantations prior metal deposition, after metal deposition, into the silicide) are discussed.

4H-SiC p+n photodiodes based on ultrathin-junctions have been fabricated with distinct processes for the p+-region creation: either with Aluminium conventional ion implantation, or with Boron Plasma Ion Immersion Implantation. Spectral sensitivity measurements were performed at several temperatures from room temperature up to 340°C, with incident wavelengths ranging from 200 to 400 nm. Both responses are characterized by a stability between 200 and 270 nm, and a important increase with temperature between 270 and 380 nm. This fact has to be related to the two different kinds of optical absorption phenomena in SiC with respect to the wavelength, which are direct and indirect (phonon assisted) transitions. When decreasing the temperature, we noticed a hysteresis effect, which could be due to charge trapping by temperature activated defects. After strong proton and electron irradiations, the diodes showed a stability of the response below 270 nm, making them suitable for use in harsh environments. Simulation was performed at room temperature, with a good correlation between simulated and experimental room temperature curves.

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible.

International audience; This paper deals with the study of the photoresponse properties of 4H-SiC UV-photodetector devices based on a thin junction following their testing in darkness and under UV light over the 200 to 400 nm range. An increase of the carrier harvesting for low implanted layer thickness was shown by simulation. Thus, an implantation at low energy (27 keV) was carried out on our samples. Because of the thin junction architecture, the photocurrent at 280 nm was found to be four orders of magnitude larger than the dark current. A spectral responsivity of our photodetectors shows a peak at 280 nm with a value of 0.03 A/W.

Here, we present and discuss the electrical characteristics of fully depleted MOSFET transistors of planar and tridimensional architecture, doped by Plasma Immersion Ion Implantation (PIII) or Beam Line Ion Implantation (BLII). Both techniques delivered similar and satisfactory results in considering the planar architecture. For tri-dimensional Tri-Gate transistors, the results obtained with PIII are superior.

In this paper, we deal with the study of Ultra Violet (UV) photodetector device based on SiC material undergoing a p-i-n structure process. Current density-voltage (J-V) measurements in reverse and forward bias, are performed on the UV photodetector device. Due to a very thin p+-type doping layer, a high reactivation annealing and the metallic contact deposit, experimental measurements point out Junction Barrier Schottky (JBS) device behaviour in spite of the p-i-n structure device process. To understand this involuntary phenomenon, these experimental characteristics are accompanied with an experimental study by the SIMS analysis.

For continued scaling of future CMOS devices (sub-32 nm), heavily-doped ultra-shallow junctions are required. Plasma doping (PD) with PULSION® offers the attractive capability of high dose and low energy doping with short production times [1, 2]. All of these aspects make plasma doping a good candidate for the next technology steps driven by the roadmap. In this paper we discuss the integration of plasma doping into a Fully Depleted SOI CMOS process flow (sub-10 nm top Si layer). The compatibility of PD with patterns (charging effects) has been studied as well as the Selective Epitaxial Growth (SEG) performed after the source/drain extension implantations to thicken these regions prior to silicidation [3].

Thanks to the European Project SEA‐NET, an industrial version of the IBS Plasma Ion Implantation tool has been installed in LETI for the fabrication of Ultra‐Shallow Junction for 45 & 32 nm CMOS on 200 and 300 mm wafers. In this study, we present first doping results on 300 mm wafers using BF3 plasma. Annealing after PULSION implantation is perfomed by the ASM furnace LEVITOR. This tool, which works on conduction heating is emissivity independent for temperature control and allows reaching high ramp up and ramp down speeds (up to 900 °C/s). Main characteristics of as implanted wafers are presented (metal contamination 2E10/cm2, SIMS depth profiles down to 5 nm). Then the effect of convection gas in the annealing process on sheet resistance, junction depth and uniformity is presented.

This work demonstrates the efficiency of a Germanium and Carbon co-implantation that suppresses the Boron Transient Enhanced Diffusion, enhances Boron activation and enables large improvement of Short Channel Effects in PMOS devices while maintaining drive current performances. We present here 65/45nm node devices on conventional bulk substrates featuring Germanium and Carbon engineered shallow junctions that enable to reduce the Drain Induced Barrier Lowering compared to devices implanted only with Boron. This improvement is attributed to the suppression of Boron channelling with Ge pre-amorphization (PAI), and to the reduction of Boron TED due to the trapping of interstitial defects by Carbon with Germanium PAI.