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Static Random Access Memory (SRAM) is a core technology for building computing hardware, including cache memory, register files and field programmable gate array devices. Hence, SRAM reliability is essential to guarantee dependable computing. While significant research has been conducted to develop automated test algorithms for detecting manufacture-induced SRAM faults, they cannot ensure detection of faults deliberately implemented in the SRAM array by untrusted parties in the integrated circuit development flow. Indeed, such hardware Trojan attacks represent an emerging security threat. While a growing body of research addresses Trojan designs in logic circuits, little research has explored hardware Trojan attacks in embedded memory arrays [20]. In this article, we propose a new class of hardware Trojans targeting embedded SRAM arrays. The Trojans are designed to evade industry standard post-manufacturing tests while enabling attacks targeting various system hardware components during deployment. Transistor-level simulation results demonstrate minimal impact on SRAM power, performance, and stability while Trojans are not activated. We also prove the feasibility of Trojan insertion in foundries by showing the proposed layouts that preserve the SRAM cell footprint and incur zero silicon area overhead. Finally, we elaborate on several system-level attacks that can leverage these Trojans to compromise security and privacy.

The technique of current splitting is presented as part of an integrated circuit development for an X-ray imager. This method enables integration of charge signals of unprecedented magnitude in small pixels, achieving a dynamic range of 105. Results from two front end prototypes are given and a final optimized design is proposed.

Spoof surface plasmon polaritons (SSPP) is an electromagnetic wave that can be tightly confined near the interface between metal and medium; it can solve the crosstalk problem caused by the strong mutual coupling in highly integrated circuits[1]. Using this feature is expected to break through the bottleneck of integrated circuit development. In this paper, we construct a spoof surface plasmon polaritons transmission line byembedding hybrid ELC resonantors within the grooves of the periodic unit to achieve the tunablefiltering effect. For dynamic regulation, we combine vanadium dioxide with the resonant unit to implement the phase change characteristics of vanadium dioxide for tunable filtering bandgap.

RTL verification is still one the most challenging activities in digital system development as it is still the bottleneck in the time-to-market for an integrated circuit development cycle. Thus reducing verification time is one of the most important targets. In this paper, a tool is developed to generate automatic tests from SystemVerilog assertions or SystemVerilog Coverage. The proposed tool is tested using different memory modules starting from single port RAM through Multiple ports RAM, FIFO and the DDRx families. The performance, regarding the runtime, has been compared with the handcrafted test case generation process. Moreover, the performance has been compared with other automatic test generation tools. Results shows the effectiveness of the proposed design. The proposed tool excelled in terms of its run-time, complexity, and coverage percentage.

This paper presents an empirically grounded model, which links organizational learning to pattern-specific fixed costs in integrated device manufacturing. The approach described in this paper helps fab managers make fundamental strategic decisions concerning product design and product mix by engaging in scenario planning. Four critical aspects of managing pattern-specific fixed cost are analyzed in detail—sensitivity to time, design cost, and production volume; platform designs; process postponement solutions; and design penalties. The model suggests that designers and fabrication facilities must collaborate extensively on the design and realizations of product platforms for state-of-the-art integrated circuit products to remain economically viable.

The continuous development of electronics has been characterized by Moore's law. Although the current CMOS integrated circuit development is driven by a lot of innovations, there are still some limits determined by unavoidable physical effects. There are many new ideas for building atomic or molecular scale devices for the information technology, but there is still a gap between CMOS technology and novel devices. The recently proposed thermal-electronic device (phonsistor) and the CMOS compatible thermal-electronic logic circuit (TELC) may help to fill this gap. The operation is based on the semiconductor-metal transition (SMT) effect shown by certain materials, for example VO 2 . The switches can be excited by electronic and thermal signals as well, thus two different physical parameters are available for representing the logic states. A proof of concept for the device operation has been demonstrated, and device scaling and integration issues will be discussed too.

Three-dimensional die-stacking architectures have been proposed as a promising solution to the increasing interconnect delay that is observed in scaled technologies. Although prior research has extensively evaluated the performance advantage of moving from a 2-D to a 3-D design style, the impact of process parameter variations on 3-D designs has not been studied in detail. In this paper, we attempt to bridge this gap by proposing a variability-aware design framework for fully synchronous (FS) and multiple clock-domain (MCD) 3-D systems. To mitigate the impact of process variations on 3-D designs, we propose the variability-aware 3-D integration strategy for MCD 3-D systems that maximizes the probability of the design meeting specified system performance constraints. The proposed optimization strategy is shown to significantly outperform the FS and MCD 3-D implementations that are conventionally assembled, for example, the MCD designs assembled with the proposed integration strategy provide, on average, 44% and 16.33% higher absolute yield than the FS and conventional MCD designs, respectively, at the 50% yield point of the conventional MCD designs.

A new process in 4H-SiC is developed that features n-type buried and inversion channel lateral MOSFETs that are fabricated with several different channel lengths (2-8 μm) and widths (8-32 μm ) and characterized over a wide temperature range (25°C-225°C). It is shown that the on-resistance of enhancement-mode SiC MOSFETs reduces with temperature despite a reduction in inversion mobility because of the interaction of interface states with temperature. To enable integrated circuit development using the developed MOSFETs, their electrical characteristics are modeled over geometry and temperature using the industry standard PSP MOSFET model. A new mathematical formulation to describe the presence of the interface states is also developed and implemented in the PSP model, and excellent agreement is shown between measurement and simulation using the modified PSP model.

In this paper, we studied the automated design of analog circuit. Automated design technique of analog circuit has not been established. Auto design has already been positively used in the digital circuit. The difference between the design time has become a bottleneck of the integrated circuit development. Several studies have also been made in the past [1]–[3]. However, they are not practical. Because, made circuit can't be understood by people, or circuit can't be designed. In this paper, I had verified the technique of automatic design, in order to shorten the design time of the analog circuit. Circuit is reliably designed, and yet the designed circuit is understandable. First of all, we decided to automated design an important circuit block of the analog circuit. This time, we decided to design object an operational amplifier because it is widely used in mobile terminal and radio device. Using a genetic algorithm, it is a learning algorithm that mimics the process of evolution going organisms to adapt to the environment. Replacing the minimum design conditions of the operational amplifier to the environment, we evaluated the degree of evolution. Design conditions the following circuit is discarded, high evaluation value circuit will survive to the next generation. Finally we discussed the validity of the finally designed circuit and the study.

Reconfigurable circuit design has become very important in the last decade for increasing the lifetime of CMOS circuits in deep sub-micron technologies. Sense & React approach is one of the reconfigurable design approaches, where degradation in a circuit performance is detected via sensor circuitry and a pre-established recovery operation is applied to circuit. However, sense operations are quite problematic since direct measurement of the degradation in circuit performance is highly complicated. Therefore, indirect measurements are preferred, in which one or more relevant circuit variables, which are called signatures, are selected out of measurable circuit quantities. Conventionally, the designer selects the signatures by performing an iterative search and evaluation on aging simulation results, and no such procedure has been defined in the literature yet. This paper proposes an efficient selection methodology and tool for determining efficient signatures for sense operation.

Integrated circuit technology follows Moores Law scaling down to the nano-scale, and the power consumption challenges become a bottleneck restricting integrated circuit technology development. The development of microelectronics technology has entered the power constraints era. Power consumption becomes a critical issue of integrated circuit design and manufactory. Reducing power consumption may take the place of improving integration and reducing the size of the device, and becomes the driving force of future integrated circuit technology development. The realization of low-power integrated circuits is systematic engineering. From the device level to circuit level and system level, power optimizations should be taken into account, and a tradeoff between performance and power consumption is needed. As CMOS technology scaling down to nano-scale, the effects of leakage current and parasitics of MOSFET become serious issues. Many traditional low-power technologies become a “stopgap” solution, and are difficult to fundamentally solve the problem of the power constraints encountered in the development of integrated circuits. Moreover, the power constraints have affected the sustainable development of nano-scale integrated circuits. In this paper, based on in-depth analysis of all aspects affecting the power consumption of integrated circuits, the technology, the device structure and design methods for the ultra-low-power integrated circuit application are introduced.

In this contribution, the authors describe an application of Defect Oriented Testing (DOT) to commercial mixed-signal designs. A major challenge of DOT application to these designs is the enormous simulation time typically required. The authors address this major challenge with a new algorithm that provides a significant speed-up of over 100x, while at the same time reduces test time by 48% and improves fault coverage by 15%.

Application specific integrated circuits are considered as one essential building block for high speed digital transceivers. We review ASIC requirements and discuss architectural design limitations and implementation optimization options, both driven by system requirements. We provide hardware based proof points for a 100 G design solution and highlight challenges for future designs beyond 100 G.

Based on systems engineering theory, complex systems development process is discussed. The integrated model is built, in which the integration methods are introduced. The product development process is not only a continuously evolutional process, but also an improvement process of product model. A conceptual framework for integrated development is proposed. Furthermore, building a full context model to cover life cycle is to leverage the deployment of system engineering process. The result in this paper has a wider implication upon industrial integrated development for complex systems.

This paper presents the novel research on the low power and low voltage CMOS integrated circuit design patterns and general methodologies. With the integrated circuit technology to the rapid development of the deep sub-micron and nanometer order of magnitude, how to reduce the power consumption of the integrated circuit has become equally important problem with speed, area, power consumption constraints to further improve the performance of the chip, and increase the cost of the integrated circuit. A high level of integration and the application of high-speed device, especially in today's mobile devices and battery power equipment of the large-scale promotion, makes the power dissipation problem is becoming more and more prominent. Our research combines the literature list of reviews to propose the novel implementation paradigm for better performance. The reliability of semiconductor devices in a large part of the way that is depends on the reliability design of the product. In the process of general product development, must be reasonably by means of reliability technology and the engineering design method can effectively improve the reliability of the product, to ensure the reliability of the products. Only in device design reliability basis to achieve high reliability of products. CMOS integrated circuit development up to now, traditional two-dimensional planar integration process has reached its integration density limit, in order to increase performance chip integration more transistors, it is necessary to increase the chip size, and chip size increased with the extension of basic global interconnect distance, the more the grim problem of interconnection to overcome interconnect bandwidth limitations, we must change design method. The advantage of the polycrystalline silicon integrated circuit and the design difficulty can be listed as follows. • Due to the polycrystalline silicon is made up of different grain size and phase velocity of grain boundary structure characteristics, each of the thin film transistor threshold voltage that carrier mobility and series resistance, resulting in the output characteristics of polycrystalline

Nowadays, facing the high elimination rate and the demand for smaller and high-function on the electronic products, it is necessary to have an appropriate method to design in a limited time. Besides, the designer needs to consider not only circuit interconnect but also circuit performance. Therefore, integrating a package can solve the problem that I mention. It is important to build up an equivalent circuit model. In this paper, use the High Frequency Structure Simulator to get the circuit simulation and extract the value of the component. The equivalent circuit model can be built up and individually modify the model. After all the models are confirmed, use the Library Builder of Advanced Design System provided by Keysight to set up the model. In the future, this library can quickly build up the model design and simulate the circuit, instead of wasting too much time on verification.

Where task dependencies are sufficiently complex, process-architecture or task-based Design Structure Matrices (DSMs) can be used to visualize, analyze and optimize those dependencies.This paper explores integrated circuit (IC) new product development (NPD) visualization and optimization (i.e. make more predictable) using such DSMs.First, an initial, non-optimized, DSM is constructed that reflects typical feedforward dependencies derived from integrated circuit development experience and worst-case feedback dependencies derived from potential unplanned iterations (UPIs) what-if analysis.This worst-case starting point is then modified to construct a multiple (two) design/layout iteration version, thereby transforming most of the important feedback dependencies into feedforward ones.Additionally, by explicitly integrating both requirements management and risk management tasks into the NPD DSM, a more predictable and optimized NPD task sequence may be determined.

The design of industrial integrated circuits (IC) in today's advanced technologies is a challenging task that involves several relevant aspects often not considered by academic IC designers. Issues such as time-to-market, design reuse, design for test (DFT), design for manufacturing (DFM), yield, project negotiation and intellectual property management, are highly relevant and often not considered in academic projects. This talk will provide an introduction to the area of industrial integrated circuit (IC) design. It is mainly aimed academic researchers with little or no experience on industrial IC design that want to get involved eventually in the development of commercial IC design projects. Focus will be on practical aspects of industrial IC development, based on the experience of the author in research and development projects with various companies. A detailed case study of an ASIC developed by the author for contactless angular detection in automotive applications will serve to illustrate the different concepts treated in the talk.

PurposeThe primary objective of this paper is to illustrate the development of an integrated product development environment using template‐based methodology. This system would thus act as an effective tool to reduce cost by foreseeing manufacturability constraints during concept generation phase. Concurrent engineering approach is applied to product and process development and thus the different phases of manufacturing are integrated together. The developed template system is then used for the design of a prototype using an electric motor.Design/methodology/approachIn this paper, implementation of an integrated design based on templates is presented. The developed system components such as design calculations, component search, machine selection, process template retrieval and cost estimation. These components are integrated to relational databases. These databases contain all information required for integrated product and process development. Concepts used in developing the system are independent of the software used.FindingsBy using templates, the time required for new product development is drastically reduced. At the same time incorporating computer‐aided process planning into the system gives the designer a better understanding of the cost implications of the modified design with respect to manufacturing. The major challenge in implementing of such system is that any changes in the manufacturing facility have to be incorporated in the process plans stored. This can be a tedious job but can be overcome by using hybrid process planning approach instead of variant based approach.Research limitations/implicationsThe proposed template systems can be further developed to be considered as infrastructure necessary for design within a collaborative engineering environment. Further research and development is necessary for implementation. Though, the result from this case is promising.Originality/valueThe paper proposes the structure necessary for the implementation of a template‐based system. The approach used in the development of the integrated systems could be used by small and mid segment industries which do not have enough resources for costly software upgrading and complex computer technologies. By using templates, the time required for new product development is drastically reduced.

This paper provides some strategies that can help IC designers deal with problems arising from the emergence of advanced manufacturing techniques with minimum dimensions of less than 100 nm. Many of the physical effects that could be ignored in less dense processes are now becoming painfully apparent, making design significantly more difficult and prompting some engineers to reconsider their use of the latest processes. To address this problem, one of the options is to design circuits and systems that achieve fault tolerance using redundancy and other mechanisms. Another option is to use hardware that recognizes when a circuit hasn't performed correctly and uses a built-in recovery mechanism to get the circuit to repeat the desired operation. The availability of multiple central processing units on one chip is expected to change system design as well as significantly increase the opportunity to be constructive in defect tolerance.

Working within the application-specific integrated circuit (ASIC) industry, time to market is very important. With very deep submicron (VDSM) processes, issues with timing enclosure, cell placement efficiency, the antenna effect, signal integrity, etc., have impacted our ability to meet market requirements in a timely manner. By focusing on the design process, two of the major issues, the antenna problem and cell placement efficiency, can be addressed. I propose using knowledge-based priority placement (KBPP), which utilizes design knowledge to simplify those two issues.

The articles in this special section focus on leading-edge research and methodologies that address nagging challenges persisting in today’s 3-D integration, and the work being done to realize both 3-D and hybrid 2.5-D schemes for more fluid design and test platforms that can yield the most benefits at the least cost in the coming years. The selected papers cover a wide range of topics on 3-D ICs, from manufacturing process and 3-D integration technology to test methodologies, applications, and optimization algorithms.

Verification is the most challenging stage in an integrated circuit development cycle. The current techniques used in pre-silicon verification helps the designer catch and fix some errors, but it can not guarantee error free designs for complex integrated circuits in the first fabrication. Some errors are only uncovered after millions of clock cycles. Using post-silicon debug techniques, the designer can monitor the device capturing errors that occur only in a real environment. However, in order to identify an error cause, the related signals should be stored in a trace buffer and then analyzed. Thus, the trace buffer size limits the number of analyzed signals, forcing the designer to use an interconnection fabric to select a signal set to monitor from all tapped signals. In this paper we present a tool to build this interconnection fabric. Our tool is capable to create asymmetric networks like Mux Trees, Clos Networks and Crossbars in Verilog HDL.

In order to optimize integrated circuit designs, it is critical not only for circuit designers to adjust circuit geometries but also for process developers to adjust device characteristics for optimal overall system performance. This paper describes concurrent process-circuit optimization (CPCO), a methodology for concurrent integrated circuit optimization that spans the fabrication process design and circuit design disciplines. CPCO enables process developers and circuit designers to work coordinately toward the common goal of optimizing a system-level objective, and therefore produces better designs than single-discipline optimization schemes. The methodology logically partitions the overall integrated circuit optimization task into loosely coupled process and circuit design tasks that may proceed concurrently-this produces substantial time savings over a flat "all-at-once" optimization approach. Finally, the CPCO method formulates a multiobjective optimization problem that may be used to negotiate tradeoffs in adjusting a single process to optimize multiple circuits, to optimize nominal circuit performances or to improve circuit yield. The implementation of the CPCO method in an extensible object-oriented software architecture is described. Results of applying the methodology to integrated circuit design examples with industrial grade simulation tools are presented. The results demonstrate substantial performance gains over separate process/circuit optimization and substantial time savings over "all-at-once" combined optimization.

Life cycle engineering, or integrated product and process development (IPPD), is a new trend of research and application in industry and academia. In our previous work, a generic framework was proposed to provide a means for an integrated consideration of the performance optimization issues in a product’s lifetime. Based on this generic framework, this paper proposes and presents an integrated product and process development methodology. Important concepts of the methodology are introduced, and an application procedure is provided to illustrate the systematic application of the methodology to real product and process development. Finally, we provide a brief report of our application of the methodology to personal computer development.

This article presents a discussion of several methods that can be used to improve the testability of complex mixed-signal telecommunication integrated circuits. We begin by outlining the role of test and its impact on product cost and quality. A brief look at the pending test crises for mixed-signal circuits is also considered. Subsequently, we outline the evolution of test strategies with time, and their corresponding test setups for verifying the function of the analog portion of a mixed-signal circuit. The article also describes several circuit techniques for improving test access and providing built-in self-test solutions for telecommunication circuits.

Reverse engineering is the process of learning as much as possible about an IC device by transforming a detailed design description into successively higher levels of abstraction. This tutorial focuses on deriving a module-level description from a gate-level netlist.

One of the most complex problems in the integrated design and manufacture of products is the meaningful and rapid conversion of early product specifications into manufacturing and assembly process requirements. The theoretical background to the research described herein is the definition of a new, time-based process planning architecture that consists of three levels corresponding to aggregate, management and detailed planning. The Concurrent Assembly and Process Assessments BLocks for Engineering manufacture (CAPABLE) is an aggregate process planning tool-kit which is designed to support the integrated product development process from its early stages. The main functions of CAPABLE relate to; the identification of production technology requirements, process and equipment selection, production route generation, evaluation of factory configuration and the rapid evaluation of what-if scenarios concerning product configuration and processing options. An initial testing phase has been completed in close collaboration with the industrial partner with very encouraging results.

Even with aggressive new technology, the complex high-performance processor will require special design techniques and architectures to take advantage of new interconnect and transistor technology. Microprocessor on-chip clock frequencies of multiple GHz are predicted for future generations. However, significant development is necessary in technology, manufacturing, and design CAD tools in order to achieve the performance, manufacturability, and reliability desired for these future products. Design must own the test function. The ability of test to continue supporting at-speed testing has reached physical limits as well as cost impacts that will make testing a very high design priority.

This The key to gaining substantial benefit from the use of 3DIC technology is to create 3D specific designs that do more than recast a 2D optimal design into the third dimension. This paper explores some of the approaches to creating 3D specific designs and the CAD tools that can help in that exploration. The power advantages of 3D design are illustrated in details. Results from different partitioning approaches (function, modular and circuit) are presented, together with early results from a thermal pathfinding tool.

Summary form only given. Three-dimensional stacked ICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, all of the above can only become true if 3D-SICs can be properly tested for manufacturing defects. Companies have started to develop their test strategies for these products, and the outcome is largely dependent on (1) the necessity of test generation for specific new 3D defects, (2) the feasibility of access the test targets, and (3) the economic trade-offs involved. Test research is needed to create options for these challenges.

Integrated Circuits (IC) have evolved over the last few decades from modest circuit complexities to highly complex circuit realizations in meeting the market needs. Considering the heavy investments of time, manpower and financial resources in the development of the advanced chips, the original developers of the chip, per force, take steps to protect the various Intellectual Properties (IP) through appropriate IP regimes operating in their countries. In the competitive world of numerous product ranges and less time to market the products, the probabilities of infringements i.e copying of earlier works into the circuits is increasing and hence, there is severe need of capturing the circuit elements with infringements. The IP registering authorities would assess and in some cases evaluate the IC Layout Design filings made for the chip submitted for IP registration including absence of infringements. A well informed developer will also be vigilant to monitor the market to trace any illegal circuit infringement business through copying of their chip works. From these perspectives, it can be seen that screening of the IC Layout Designs (ICLDs) in detail including comparing them with suspicious candidates becomes vital.

The research presented in this paper is concerned with the automation of analog integrated circuit design and, in particular, with a description of methods and techniques employed by the ISAID design system developed at Imperial College, UK. ISAID is comprised of two modules: the circuit generator and the circuit corrector. The circuit generator is based on newly developed methods that are used to handle hierarchical generation of topologies and size MOS transistors so that the performance of designed circuits compare satisfactorily with their specifications. To avoid long design times, simulation is used only after the generation of an initial circuit topology. Simulated performances may therefore be found to differ from the required. One novel feature of the proposed methodology is that in such cases a circuit corrector is invoked to correct the initial design. The circuit corrector is essentially a novel application of qualitative reasoning, which, without iterative simulation analyses performance trade-offs, thereby selects circuit adjustments-transistor size adjustments or topological modifications-that would improve the problematic performances. Several design examples have demonstrated the benefits of the ISAID design approach. >

In recent years 3D IC design and manufacturing is continuously emerging. Along with the variety of possibilities on how to vertically integrate two or more dies, many aspects including cost, design and choice of technology must be considered. Therefore a design methodology and software implementation is presented in this paper which makes use of the mutual dependency of design and process technology in order to provide a manufacturable integration flow.

Database integrity of an information system from its beginning to the end of its life cycle is an important issue of concern among specialists (Melton & Simon, 2002) (Guoqi Feng et al, 2009), (Post & Gagan, 2001) (Eastman C. et al, 1997) (An Lu & Wilfred Ng, 2009). The proposal solution, concerning all the aspects of an information system project, is introduced here with the aim of ensuring the integrity of the database throughout the development of the system. The general aim of this chapter is to propose a method derived from MERISE (Tardieu et al, 1985), consisting of an interconnected set of tools and those heuristics to improve the requirements engineering issues, facilitating the design of specifications, allowing alternatives of organization in terms of workstation, tasks, etc. Establish the requirements for the development of a computer system involves collecting information and expectations from users of various levels of responsibility and belonging to areas that may have, if not conflicting, at least different interests. However, the demands of different users, should reconciled into a set of specifications that will be acceptable, in a concerted way, for all of them. It is essential, to fix up the final solution, to present the proposed options in an understandable way to all users (Zelasco & Donayo, 2011).

As advanced technology process rapidly migrates, more than Moore approach, with pursuing cutting-edge performance, power and area scaling, revolutionary introduction of new material, process and structure will tax traditional reliability target (spec) being continuously adopted for advanced CMOS process qualification to handle reliability concerns with finer granurality. Although ICs for all applications are currently coming from the same technology node and production line, silicon technology developers face technical juggernauts without the definition of application and associated reliability target, based on physics-based degradation model and circuit/system reliability simulation. Since future technology market is going to be driven by reliability-cost and reliability-performance, design aware and application specific reliability qualification is a critical topic needs a full attention in connection to silicon technology users.

Computer-aided design tools are catching up with the shrinking transistor dimensions and channels, high device density, and low power requirements of today's IC designs. These tools aid in power and timing analysis and in the modelling of second order effects. The features of such tools are discussed by the author. >

Verification is the most challenging and time consuming stage in the integrated circuit development cycle. As designs complexities double every two years, novel verification methodologies are needed. We propose an algorithm that dynamically builds and updates an HDL module error proneness list. This list can be used to assist the development team to allocate resources during verification stage. The algorithm is build up using the idea that problematic modules usually hide many uncovered errors. Thus, our algorithm caches the most frequently modified and fixed modules. In an academic experiment composed by 17 modules, using a cache of size 3, we were able to correctly predict almost 80% of the faults occurrences.

This paper reports the progress made in the development of an electronic circuit design tool in an expert system environment. The objective of this knowledge-based system is the entire process of designing electronic circuits including determination of the appropriate circuit configuration, component selection and value calculation, specification of circuit layout, simulation of circuit operation, and automatic design of an appropriate printed circuit board layout. To determine the feasibility of this project, a prototype expert system has been developed to select the most appropriate integrated circuit chip for a dc-dc converter using a commercially available expert system shell, “MicroExpert”. One of the main advantages of the approach adopted is expected to be a reduction in the time needed to design and simulate circuits from weeks to days.

Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or minimum yield requirements. The method is illustrated with the parametric design of integrated CMOS bias stages.

Each industry has unique managerial factors that have a critical impact on a firm's success. These factors, known as key success factors, are the characteristics, conditions, or managerial variables that need to be maintained to achieve prosperity in a given industry. Although techniques for identifying KSFs have been developed, the determination of their priorities will help management allocate resources. Furthermore, connecting KSFs to a firm's major value activities will assist management in planning the firm's business. This article proposes an analytic hierarchy process (AHP) which integrates and operationalizes the theories associated with the KSFs and value chain for the above purposes. The proposed process is applied to the analog integrated circuit (IC) design industry to illustrate its efficacy.

With the worsening of interconnects due to scaling, the reliance of the original physical synthesis paradigm on merely some placement of the cells in order to predict net delays no longer suffices. Practitioners have augmented this paradigm over the years with increasingly sophisticated net models in an effort to improve the accuracy of the interconnect delay predictions. In this paper, we will review these advances and motivate their natural evolution towards “guaranteed” net delays by describing a new scheme known as persistence. Although a naive implementation of persistence can result in unroutable circuits, we will describe how persistence can be applied intelligently in an industrial flow to improve the circuit optimization without impacting its congestion.

Verification is one of the most critical stages in integrated circuit development. Given the current market conditions, a wise manner to improve verification results would be concentrating resources in error-prone modules. In this paper a novel method of attaching information to commit messages is introduced. Through the use of a simple and parseable language, important and more accurate statistics can be retrieved. Tools were developed in order to make commits faster and prevent erroneous data analysis.

Rapid advances in integrated circuit (IC) development predicted by Moore's Law lead to increasingly complex, hard to verify IC designs. Design insiders or adversaries employed at untrusted locations can insert malicious Trojan circuits capable of launching attacks in hardware or supporting software-based attacks. In this paper, we provide a method for detecting Trojan circuit denial-of-service attacks using a simple, verifiable hardware guard external to the complex CPU. The operating system produces liveness checks, embedded in the software clock, to which the guard can respond. We also present a novel method for the OS to detect a hardware-software (HW/SW) Trojan privilege escalation attack by using OS-generated checks to test if the CPU hardware is enforcing memory protection (MP). Our implementation of fine-grained periodic checking of MP enforcement incurs only 2.2% overhead using SPECint 2006.

The classification and quantification of a projected design's technical properties is essential for the prediction of success or failure of a microelectronic development project. The derived values have to mirror the design's capacity and thus allow for an estimation of the design complexity. This chapter depicts the PRODUKTIV+ solution approach to the ascertainment of a design artifact and the determination of equations in particular.

We review the literature for reliability- and process-variation aware VLSI design to find that an exciting area of research/application is rapidly emerging as a core topic of IC design. Design of reliable circuits with unreliable component is a significant challenge that is likely to remain relevant for all circuit designs from now on, therefore any contribution in this field is likely to have lasting effect of the design philosophy of integrated circuits

Today, reliability of electronic products is considered as the minimum requirement to ensure the functionality in a safe and reliable way over years. From the semiconductor sector, as the provider from high-integrated circuits, this trend, is one of the main challenges to ensure the reliability of the product, but much more to precisely predict the reliability of those products. austriamicrosystems very early recognized this trend and implemented the zero-defect program over all process steps from design to the end-of-the-life their product. In this paper an overview of the zero-defect program the achievements and the methods are described is shown.

The well known technology dependency of analog/mixed-signal design largely prevents the same circuits from being used on more than just one specific process, often requiring consuming, error-prone retargeting efforts. This paper presents a new computer-based methodology that significantly facilitates the way analog/mixed-signal circuits can be ported across different processes in a reliable, time-efficient and predictable manner. The use of the proposed methodology in complex analog/mixed-signal industrial projects has reduced design cycle times by factors of 10% and increased the rate of 1st time success. The proposed methodology can be integrated in any of the leading industry EDA environments.

The design of an integrated circuit requires the efforts of a large number of people with a wide range of skills. The compact model is a communication tool by which the designer of transistors, resistors and other circuit elements tells the designer of circuits how the circuit elements behave. Without this information the circuit design would be a trial and error process and modern electronics would be impossible. High quality, industry standard compact models enhance the productivity of the industry by enabling precise communication between any device design team, and any circuit design team, anywhere in the world. To be useful for leading edge design the compact model must keep up with the pace of semiconductor technology innovation. This is the great challenge for the Compact Model Council. It is only possible because the CMC creates collaboration between academics, semiconductor foundries, EDA vendors and circuit designers.