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Background It is unclear to which extent persistence of symptoms and/or residual haemodynamic impairment clinical course of pulmonary embolism are associated with worse quality of life (QoL). Aims To study the correlation between symptoms and haemodynamic impairment with QoL during the first year after acute pulmonary embolism (PE). Methods The Follow-Up after acute pulmonary embolism (FOCUS) study prospectively enrolled and followed consecutive adult patients diagnosed with acute symptomatic objectively diagnosed PE. In the present analysis, we considered patients who completed the Pulmonary Embolism QoL (PEmb-QoL) Questionnaire at predefined visits 3 and 12 months after acute PE. The PEmb-QoL score ranges from 0% (best QoL) to 100% (worst QoL). We evaluated at these two time points the correlation between persisting symptoms (group: symptoms), elevation of natriuretic peptides or residual right ventricular dysfunction (group: RVD), or their combination (group: symptoms + RVD) and QoL. Results A total of 617 patients were included; their median age was 62 years, 44% were women; 8% had active cancer, and 21% previous venous thromboembolism. At 3 months, patients with neither symptoms nor RVD (n=302) had the highest quality of life (median score 18%, 25th–75th percentile: 8%–34%), followed by those without symptoms but with RVD (n=255; median score 19%, 25th–75th percentile: 7%–34%), and by those with symptoms only (n=131; median PEmb-QoL 31%, 25th–75th percentile: 18%–49%). Patients with both symptoms and RVD (n=170) had the worst quality of life (median score 38%, 25th–75th percentile: 19%–53%); Figure 1A. At 12 months, we found an overall improvement of PEmb-QoL score. The degree of this QoL improvement varied across groups, being largest for patients who recovered from having symptoms + RVD at 3 months to normalization of at least one at 12 months. The change in QoL from 3 to 12 months was smaller both in patients who had neither symptoms nor RVD and in patients who had no recovery in either symptoms or RVD; Figure 1B. Conclusions Persistent symptoms after PE, especially in patients with elevated biomarkers or residual echocardiographic dysfunction, were the main drivers of QoL at 3 months as well as of the course of QoL over time. Figure 1 Funding Acknowledgement Type of funding source: Public grant(s) – National budget only. Main funding source(s): University Medical Center of the Johannes Gutenberg University, Mainz, Germany; German Federal Ministry of Education and Research

Objectives Ceftaroline (active form of the prodrug ceftaroline fosamil) is a novel cephalosporin with activity against pathogens commonly associated with community-acquired pneumonia (CAP), including Streptococcus pneumoniae and Gram-negative pathogens. This randomized, double-blind, Phase III study evaluated the efficacy and safety of ceftaroline fosamil in treating patients with CAP. The primary objective was to determine non-inferiority [lower limit of 95% confidence interval (CI) ≥ -10%] of clinical cure rates achieved with ceftaroline fosamil compared with those achieved with ceftriaxone in the clinically evaluable (CE) and modified intent-to-treat efficacy (MITTE) populations. Methods Patients hospitalized in a non-intensive care unit setting with CAP of Pneumonia Outcomes Research Team (PORT) risk class III or IV requiring intravenous (iv) therapy were randomized (1:1) to receive 600 mg of ceftaroline fosamil iv every 12 h or 1 g of ceftriaxone iv every 24 h. Clinical cure, microbiological response, adverse events (AEs) and laboratory tests were assessed. FOCUS 2 registration number NCT00509106 (http://clinicaltrials.gov/ct2/show/NCT00509106). Results The study enrolled 627 patients, 315 of whom received ceftaroline fosamil and 307 of whom received ceftriaxone. Patients in both treatment groups had comparable baseline characteristics. Clinical cure rates were as follows: CE population, 82.1% (193/235) for ceftaroline fosamil and 77.2% (166/215) for ceftriaxone [difference (95% CI), 4.9% (-2.5, 12.5)]; and MITTE population, 81.3% (235/289) for ceftaroline fosamil and 75.5% (206/273) for ceftriaxone [difference (95% CI), 5.9% (-1.0, 12.7)]. Clinical cure rates for CAP caused by S. pneumoniae in the microbiological MITTE (mMITTE) population were 83.3% (35/42) and 70.0% (28/40) for ceftaroline fosamil and ceftriaxone, respectively. Ceftaroline fosamil and ceftriaxone were well tolerated, with similar rates of AEs, serious AEs, deaths and discontinuations due to an AE. The most common AEs for ceftaroline fosamil-treated patients were diarrhoea, headache, hypokalaemia, insomnia and phlebitis, and the most common AEs for ceftriaxone-treated patients were diarrhoea, insomnia, phlebitis and hypertension. Conclusions Ceftaroline fosamil achieved high clinical cure and microbiological response rates in patients hospitalized with CAP of PORT risk class III or IV. Ceftaroline fosamil was well tolerated, with a safety profile that is similar to that of ceftriaxone and other cephalosporins. Ceftaroline fosamil is a promising agent for the treatment of CAP.

Belastungstests konnen zur Beurteilung der korperlichen Belastbarkeit, zur differenzialdiagnostischen Abklarung der Dyspnoe, zur Analyse von Gasaustauschstorungen, zur Beurteilung eines belastungsinduzierten Bronchospasmus, zur Trainingssteuerung und bei der Begutachtung wie auch zur praoperativen Risikoabschatzung eingesetzt werden. Sie sind ferner zur Beurteilung von medikamentosen und nichtmedikamentosen Therapieeffekten sowie zur Abschatzung der Prognose bei zahlreichen Herz- und Lungenerkrankungen hilfreich. Die Auswahl des Belastungstests erfolgt in Abhangigkeit von der Fragestellung. Vor Durchfuhrung der Belastung sollten neben Anamnese und korperlichem Untersuchungsbefund ein Ruhe-EKG, eine Rontgenuntersuchung der Thoraxorgane, fakultativ auch eine Spirometrie mit Bestimmung der Blutgaspartialdrucke in Ruhe erfolgen. Die Belastungstests konnen zur Beurteilung der Ausdauerleistung sowie der maximalen Leistungsfahigkeit eingesetzt werden. Haufigste Belastungsuntersuchungen sind der 6-min-Gehtest, die Ergometrie auf dem Fahrrad in sitzender oder halb liegender Position sowie die Untersuchung auf dem Laufband. Mittels standardisierter Protokolle werden Kenngrosen der Belastung entweder unter Steady-state-Bedingungen oder – zunehmend haufiger – in Form eines Rampenprotokolls untersucht. Die Ergebnisse der Belastungsuntersuchungen sind in Zusammenschau mit Anamnese, klinischen Untersuchungsbefunden und klinischen Befunden zu werten.

Das pulmorenale Syndrom ist ein internistischer Notfall, der unbehandelt mit einer hohen Letalitat einhergeht. Die haufigsten Ursachen sind die ANCA-assoziierten Vaskulitiden – unter diesen am haufigsten die Wegener-Granulomatose und die mikroskopische Polyangiitis – und das Goodpasture-Syndrom. Nach primarer respiratorischer und hamodynamischer Stabilisierung der Patienten ist eine schnelle Diagnose unter Berucksichtigung vieler Differenzialdiagnosen wichtig, um unverzuglich eine adaquate Therapie einleiten zu konnen. Hilfreich sind hier neben einer gezielten Anamnese und Untersuchung die Bestimmung von Autoantikorpern sowie Bildgebung und Bronchoskopie, auserdem sollte eine Nierenbiopsie erfolgen. Der diagnostische Wert einer Lungenbiopsie ist bisher nicht belegt. Die Therapie basiert im Wesentlichen auf einer aggressiven Immunsuppression und der Plasmapherese.

Eine 60-jahrige Patientin prasentierte sich 4 Monate nach einer Herztransplantation mit Fieber und einem neu aufgetretenen Lungenrundherd. Die mikrobiologische Aufarbeitung einer bronchoalveolaren Lavage und eines Lungenteilresektats ergab die Diagnose einer pulmonalen Nokardiose. Weiterhin konnte eine Beteiligung des zentralen Nervensystems festgestellt werden. Eine antibiogrammgerechte Therapie uber rund 1 Jahr fuhrte zu einer vollstandigen Eradikation der pulmonalen und zerebralen Nokardiose. Bei pulmonalen Raumforderungen immunsupprimierter Patienten ist fruh nach einer Organtransplantation vor allem an opportunistische Infektionen zu denken. In der Spatphase konnen Tumoren ursachlich sein.

BASIC PROBLEM AND OBJECTIVE OF THE STUDY Lung volume reduction (LVR) is a new surgical approach designed to relieve shortness of breath and improve exercise tolerance in patients with severe lung emphysema. The aim of this study was to analyse changes of lung function, gas exchange, exercise tolerance and degree of dyspnoea one and 3 months after LVR. PATIENTS AND METHODS Seventeen patients (15 men and two women; mean age 53 [38-68] years) with severe emphysema (six with alpha 1-PI deficiency) underwent unilateral (n = 14) or bilateral (n = 3) LVR surgery. One week before and one and 3 months after surgery pulmonary function tests, arterial blood gas analysis at rest breathing room air, 6-minute walking distance and dyspnoea score (Medical Research Council Scale) were determined. RESULTS There was a significant increase in forced expiratory vital capacity after one second (FEV1, P < 0.001), and a significant decrease in total lung capacity (TLC, P < 0.0001) and residual volume (RV, P < 0.0001). The mean increase in FEV1 was 39% and in PaO2 9%. The mean decrease in TLC was 20%, in RV 26% (P < 0.001; both comparisons), and in paCO2 4% (not significant). The mean 6-minute walking distance increased by 96% from 229 to 405 meters (P < 0.0001). The mean dyspnoea score on a five point scale (0-4 points) decreased by 52% from 3.4 to 1.6. With the exception of the improved inspiratory vital capacity the postoperative results at one and 3 months after LVR did not differ significantly. All patients were alive 3 months postoperatively. CONCLUSIONS In patients with severe emphysema surgical LVR shows significantly improved pulmonary function, gas exchange, dyspnoea and walking distance as assessed one and three months postoperatively. The early mortality seems to be low.

Summary Background Hypocomplementemic urticarial vasculitis (HUV) with pulmonary emphysema is associated with a poor prognosis, despite high-dose anti-inflammatory treatment including steroids. Objective A female former marathon runner, age 47 years, was diagnosed with HUV with skin, renal and pulmonary involvement. Pulmonary arterial pressure was increased during exercise, a novel finding in this disease entity. Complement consumption was associated with the presence of an anti-C1q autoantibody (IgG). Methods The initial treatment included high-dose steroids and chloroquine. In analogy to other systemic inflammatory lung diseases, increased oxidant levels were postulated and high-dose acetylcysteine (NAC) was initiated. Later on, dapsone as an inhibitor of pathologically increased neutrophil function was added. Results Within 3 months, this therapy resulted in a significant increase of the reduced serum complement levels (CH50, APH50, C4A, and C4B), diffusing capacity, decrease of the anti-C1q autoantibody titer, and normalization of the increased granulocyte count in the broncho-alveolar lavage. Additionally, a stepwise improvement of exercise tolerance (6-min walk test, oxygen consumption during exercise) was seen. Dapsone had no further effect on diffusing capacity or (did not affect) complement serum levels, which remained slightly reduced but stable despite the presence of the anti-C1q autoantibody. The effects have remained stable for the following 36 months. The therapy was well tolerated. Conclusions Antioxidant therapy with high-dose NAC might be a potential addition to the conventional anti-inflammatory therapy in patients with HUV and pulmonary involvement. It should be considered for investigation in a larger patient population.

The objective of this paper is to provide a framework by which jitter, in the output signals of a test-head board in an automatic test equipment (ATE), can be measured. In this paper, jitter phenomena caused by radiated electromagnetic interference (EMI) noise are considered. EMI noise is mainly present in the test head of an ATE as result of the activity of the dc-dc converters. An analysis has been pursued to establish the areas of the test-head board that are most sensitive to EMI noise. The most sensitive part of the test-head board has been found to occur in the loop filter of the phase-locked loop (PLL) that is used to obtain a high-frequency clock for the timing generator (TG). Different H-fields are then externally applied to the loop filter to verify the behavior of the output signal in terms of rms jitter. A frequency-domain methodology has been employed for the rms-jitter measurements. The rms-jitter variation for the radiated EMI magnitude and frequency has been characterized. Also, the orientation of the external H-field source has been investigated with respect to the target board and its effects on the measured rms jitter. For measuring the jitter, an interface circuitry has been designed on an adapter board to circumvent ground noise and connectivity problems arising from the test-head environment.

This paper deals with multisite testing of VLSI chips in a manufacturing environment. Multisite testing is analyzed and evaluated using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, fault coverage, and touchdown time for the head). The presence of idle time periods and their impact on the multisite test time is analyzed in depth. Two hybrid testing scenarios which combine built-in self-test (BIST) and automatic test equipment (ATE) are proposed and analytical models are provided to establish the corresponding multisite test time. It is shown that a hybrid approach based on screening chips through a BIST stage improves the performance of multisite test and allows a better utilization of channels in the head of an ATE.

This paper analyzes an environment which utilizes built-in self-test (BIST) and automatic test equipment (ATE), and presents closed-form expressions for fault coverage as a function of the number of BIST and ATE test vectors. This requires incorporating the time to switch from BIST to ATE (referred to as switchover time), and utilizing ATE generated vectors to finally achieve the desired level of fault coverage. For this environment, we model fault coverage as a function of the testability of the circuit under test and the numbers of vectors which are supplied by the BIST circuitry and the ATE. A novel approach is proposed; this approach is initially based on fault simulation using a small set of random vectors; an estimate of the so-called detection profile of the circuit under test is established as the basis of the test model. This analytical model effectively relates the testable features of the circuit under test to detection using both BIST and ATE as related testing processes.

Testing multimodule systems presents several challenges, particularly when systems use submicron technology. The authors propose strategies to diagnose interconnect faults in bus-structured systems using several models. We propose several methods and strategies for a diagnosis using different fault models, including those applicable to submicron technology. Besides defining new features, such as the logical extent of faults, we also propose a reduction strategy that permits 100% fault detection and identification (including fault location).

We present a methodology for production-time testing of one-time programmable field programmable gate arrays (FPGAs) such as those manufactured by Actel. The methodological principles are based on connecting the uncommitted modules (sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays, similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions for constant testability (C testability). Two design approaches are proposed. Features such as testing time and hardware requirements (measured by the number of cycles and additional transistors and primary input-output pins) are analyzed. We show that the proposed designs require considerably less testing time than a previous technique based on scan. The proposed approaches require 8+n/sub f/ vectors for testing the Actel FPGAs, where n/sub f/ is the number of flip-flops in a row. Hardware overhead for the testing circuitry is also analyzed.

An approach is proposed to test FPGA logic blocks, including part of the configuration memories used to control them. The proposed AND tree and OR tree-based testing structure is simple and the conditions for constant testability can easily be satisfied. Test generation for only a single logic block is sufficient. We do not assume any particular fault model. Any number of faulty blocks in the chip can be detected. Members of the Xilinx XC3000, XC4000, and XC5200 families were studied. The proposed AND/OR approach was found to reduce the number of FPGA reprogrammings needed for testing by up to a factor of seven versus direct methods of multiple faulty block detection.

This paper presents a new approach to detecting faults in interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults with a weighted graph, which is then analyzed to appropriately compact the tests and schedule their execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weight heuristics from the weighted adjacency graph. Simulation has been performed for unweighted and weighted fault models. Results on random interconnects and the local interconnect of a commercially available field-programmable gate array are provided. The advantage of the proposed approach is that, on average, early detection of faults is possible using significantly fewer tests than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still having a small number of vectors.

Field-programmable gate arrays can suffer from a variety of faults, ranging from wire anomalies and defects to inoperative programmable connections. The solution to these faults depends on whether or not we are dealing with a reprogrammable FPGA or a one time programmable (OTP) FPGA. To correct faults, developers can reconfigure FPGAs such as those made by Xilinx and Altera by reprogramming. These devices can be programmed many times, for different designs and applications. Correcting faults in OTP FPGAs, such as those made by Actel is more difficult. For one thing, OTP FPGAs are based on antifuses. With an antifuse, the FPGAs configuration information has an initial (default) value that can be changed, but once changed cannot be restored. Therefore, the procedures to bypass faulty cells or faulty routing in an OTP FPGA must meet more stringent requirements than for reprogrammable FPGAs. The "Reconfiguration Approaches" sidebar describes two methods other researchers have tried. This article describes our approach to reconfiguring OTP FPGAs. We explain how we determine if reconfiguration is feasible, the algorithms we used, and the results of our experiments on a generic OTP FPGA model and a generic detail router.

We give three new algorithms to compute tests for faults in the interconnects of random access memories (RAM) using only read and write operations. Diagnosis of address line faults is the most difficult step. Our Adaptive Diagnosis Algorithm (ADA) considers each address line separately. Single line faults are easy to diagnose, so the objective is to ascertain which address lines are free of faults, thereby pruning impossible multi-line faults. Our Consecutive Diagnosis Algorithm (CDA) uses a more complicated and lengthier test sequence. However, with CDA, interpreting the test results is easier and the diagnostic resolution is superior. Our third algorithm, Adaptive Diagnosis Algorithm with Repair (ADAR), relies upon additional testing after repair in order to diagnose more faults than would otherwise be possible. ADAR has three test stages with two repair stages between them.

We present a new technique for testing field programmable gate arrays (FPGA's) based on look-up tables (LUT's). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUT's, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (l-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work.

To determine the optimal redundancy organization for yield enhancement, redundant and modular memories are analyzed using the center-satellite model. The model suggests that the degree of redundancy for a memory module be determined according to its distance from the periphery of the wafer since the defect density increases as the periphery is neared. Analytical expressions are formulated for the yield of memory modules with extra rows and/or extra columns, coding, and coding with extra rows. Results from the analysis suggest that, for high levels of defect densities, coding can be more effective than simple extra rows and columns. For high levels of defect densities, coding with extra rows is shown to offer even better yield. For low levels of defect densities, though, just extra rows and columns may be sufficient for a high yield. An optimal amount of redundancy can be found to achieve the highest possible yield using the model that considers precise cluster distributions on the wafer, defects in a cluster, and the radial variation of these defects. >

A young pregnant woman (32nd week of gestation) presented with acute chest pain due to right coronary artery dissection (CAD) in a pre-hospital setting. The pre-hospital diagnosis by the ambulance staff of an acute myocardial infarction in the antenatal period based on a 12-lead ECG combined with successful treatment by percutaneous coronary intervention with stenting is novel.

An accurate yield evaluation is essential in selecting redundancy allocation and testing strategies for memories. Yield evaluation can resolve the many issues revolving around cost-effective built-in self-test (BIST) and automatic test equipment (ATE)-based solutions for a higher test transparency. In this paper, two yield-calculation methodologies for SRAM arrays are proposed. General yield expressions for VLSI chips are initially presented. The regular and repetitive structure of an SRAM array is exploited, and substantial yield improvements can be achieved by the introduction of redundancy. Two repair yield-evaluation methods for one-dimensional redundant memory arrays are introduced and compared for ATE application. The first method is based on the sum of the probabilities of all repairable fault patterns; the second method is based on Markov modeling. Using industrial data, it is shown that these methods are applicable to ATE usage under different conditions of defect rate in the possible defects. Different features of the proposed methods are discussed

The objective of this paper is to provide a framework by which jitter phenomena, which are encountered at the output signals of a head board in an automatic test equipment (ATE), can be studied. In this paper, the jitter refers to the one caused by radiated electromagnetic interference (EMI) noise, which is present in the head of all ATE due to DC-DC converter activity. An initial analysis of the areas of the head board most sensitive to EMI noise has been made. It identifies a sensitive part in the loop filler of a phase locked loop which is used to obtain a high frequency clock for the timing generator. Different H-fields are then applied externally at the loop filter to verify the behavior of the output signal of the head board in terms of RMS jitter. As for RMS jitter measurements, a frequency domain methodology has been employed. A trend for RMS jitter variation with respect to radiated EMI magnitude as well as frequency has been obtained. Also the orientation of the external H-field source with respect to the target board and its effects on the measured RMS jitter has been investigated. For measuring the RMS value, a proper circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment.

This paper presents theoretical yet practical methodologies to model, assure and optimize the reliability of clockless wave pipeline. Clockless wave pipeline is a cutting-edge and innovative technology as an alternative to traditional pipeline, and a promising computing model towards ultra-high throughput and speed. The basic computational components of such clockless wave pipeline are data waves in association with request signals and switches. The key to the success of clockless wave pipeline is how to coordinate and ensure the processing of datawaves throughout the pipeline in association with the request signals without relying on any intermediate access points under clocked-control. Due to the complication of clockless operations, an efficient and effective method to model and analyze the confidence level (referred to as reliability or yield) of clockless operations of wave pipeline is exigently demanded, but has not yet been adequately addressed, in an integrated level such as datawaves in association with request signals, leaving this as a challenge. In this regard, out-of-orchestration between datawaves and request signals, referred to as datawave fault, is the major concern in assuring and optimizing the reliability of the system. This paper specifically addresses and resolves: extensive and practical clockless-induced datawave-fault modeling; assurance and optimization; clockless-oriented fault tolerant design methods. The proposed methods will establish a sound and adequate theoretical foundation for development of innovative yet practical test/diagnosis/fault-tolerant design methods in early design stage of clockless wave pipeline.

This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (OUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, coverage and touchdown time for the head). Two scenarios which permit immediate and delayed replacements, are considered and analytical models are given to establish the multisite test time of an ATE. A hybrid BIST and ATE approach is also analyzed to improve the performance of a multisite test environment and to better utilize the channels in the head of the tester.

Recent research on modeling timing jitter has raised a requirement for a predictable, high magnitude, uniform, and wide bandwidth H-field. In this paper, a novel H-field generator design methodology is proposed. It consists of a single layer air core solenoid and a digital power switch driver that takes advantage of low power, wide bandwidth, and big current-driven capability. With input overdrive voltage, the digital switch can drive rail-to-rail voltage with output current up to 16 A and power bandwidth more than 3 MHz. This paper demonstrates a novel solenoid driver circuit to generate an accurate H-field by comparing digital and analog approaches and comparing the experimental data with the theoretical data.

Advances in spaceborne vehicular technology have made possible the long-life duration of the mission in harsh cosmic environments. Reliability and data integrity are commonly emphasized requirements of spaceborne solid-state mass storage systems, because faults due to the harsh cosmic environments - such as extreme radiation - can be experienced throughout the mission. Acceptable dependability for these instruments have been achieved by using redundancy and repair. Reconfiguration (repair) of memory arrays using spare memory lines is the most common technique for reliability enhancement of memories with faults. Faulty cells in memory arrays are known to show spatial locality. This physical phenomenon is referred to as fault clustering. This paper initially investigates a quadrat-based fault model for memory arrays under clustered faults to establish a sound foundation of measurement. Then, long-life dependability of a fault-tolerant spaceborne memory system with hierarchical active redundancy, which consists of spare columns in each memory module and redundant memory modules, is measured in terms of reliability (i.e., the conditional probability that the system performs correctly throughout the mission) and mean-time-to-failure (MTTF i.e., the expected time that a system will operate before it fails).

Performance and reliability are two of the most crucial issues in today's high-performance instrumentation and measurement systems. Instrumentation and measurement systems have found and enjoyed their performance enhancement through parallel and distributed processing. High speed and density Multistage Interconnection Networks (MINs) are widely-used subsystems of parallel processing and communication systems. New performance models are proposed to evaluate the fault tolerant MIN in this paper, thereby establishing a sound foundation for assuring the performance and reliability of fault tolerant MINs with high confidence level during parallel instrumentation. A concurrent fault detection and recovery scheme for MINs is introduced to enable a generic approach to fault tolerance by rerouting over the redundant interconnection links. A switch architecture to realize the concurrent testing and diagnosis is shown. The proposed performance models are developed and used to evaluate the compound effect of the fault tolerant operations such as testing, diagnosis and recovery on the throughput and delay. Results are shown on single transient and permanent stuck-at fault on links and storage units in switching elements. it is shown that the performance degradation for the overhead due to the fault tolerance is quite graceful while the performance degradation without fault recovery is unacceptable.

This paper presents a novel approach for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Different testing objectives (detection and maximal diagnosis) are considered. An extensive analysis of the faults is pursued to characterize their impact on the BCMRS as well as on the test operations (such as WRITE and READ).

A comprehensive approach is given to reconfigure field programmable gate arrays (FPGAs) with faults in the logic resources. Reconfiguration consists of a reassignment of the cells that takes into account the one-time programmable nature of the chip resources. The method alters neither the FPGA nor the fault-free design; so the effectiveness of the reassignment depends on the efficient use of routing resources in the fault-free design. Under a generalized architecture, the spare routing resources needed are obtained to bypass each faulty cell and reassign its functions to a spare (unused) cell. If every channel has as many spare trades as half the number of logic cell inputs and outputs, then any single faulty cell can be reassigned, thus yielding a successful chip reconfiguration. The proposed reassignment algorithm has an efficient execution, so it can be run while chips are programmed and tested on an assembly line. The number of calls to the routing software is at worst quadratic in the number of faulty cells, provided no backtracking is needed in the reassignment. Under some randomness assumptions, the average number of calls to the routing software is linear in the number of faulty cells. The proposed method is analyzed with benchmark circuits and simulation results are presented.

We give a comprehensive model of interconnect testing in boundary scan architectures. This includes two fault categories: driver faults (stuck-at, stuck-driving, and stuck-not-driving (equivalent to stuck-open)) and net faults (shorts). We permit short faults to exhibit zero-dominance (wired-AND), one-dominance (wired-OR), and net-dominance. We split the built-in self-test hardware into two components: a control pattern test generator (CTPG) and a data pattern test generator (DTPG). For the DTPG, we use a complementary counting sequence, which is an instance of a maximal independent test set. We give novel designs for CTPGs that guarantee 100% fault coverage with low hardware overhead and time complexity. We give a general and complete procedure to implement the CTPGs. Using a linear feedback shift register as a one-shot counter to cover all control cells in the boundary scan, we ensure that no two control cells of one net are assigned to a single register; this avoids circuit damage when testing.

In this paper, a novel architecture for built-in self test (BIST) and different designs for both the control and data test pattern generators (CTPG and DTPG) are proposed for interconnect testing using the IEEE standard 1149.1. A general and complete procedure to implement this architecture is also presented. For the DTPG design, the complementary counting sequence (as an example of a maximal independent test set) is used for fault detection. One of the main features of this design is its independence with respect to the type of cell in the chain. A novel design is proposed for the CTPG to avoid damage to the circuit as well as to guarantee 100% fault coverage with low hardware overhead and time complexity.

This paper analyzes the architectural and complexity features of the array-based testing technique for field programmable gate arrays (FPGAs). The analysis is pursued using a hybrid (functional/stuck-at) single fault model by considering both the architecture of the configurable logic block (CLB) as well as the whole FPGA. Its evaluation using three commercially available FPGA families by Xilinx is presented in detail; emphasis is given to the different array configurations which permit the observability/controllability requirements of the testing process to satisfy the input/output restrictions (given by the I/O pins) of the FPGA, while still reducing the number of required programming phases.

This paper addresses the issues pertaining to testing field programmable gate arrays (FPGAs) using an array-based technique. In particular, the issues of testing configurable devices (such as multiplexers and flip-flops) in the sequential array process (as the most significant factor for assessing complexity) and the arrangement for pipelining test vectors are treated in detail. Initially testing procedures for a configurable flip-flop and a programmable multiplexer are presented. At system-level, two new pipeline arrangements referred to as the quasi-pipeline and normal pipeline structures are proposed for reducing the number of programming phases. The application of the proposed approaches to the XC4000 FPGA family is also presented.

We present a novel approach for detecting faults in tristate system environments-e.g., in multiple board systems. These environments are made of an interconnect and drivers/receivers with tristate features. We present a comprehensive fault model that includes faults in terminals (drivers/receivers) and nets. Under this fault model, physical faults (stuck-at and short), as well as functional faults (dominance, permanently enabled or permanently disabled driver modes), are taken into account. We show that, for a single net with L drivers, 2L tests are necessary and sufficient for fault detection. This is independent of the number of receivers. We extend this result to a system environment with N nets and where K is the maximal number of drivers for a net. Under the proposed fault model, any number of faults of any type can be detected in a system environment using any types that can be detected in a system environment using max (2K, P) tests, where P is the minimal integer that satisfies C/sub /2//sup P//spl ges/N. If only the traditional (wired-AND or wired-OR) model is assumed, then the test set required for fault detection can be further reduced. We provide simulation results and show that the proposed approach outperforms previous methods found in the technical literature.

This paper presents two new approaches for testing interconnects of random access memories (RAM). Tire first algorithm is referred to as the Adaptive Diagnosis Algorithm (ADA), while the second algorithm is referred to as the Consecutive Diagnosis Algorithm (CDA). Initially, it is shown that the diagnosis of the address lines is the most difficult step in interconnect testing of memories as the diagnosis of faults in data lines can be resolved easily. The execution of ADA is such that the diagnosis of the address lines is performed sequentially (i.e. on a line by line basis), while enforcing the conditions by which it is possible to differentiate for each line a stuck-at fault from a short. This is determined by the operations as for diagnosis a short requires an additional READ compared with a suck-at fault. A different condition in the generation of the overall sequence is utilized in CDA; by using different test patterns for the address lines, a relation can be assessed between consecutive READ operations.

This paper presents a novel approach for fault tolerance of one-time programmable FPGAs by reassignment of routing resouces. As the underlying problem is NP-complete, a greedy algorithm is proposed to provide rapid, but suboptimal solutions. Due to the one-time programmable characteristic of the switches (commonly referred to as antifuses), only unused (fault-free) routing resources must be utilized for reassignment in a chip with a faulty interconnect. We specifically investigate whether reassignment could be accomplished without changing the global routing of any connections. A RC-tree model for the net delay is also presented; delay bounds are established to fully quantify the degradation due to the reassignment. Extensive simulation results are provided.

The problem of establishing reliable communication across point-to-point networks is addressed. Several protocols are given, using node-disjoint paths to implement a set of independent virtual links (u-links) between each node pair. The u-links can be used to establish communication between the node pair provided the number and type of failures in the network are limited. Failed devices are classified by whether they are benign (delay and omission faults) or are malicious (not benign). The use of u-links is demonstrated with a protocol for remote information retrieval. With b benign and m malicious faults, retrieval can always be achieved if the graph connectivity exceeds b+2 m. This bound is tight. The authors give a flexible retrieval protocol; it analyzes the responses received thus far, and computes a minimum and maximum number of u-links to send (additional) retrieval requests. Maximal requests guarantee completion of the protocol upon their timeout. With minimal requests, protocol completion is barely possible with no further requests. u-links are extended so that they bounce requests when there is no response, which strengthens the retrieval protocol.

This paper presents a novel approach for testing and diagnosing configurable field programmable gate arrays (FPGAs). The proposed approach is row-based and uses a two-session procedure. The approach arranges some logic blocks to be programmed as XOR-tree (or chain, or cascade) in the first session. The XOR-tree is effectively used as test vehicle for observability. The roles of the CLBs are inverted in the second session. It is shown that the proposed testing arrangement requires a number of tests independent of the number of CLBs in the FPGA (i.e. C-testability is accomplished). Routing is kept local, and compatibility for a CAD implementation is also accomplished.

This paper presents a combined approach for testing logic and routing resources in programmable logic devices (PLDs). The proposed approach is based on configuring the PLD using different arrangements such as built-in self-test schemes (for example, a parity chain) and one-dimensional arrays (with and without common inputs). It is proved that the proposed approach achieves 100% fault coverage under a fault model consisting of a single fault in the logic resources and active routing devices, or multiple faults in the interconnection channels and input/output lines.

The average new chip design already exceeds two million devices. Companies are racing to produce innovative systems-on-a-chip (SoC). Economic exigencies are mandating the re-use of core designs. These trends have led to new research concerns in SoC testing, SoC yield prediction, core interfacing, and intellectual property (IP) protection. In this work, we address design decisions associated with embedded cores that have defect-tolerant properties. Specifically, we address whether knowledge about the remainder of the chip would result in different core design decisions pertaining to yield.

This paper presents new approaches for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short, open and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Detection and maximal diagnosis are considered under a restricted fault model (short faults only) as well as a general fault model (all types of faults).

Lung volume reduction surgery (LVRS) in patients with severe lung emphysema restores the thoracic configuration to a more normal functional capacity. The aim of this study was to investigate whether reduction in intrathoracic volume by LVRS improves the inspiratory muscle force generation of the respiratory pump. Pulmonary function tests, maximal inspiratory mouth pressure (MIP), sniff nasal inspiratory pressure (SNIP), sniff transdiaphragmatic pressure (Pdi), and inspiratory mouth occlusion pressure (P0.1) were measured in 17 emphysematous patients (mean (+/- SEM) age 53 +/- 2 yrs) before and 1 month after LVRS. The mean value of forced expiratory volume in one second (FEV1) increased (0.82 +/- 0.07 vs 1.12 +/- 0.08 L; p < 0.0001), whilst there was a decrease (p < 0.0001) in residual volume (RV) (337 +/- 31 vs 250 +/- 21 % of predicted), functional residual capacity (FRC) (210 +/- 9 vs 159 +/- 9% pred), and total lung capacity (TLC) (138 +/- 6 vs 110 +/- 5% pred). The mean value of MIP increased by 52% from 4.8 +/- 0.4 to 7.3 +/- 0.6 kPa (p < 0.001), the mean value of SNIP increased by 66% from 3.9 +/- 0.4 to 6.5 +/- 0.5 kPa (p < 0.001), and the mean value of Pdi increased by 28% from 6.0 +/- 0.6 to 7.7 +/- 0.8 kPa (p < 0.05) after LVRS. P0.1 decreased on average by 24% from 0.46 +/- 0.03 to 0.35 +/- 0.02 kPa after LVRS. No significant correlations were found between inspiratory muscle (MIP, SNIP, Pdi) and respiratory drive (P0.1) indices, lung function data, 6 min walk distance, or dyspnoea score. In conclusion, the observed clinical improvement of patients with severe emphysema after lung volume reduction surgery results, in part, from an increased ability of the inspiratory muscles to generate force, which is paralleled by a significant decrease in central respiratory drive.

A second-order state space load model was developed and adapted for parameter identification. A weighted least squares identification process was developed to identify model parameters from measurements of load current response due to changes in input voltage. An induction motor model response was used to provide measured input-output load response. The state space load model was implemented in a typical power system stability program. The application of the state space load model to transient stability studies demonstrates that it can more accurately reflect actual load response than conventional stability load models. The state space load model is shown to adequately model the dynamics of power system composite bus load.

This paper is one of a series presented on behalf of the Systems Operations Subcommittee with the intent of focusing industry attention on current problems faced by electric utilities in the operation of its bulk power system. Four short note reports are presented which direct attention to problem areas being faced by utilities in regard to non-utility generation systems. Each report focuses on different aspects of the nonutility generation problem. Reports which are included address generation and fuel, transmission, distribution, and Energy Management and Control Systems.