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Schottky contacts have been used to fabricate normally-off lateral reverse-blocking MESFETs on p-type (boron-doped) O-terminated monocrystalline diamond. The devices utilized an ohmic source contact but both gate and drain contacts were Schottky in nature. Boron-doped p-channel diamond MESFETs reported to date display the less attractive normally-on characteristics. Here, the normally-off transistor delivered a current level of ~1.5 μAmm⁻¹ at a negative $V_{GS}$ of 0.8 V and a transconductance (gₘ) of 16 μSmm⁻¹, measured at room temperature (RT); at a temperature of 425 K, these values rose to ~70 μAmm⁻¹ for $I_{DS}$ and a gₘ value of 260 μSmm⁻¹. In both cases, a negligible gate leakage current was measured with no breakdown apparent at the maximum field investigated here (3.7 x 10⁵ V/m⁻¹). The Schottky gate demonstrates a well-behaved control of the channel even at higher temperatures. The high-temperature operation, normally-off behavior, and diamond's inherent radiation hardness make this transistor promising for harsh environment applications.

As superjunction devices are scaled down to smaller dimensions, the gate ringing becomes more prominent in dynamic switching. The exact origin of superjunction MOSFET 's gate ringing has not been so far identified as the conventional three-terminal measurement method cannot capture the dynamic behavior of the device, in particular the redistribution of charge between the different internal capacitive components in the superjunction structure. In this article, it is found that the gate ringing is highly related to the input capacitance. Specifically, by employing a TCAD model with a split gate method, the gate-to-source ( CGS ) and gate-to-drain ( CGD ) current are investigated during the dynamic transitions. The gate ringing is highly dependent on sum of the input capacitances ( CGS + CGD ) for the turn- on . In the case of the turn- off , however, the gate ringing is affected by the ratio of the input capacitances ( CGD / CGS ) and a lower CGS is desirable for a low gate oscillation.

The impact of different p-well designs upon the transient performance, in particular, the turn-off losses and short-circuit capability, of a >10 kV SiC n-IGBT is assessed. We find that in addition to improved transient performance, a substantial reduction in the depth of p-well implants can be achieved, if an extensively optimized retrograde approach is utilized. A conventional p-well consisting of a uniformly doped deep implant (doping concentration of ~3×1017 cm-3 and depth of >1.5 µm) exhibits considerable turn-off switching losses without offering any short circuit capability. However, an optimized retrograde p-well consisting of a variable doping profile and depth as shallow as 0.7-0.8 µm results in much reduced turn-off losses with excellent short-circuit capability. Shallow implants are desirable to lower the development cost and processing challenges. The retrograde p-well is therefore highly promising for the development of >10 kV class of SiC IGBTs.

Multi-epitaxially grown superjunctions feature a fluctuation of the doping concentration (ripple) in the pillars and the ripple is highly dependent on the supplied thermal energy during the fabrication. This study thoroughly investigates the relationship between the ripple in the pillars and the static/dynamic characteristics of the device. The ripple dependent trade-offs in terms of the specific resistance and turn-off switching loss will be able to provide a guide for developing fine pitch superjunction devices.

Funder: National Physical Laboratory; doi: http://dx.doi.org/10.13039/501100007851, Funder: Royal Society Dorothy Hodgkin Research Fellowship, The gas sensor market is growing fast, driven by many socioeconomic and industrial factors. Mid-infrared (MIR) gas sensors offer excellent performance for an increasing number of sensing applications in healthcare, smart homes, and the automotive sector. Having access to low-cost, miniaturized, energy efficient light sources is of critical importance for the monolithic integration of MIR sensors. Here, we present an on-chip broadband thermal MIR source fabricated by combining a complementary metal oxide semiconductor (CMOS) micro-hotplate with a dielectric-encapsulated carbon nanotube (CNT) blackbody layer. The micro-hotplate was used during fabrication as a micro-reactor to facilitate high temperature (>700 ∘C) growth of the CNT layer and also for post-growth thermal annealing. We demonstrate, for the first time, stable extended operation in air of devices with a dielectric-encapsulated CNT layer at heater temperatures above 600 ∘C. The demonstrated devices exhibit almost unitary emissivity across the entire MIR spectrum, offering an ideal solution for low-cost, highly-integrated MIR spectroscopy for the Internet of Things.

We present a miniaturised thermal acoustic gas sensor, fabricated using a CMOS microhotplate and MEMS microphone. The sensing mechanism is based on the detection of changes in the thermal acoustic conversion efficiency which is dependent on the physical properties of the gas. An active sensing element, consisting of a MEMS microphone, is used to detect the target gas while a reference element is used for acoustic noise compensation. Compared to current photoacoustic gas sensors, our sensor requires neither the use of gas-encapsulated microphones, nor that of optical filters. In addition, it has all the benefits of CMOS technology, including production scalability, low cost and miniaturization. Here we demonstrate its application for CO[Formula: see text] gas detection. The sensor could be used for gas leak detection, for example, in an industrial plant., We acknowledge funding from EPSRC grants EP/S031847/1, EP/R022534/1, Alan Turing Institute Award TU/B/ 000096 under EPSRC Grant EP/N510129/1, and Royal Society Equipment Grant RG170136.

A p-well consisting of a retrograde doping profile is investigated for performance improvement of >10kV SiC IGBTs. The retrograde p-well, which can be realized using low-energy shallow implants, effectively addresses the punch-through, a common issue in high-voltage vertical architectures consisting of a conventional p-well with typical doping density of 1e17cm-3 and depth 1μm. The innovative approach offers an extended control over the threshold voltage. Without any punch-through, a threshold voltage in the range 6V-7V is achieved with gate-oxide thickness of 100nm. Gate oxide thickness is typically restricted to 50nm if a conventional p-well with doping density of 1e17cm-3 is utilized. We therefore propose a highly promising solution, the retrograde p-well, for the development of >10kV SiC IGBTs.

An analytical model for superjunction (SJ) MOSFETs having an oxide pillar between the n-pillar and the p-pillar is developed. Owing to the low permittivity of the oxide, a high electric field is sustained across the oxide. This reduces the parasitic depletion width within the n-pillar, thus improving the current conducting path. The advantage of this structure is particularly visible as the cell pitch is scaled down and the pillows become narrower. The use of an oxide pillar leads to 30% reduction in the specific ON-state resistance when compared to a conventional SJ for a 2- $\mu \text{m}$ cell pitch. The analytical model shows a good agreement with the simulation results.

This paper investigates the advantages and disadvantages of bonding pad over active area (BPOA) layout over a conventional layout for lateral AlGaN/GaN HEMTs designed for use in power applications. Extensive analysis of the performance of a BPOA device, both experimentally and supported by 3-D TCAD model simulations, reveals that while it can offer a higher current capability per unit area, it can lead to other disadvantages compared to a conventional design when considering reliability aspects.

A new type of high-voltage termination, namely the “deep p-ring trench” termination design for high-voltage, high-power devices, is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required but also removes the need for an additional mask as is the case of the traditional p+ ring-type termination. Furthermore, the presence of the p-ring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide, which results in reduced hot carrier injection and improved device reliability.

In ISPSD 2020 it has been shown that the effective mobility of a lateral 4H-SiC MOSFET could be increased by an order of magnitude through using an ultra-narrow-body design. Thus, this work presents further experimental results on a wide set of fin widths, ranging from conventional (860nm) to ultra-narrow (35nm). Furthermore, a 3D TCAD model, employing quantum corrections, is matched to experiment and applied to study these designs. It is thereby shown that the FinFET effect can have a strong impact in SiC devices and may allow for up to an 18x increase of the mobility relative to a reference width of 280nm. Finally, an optimization window of ~30-50nm is predicted for the fin width, below which the FinFET effect becomes detrimental.

This paper presents for the first time a combined experimental/numerical study of the electro-thermal surge current behaviour of 6.5kV SiC MOSFETs for various cell layouts. By means of a matched TCAD model it is demonstrated that the circular (and hence also the hexagonal) topology shows an inferior surge capability to the stripe. Conversely, the ALL allows for the dissipated losses and the peak lattice temperature attained during a 10ms pulse test to be reduced in both body and channel diode mode. In this context, it is shown that the sensitivity of the device’s response to the active area can be decreased at smaller pitches.

In this paper we present a snap-back free 3.3kV, 75A Reverse Conducting IGBT (RC-IGBT) with improved Reverse Bias (RBSOA) and Short-Circuit (SCSOA) Safe Operating Areas. The device employs floating N+ regions under the gate BUSBARs to locally reduce hole concentration and uses segmented N+ Anode regions to minimise the reverse recovery losses. The device architecture was conceived on extensive TCAD modelling and a DOE approach. The best design variants have been manufactured, tested and used for extensive analysis of key device trade-offs.

In this paper we present a novel MEMS technology for CO 2 detection, based on differential thermal conductivity. Holes have been positioned across the thin-film dielectric membrane to induce an asymmetric temperature profile in conjunction with a centrally heated tungsten resistor, leading to distinct magnitudes of gas interaction across the sensor, all of which is substantiated by a numerical model. Differential readings are taken from four surrounding resistors and shown to correlate to CO 2 concentration. The best resistor combination is investigated and is shown to provide a sensitivity of 0.05 mV/%CO 2 . Using separate heating and sensing elements greatly lowers the noise and a detection resolution of < 100 ppm is calculated. This proof-of-concept article introduces a device that could lead to low-cost, low-power, high-sensitivity, scalable gas detection.

Low-cost infrared (IR) thermal cameras are powering a rising market of industrial and consumer applications. Complementary metal-oxide-semiconductor (CMOS)-based thermopile arrays are proven thermal imagers that can be monolithically integrated into low-cost and low-power-consumption formats for high-volume manufacturability. Here we present a simple method to evaluate the cross-talk of these arrays and propose a numerical model for device optimization.

Early diagnosis in exhaled breath is a key technology for next-generation personal healthcare monitoring. Current chemiresistive sensors, primarily based on metal oxide (MOx) thin films, have limited applicability in such portable systems due to their high power consumption, long recovery time, poor device-to-device consistency, and baseline drifts. To address these challenges for ammonia ($${{\rm{NH}}}_{3}$$ NH 3 ) detection in exhaled breath, a critical biomarker for a variety of kidney and liver problems, we present a formulation of a graphene–MOx functional ink-based sensing platform. We integrate our sensing layer directly onto miniaturized CMOS microhotplates (μHP) via inkjet printing, potentially enabling scalability and device-to-device performance repeatability. Using stage-by-stage temporal analysis, and a temperature-pulsed modulation (TM) strategy, we achieve ultrahigh responsivity (1500% at 10 ppm pure $${{\rm{NH}}}_{3}$$ NH 3 ), fast response and recovery time (28 and 43 s), ultralow power consumption (~6 mW), negligible baseline drift ($${{\rm{WO}}}_{3}$$ WO 3 ) device as part of the sensor array. Our dual graphene–MOx formulations and their integration with ultralow power CMOS through inkjet printing represent a significant step towards reliable and portable multi-analyte breath diagnostics.

It is common knowledge that the gate ringing of a power MOSFET is proportional to the dV/dt during the dynamic switching. In this study we show a particular situation when the gate ringing can be reduced significantly with a faster dV/dt. The faster dV/dt occurs when the driving current in the superjunction MOSFET increases, leading to faster charging of the parasitic capacitance. Initially, the gate ringing increases with the higher dV/dt. However, beyond a certain level the gate ringing starts to decline with further increase in the dV/dt. This abnormal phenomenon originates from the temporary turn-off the MOS channel during the turn-off transition.

Commercially available high voltage Silicon Carbide (SiC) Junction Barrier Schottky (JBS) are typically designed with advanced anode topography depending on the manufacturer and the specific current-voltage rating. The anode layout of JBS rectifiers affects a wide range of electro-thermal parameters such as the leakage current and the response of the diode to over-current events (surge current capability). In this paper, the effect of 3D anode geometries for the active area of 3.3 kV-20 A SiC JBS diodes is investigated in detail for both single and repetitive surge current events. By means of advanced 3D electro-thermal finite element simulations, a trade-off between the main factors which are contributing to the bipolar behavior activation is identified.

The planar Integrated Gate Commutated Thyristor (IGCT) concept is proposed to simplify the fabrication process of the device and improve the ruggedness as well as electrothermal performance of the device. The planar IGCT concept has been verified experimentally with 4.5kV devices fabricated on 4-inch Si wafers. Afterwards, the electrical characteristics of the planar IGCT were compared with that of the conventional (with trench or mesa gate) IGCT. Both the planar and the conventional IGCTs are fabricated with corrugated p-base referred to as High Power Technology (HPT) design. In addition, mixed-mode TCAD device simulations have been performed to verify the turn-off failure mechanism and to analyze the electro-thermal performance of the planar IGCT in reference to that of the conventional IGCT.

A novel Trench IGBT design, namely the p-ring Trench Schottky IGBT, with improved latch-up immunity and an enhanced safe-operating area is proposed. This design improves the performance of the FS+ IGBT by facilitating the collection of holes through a p-doped (p-ring) buried region connected through a Schottky contact to the source/cathode contact. This unique structure approach allows the improvement in the device reliability and it is shown under numerical studies to be highly effective in expanding the safe operating area (SOA), suppress dynamic avalanche, improve the latch up robustness and have the potential to improve the device switching operation.

A lateral trench SiC MOSFET with lateral conduction on the side walls was designed using an ultra-narrowbody (UNB) sandwiched by the trench walls. The p-body is designed to be very narrow in order to avoid any depletion region formed in its body. The structure is similar to a FinFET, but applied to a SiC device. The body width in the channel region of the fabricated UNB MOSFET was 55 nm. The drain current of the UNB and conventional MOSFET were 1.27 μA and 0. 11μA, respectively, at $V_{D S}=30 V$. The UNB structure presented a significant increase in the mobility, reaching values of over 200cm2/Vs. The result indicated a very prominent FinFET effect, resulting in very high mobility and hence very significant improvement in the channel resistance of SiC MOSFETs.

Partial SOI (PSOI) is revisited as a suitable High Voltage (HV) architecture for Power Integrated Circuits (PICs). The added process complexity compared to SOI RESURF is offset by the better heat conduction due to thinner BOX, the wider voltage range capability and the reduced parasitic capacitance to the Handle Wafer (HW). The new proposed platform technology is therefore particularly relevant to the manufacturing of high voltage integrated circuits (HVICs) where low Ron, fast switching and reduced self-heating are essential. This work reports on the extension of a 200V PSOI process to 400V while providing competitive Ron and low HCI degradation.

We present a new experimental technique to characterise the crosstalk of a thermopile-based thermal imager, based on bi-directional electrical heating of thermopile elements. The new technique provides a significantly simpler and more reliable method to determine the crosstalk, compared to a more complex experimental setup with a laser source. The technique is used to characterise a novel single-chip array, fabricated on a single dielectric membrane. We propose a theoretical model to simulate the crosstalk, which shows good agreement with the experimental results. Our results allow a better understanding of the thermal effects in these devices, which are at the center of a rising market of industrial and consumer applications.

The file attached to this record is the author's final peer reviewed version. The Publisher's final version can be found by following the DOI link. This paper presents the high temperature thermal characterization of a Micro-Electro-Mechanical Systems (MEMS) infra-red (IR) thermal source, using non-contact optical approaches, based on IR and thermo-incandescence microscopy. The IR thermal source was fabricated using a CMOS based processing technology and consists of a miniature micro-heater, fabricated using tungsten metallization. The performance and reliability of the IR source is highly dependent on its operating temperature. For short-wave (1.4 μm - 2.5 μm) infra-red emission, the operating temperature is in excess of 800°C. Work will be presented in this paper in which spot temperature measurements (> 700 °C) were made on the IR source using thermal-incandescence microscopy. Thermal-optical calibration was achieved by utilizing the known melting point (MP) of different metal micro-particles. Optical measurements were compared to those obtained using an electrical approach. The thermal measurements suggest good temperature uniformity across the micro-heater of the IR source.

Temperature monitoring and thermal management of CMOS circuits / sensors is often required for long term circuit reliability and sensors temperature compensations. The ideal solution is to co-fabricate the temperature sensors along with the CMOS circuits and other sensors using CMOS materials and the same CMOS processes. In this paper we therefore, report on the fabrication and thermal characterization of such thin film temperature sensors. The thin film Resistance Temperature Detectors (RTDs) are made of single crystal p-type silicon on a silicon substrate using a Silicon on Insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process. The influence of thin film length and width on the response of RTDs has been investigated. Furthermore, the effects of aluminum (Al) and tungsten (W) metallization used for power tracks on the response of RTDs have been studied. To assess the performance of the RTDs based on SOI CMOS p-type silicon, in addition to sensitivity and TCR, their power consumption, linearity, hysteresis, repeatability, reproducibility and expected life span have also been evaluated. The p-type silicon RTDs consume very less power (i.e. 0.9 μW only) and demonstrate a sensitivity of 13.88 Ω / oC, which is much higher than the previously reported CMOS RTDs and widely used non-CMOS platinum RTDs. The RTDs also exhibit a linear response (98.9% fsd), an excellent repeatability and significantly low hysteresis with maximum variation of 0.2% between forward and reverse cycle. These RTDs also boast good reproducibility, within the wafer and wafer to wafer, with maximum sensitivity variation of 1.3% between different tested samples. The expected life span of the RTD is > 10 years. These inexpensive RTDs are therefore, good candidates for use as temperature sensors on CMOS circuits / sensors system.

The impact of electron injection from the substrate on the dynamic Ron of GaN-on-Si High Electron Mobility Transistors (HEMTs) has been investigated by means of back-bias transient and vertical leakage measurements and TCAD simulations. A strong correlation between electrons injected from the substrate and on-state drain current transients is demonstrated. Moreover, the contribution of the electron-type traps in the buffer layer as opposed to the usually studied hole-like traps to the dynamic Ron is discussed. In particular, the impact of electron-like traps for different levels of substrate leakage current is studied. A TCAD model has been developed and calibrated by taking into account both off-state vertical leakage and on-state drain current transient experimental results. The proposed charge dynamic has also been assessed against state-of-the-art theories. This analysis contributes to a deeper understanding of the complex scenario of different types of traps in the buffer layer of GaN-on-Si devices and highlights the impact that trap-states can have on the on-state and off-state currents.

The quasi-saturation (QS) effect in a power MOSFET has been discovered several decades ago. As the field has evolved and the dimensions in power MOSFETs have changed from tens of micrometers to submicrometer levels, and the gate geometry has evolved from planar to trench, the origin and the effect of the QS need to be re-assessed. This letter first discusses the origin of the QS effect in the state-of-the-art power MOSFETs and subsequently analyses the phenomenon of majority carrier injection (or diffusion) and its contribution to the increased carrier concentration in the drift region, specific to quasi-saturation.

In this article, we present a complementary metal-oxide semiconductor microelectromechanical system (CMOS MEMS) thermoelectronic flow sensor and discuss the advantages of employing anemometric and calorimetric transduction principles simultaneously. This readout concept exploits the fact that anemometric flow sensors take advantage of the maximum temperature generated within the device and, thus, are provided with the maximum flow sensitivity, while calorimetric flow sensors have the temperature sensing elements placed away from this maximum temperature region and, thus, are intrinsically less sensitive. At the same time, fluid flow direction discrimination in bidirectional flow sensors can be achieved by simply looking at the polarity of the differential signal coming from the temperature sensors placed aside the heating element. We also show that thermoelectronic flow sensors can benefit by having temperature sensors formed by an array of diodes to further enhance the device sensitivity. Although we apply these concepts to a sensor with a nonoptimum design and lacking any support electronics (e.g., filters, amplifiers, constant temperature driving circuitry, etc.), results are among the best ever reported in literature (including non-CMOS technologies), thus showing the high potential of our technology.

The physical mechanisms involved in the trapping and de-trapping processes associated with surface donor traps in gallium nitride (GaN) transistors are discussed in this paper. The paper challenges the conventional transient techniques adopted for extrapolating the trap energy level via experiments and TCAD simulations. Transient TCAD simulations were employed to reproduce the time-dependent electrical behavior of a metal-on-insulator field-effect transistor and explain the influence of the electric field and energy barrier on the transient time associated with the trapping and de-trapping mechanisms of surface traps. The comparison between three test structures and the relative variation of the trapping and de-trapping times with the bias and trap parameters leads to the suggestion of a proposed test structure and bias configuration to accurately extrapolate the energy level of surface traps in GaN transistors.

This research details the potential of a microhotplate photo sensor, based on a silicon-on-insulator (SOI) lateral PIN (P+/P–/N+) diode and a microheater, fabricated on a thin suspended membrane from a commercial 1.0-μm SOI complementary metal oxide semiconductor technology. A local annealing (30-min. microheating, at elevated temperature ∼250 °C) is directly carried out onto the suspended diode to optimize device characteristics (e.g., leakage current, output optical response), for device long-term stability and industrial application. The optical performances of such SOI lateral PIN diodes with four different backside reflectors placed below them are fully investigated. Under same incident illumination, four specific output photocurrents and responsivities are therefore obtained due to the varied light absorption in the active Si film. By combining the photodiodes responses with the four backside reflectors (i.e., gold, aluminum, silicon substrate, and black silicon), multiple-wavelength detection can be straightforwardly achieved within the 450–900-nm wavelength range, which makes the SOI photodiode highly promising in red-green-blue sensing, gas analyzing or plasma monitoring applications.

In this letter, we present the “anode-side” SuperJunction trench field stop+ IGBT concept with drift region SuperJunction pillars placed at the anode side of the structure rather than the cathode side. The extent of the pillars toward the cathode side is shown to pose a tradeoff between fabrication technology capabilities (and cost) versus the device performance, by extensive TCAD simulations. The proposed device structure simplifies the fabrication requirements by steering clear from the need to align the cathode side features with the SuperJunction pillars. It also provides an extra degree of freedom by decoupling the cathode design from the SuperJunction structure. Additionally, the presence of SuperJunction technology in the drift region of the “anode-side” SJ Trench FS+ IGBT results in 20% reduction of ON-state losses for the same switching energy losses or, up to 30% switching losses reduction for the same ON-state voltage drop, compared with a 1.2-kV breakdown rated conventional FS+ Trench IGBT device. The proposed structure also finds applications in reverse conducting IGBTs, where a reduced snapback can be achieved, and in MOS-controlled thyristor devices.

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both ${I}$ – ${V}$ and ${G}$ – ${V}$ characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: ${g}_{m}/{I}_{\text {d}}$ , ${g}_{m}/{g}_{ds}$ , ${f}_{T}$ and ${f}_{T}/{I}_{d}{V}_{d}$ , and their temperature dependence from 25 °C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to $40~\text {V}^{-1}$ , for currents lower than 10 nA/ $\mu \text{m}$ ; and 3) higher unity gain frequency per unit power for currents below 10 nA/ $\mu \text{m}$ .

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs).

Power semiconductor devices have been a mainstay of electron device technology since the introduction of the thyristor in the late 1950s. In the last six decades, electron devices and VLSI technology have gone through unprecedented changes. The state-of-the-art performance has progressed closely according to the famous Moore's Law, since it was introduced in 1965. The current techno-trend is the “More Than Moore” roadmap with emphasis on System in Package and 3-D integration. Over this period, we have witnessed device feature sizes shrinking from several microns in the 1970s to the 10-nm production-ready processes in 2017. At the same time, power semiconductor devices have also benefited significantly from these advancements.

This paper presents an extensive experimental study of the Seebeck coefficients in several conductive materials offered by standard CMOS technology when subject to a high temperature gradient. The measurements have been carried out on specific devices designed and fabricated in high-temperature SOI technology, comprising: one heating element, several thermopiles with different combinations of materials, and two highly sensitive, low leakage SOI diodes used to calibrate the absolute temperature in different points of the structure. To increase the accuracy, the chip characterization is performed in a controlled temperature chamber, with different values of the environmental temperature in the range 20 °C to 40 °C. This analysis leads to the extraction of the relative Seebeck coefficients for all thermocouples made with specific CMOS materials and, from that, the absolute values for the various materials at high temperature.

In this paper we present a thermal conductivity gas sensor with improved sensitivity by adding holes in the thin-film membrane. A numerical model is created and validated against the reference CMOS MEMS thermal conductivity sensor. The numerical model is used to investigate the advantages of having isolating holes through the membrane, located on either side of the heating resistor. These holes increase robustness and minimise catastrophic failure caused by pressure difference whilst simultaneously increasing sensitivity by enhancing convective interaction. The electro-thermal efficiency is shown to increase by 16% whilst the sensitivity to measuring percentage CO2 increases by 39.2%. It is also shown that increasing the width of the holes does not have significant effect on these sensitivities; thus, small holes can be incorporated, leaving room for multiple resistors across the membrane for different measuring techniques. This paper serves as proof that membrane holes can be used to optimise thermal conductivity sensors and will serve as a reference when these designs are fabricated and tested, leading to a new low-power, high-sensitivity gas sensor.

In this paper we present for the first time a Gallium Nitride-on-Silicon (GaN-on-Si) anenometric flow sensor based on a gold (Au) thermoresistive hot-wire. The device was fabricated in a custom GaN process, with an etching process to release a membrane made of the GaN stack. This membrane thermally isolates the hot-wire, increasing its thermal efficiency, which was measured to be 1.04°C/mW. Testing was performed at mass flow rates from 0-4 SLPM using a custom gas rig. The sensitivity of the device, driven in a constant current mode at 3 different zero-flow temperatures, was compared showing an increase in peak sensitivity of 67% at 250°C compared to 150°C.

We present a novel single-chip thermopile sensor array for mid-infrared room temperature imaging. The array is fabricated on a single complementary metal-oxide-semiconductor (CMOS) dielectric membrane, composed of single-crystal silicon (Si) p+ and n+ elements, and standard CMOS tungsten metal layers for thermopile cold junction heatsinking, significantly reducing the chip size and simplifying its processing. We demonstrate a 16×16 pixel device with 34 V/W responsivity and enhanced optical absorption in the 8–14 μm waveband, with a suitable performance for gesture recognition and people-counting applications. Our simple, low-cost sensor is an attractive on-chip array for a variety of applications in the mid-infrared spectral region.

International audience; A Wireless Sensor Network dedicated to Structural Health Monitoring applications in harsh environments, which is the basis for the design of a communicating reinforced concrete, is presented. An autonomous wirelessly powered and battery-free LoRaWAN Sensing Node is highlighted here. The presented system measures temperature and humidity from its environment and transmits the recovered data to a Communicating Node, which interconnects the physical and digital worlds whilst simultaneously powering the Sensing Nodes via a far-field Wireless Power Transmission interface.

The robustness of ultra-high voltage (>10kV) SiC IGBTs comprising of an optimized retrograde p-well is investigated. Under extensive TCAD simulations, we show that in addition to offering a robust control on threshold voltage and eliminating punch-through, the retrograde is highly effective in terms of reducing the stress on the gate oxide of ultra-high voltage SiC IGBTs. We show that a 10 kV SiC IGBT comprising of the retrograde p-well exhibits a much-reduced peak electric field in the gate oxide when compared with the counterpart comprising of a conventional p-well. Using an optimized retrograde p-well with depth as shallow as 1 µm, the peak electric field in the gate oxide of a 10kV rated SiC IGBT can be reduced to below 2 MV.cm−1, a prerequisite to achieve a high-degree of reliability in high-voltage power devices. We therefore propose that the retrograde p-well is highly promising for the development of>10kV SiC IGBTs.

The edge termination design strongly affects the ability of a power device to support the desired voltage and its reliable operation. In this paper we present three appropriate termination designs for 10kV n-IGBTs which achieve the desired blocking requirement without the need for deep and expensive implantations. Thus, they improve the ability to fabricate, minimise the cost and reduce the lattice damage due to the high implantation energy. The edge terminations presented are optimised both for achieving the widest immunity to dopant activation and to minimise the electric field at the oxide. Thus, they ensure the long-term reliability of the device. This work has shown that the optimum design for blocking voltage and widest dose window does not necessarily give the best design for reliability. Further, it has been shown that Hybrid Junction Termination Extension structure with Space Modulated Floating Field Rings can give the best result of very high termination efficiency, as high as 99%, the widest doping variation immunity and the lowest electric field in the oxide.

In this paper, we propose the use of a retrograde doping profile for the p-well for ultrahigh voltage (>uexcl;10 kV) SiC IGBTs. We show that the retrograde p-well effectively addresses the punchthrough issue, whereas offering a robust control over the gate threshold voltage. Both the punchthrough elimination and the gate threshold voltage control are crucial to high-voltage vertical IGBT architectures and are determined by the limits on the doping concentration and the depth that a conventional p-well implant can have. Without any punchthrough, a 10-kV SiC IGBT consisting of retrograde p-well yields gate threshold voltages in the range of 6–7 V with a gate oxide thickness of 100 nm. Gate oxide thickness is typically restricted to 50–60 nm in SiC IGBTs if a conventional p-well with $1 \times 10^{17}$ cm−3 is utilized. We further show that the optimized retrograde p-well offers the most optimum switching performance. We propose that such an effective retrograde p-well, which requires low-energy shallow implants and thus key to minimize processing challenges and device development cost, is highly promising for the ultrahigh-voltage (>10 kV) SiC IGBT technology.

In this paper, 2-Dimensional and 3-Dimensional numerical models of a thermal flow sensor are discussed and compared against one another whilst being validated with experimental results. The models involve and couple three physics domains: electric, computational fluid dynamics and heat transfer. A comparative analysis has been performed focusing on the relative merits. Despite being less accurate, it is shown that 2D simulations can be used to portray device behavior whilst minimizing required computational resources whereas 3D models are needed to attain more accurate quantitative data. This ultimately provides the knowledge for objective driven modelling decisions.

This paper investigates the differences between thermo-resistive and thermo-electronic flow sensors across 5 SOI CMOS designs. The two transduction principles (hot wire and thermo-diode) are both embedded within the same sensor, allowing for the first time, a fair and complete comparison. Results show that with the reduction in sensor size, the sensitivity and accuracy of thermo-resistive methods becomes worse. The thermo-electronic sensitivity is less significantly affected and the accuracy is unaffected by sensor and heater size. The length of the diode has been found to affect the non-linearity of the electro-thermal properties due to relative significance of current leakage. However, a shorter diode showed 50 % higher accuracy due to it measuring an average higher temperature. This paper can be used as a design tool for those choosing transduction methods within their sensors.

The introduction of the superjunction has challenged the well-known limit of silicon. In spite of its widespread use, and despite its correct application in classical power MOSFETs, Baliga's figure of merit no longer can be used to give an accurate picture of the material potential in power electronics. Fujihira has updated both the static and dynamic figures of merit, but, as the cell pitch of the SJ scale down, these figure of merits need to include the parasitic JFET effect and an analytical formulation of the gate-drain capacitance and its intricate dependence on the drain voltage. This work presents for the first-time new static and dynamic figure of merits which take into account the spectacular advances in the SJ technology, where the cell dimensions are approaching the sub-micrometer level.

State of the art TCAD simulation models are used to simulate the performance of ultra-high voltage (10-20 kV) SiC IGBTs in the temperature range 300–775 K. We show that unlike Si-based counterparts, ultra-high voltage SiC IGBTs stand to gain from the temperature rise if the limit is not exceeded. We show that whilst an operation at 375 K is highly promising to achieve the most optimum on-state characteristics from $S$ iC IGBTs, no significant degradation in the on-state current and breakdown voltage alongside with negligible rise in leakage current is observed until 550 K. Therefore, ≥10 kV SiC IGBTs are highly promising for Smart Grid and HVDC.

Minimizing conductive heat losses in Micro-Electro-Mechanical-Systems (MEMS) thermal (hot-film) flow sensors is the key to minimize the sensors&rsquo, power consumption and maximize their sensitivity. Through a comprehensive review of literature on MEMS thermal (calorimetric, time of flight, hot-film/hot-film) flow sensors published during the last two decades, we establish that for curtailing conductive heat losses in the sensors, researchers have either used low thermal conductivity substrate materials or, as a more effective solution, created low thermal conductivity membranes under the heaters/hot-films. However, no systematic experimental study exists that investigates the effect of membrane shape, membrane size, heater/hot-film length and M e m b r a n e (size) to H e a t e r (hot-film length) Ratio (MHR) on sensors&rsquo, conductive heat losses. Therefore, in this paper we have provided experimental evidence of dependence of conductive heat losses in membrane based MEMS hot-film flow sensors on MHR by using eight MEMS hot-film flow sensors, fabricated in a 1 &micro, m silicon-on-insulator (SOI) CMOS foundry, that are thermally isolated by square and circular membranes. Experimental results demonstrate that: (a) thermal resistance of both square and circular membrane hot-film sensors increases with increasing MHR, and (b) conduction losses in square membrane based hot-film flow sensors are lower than the sensors having circular membrane. The difference (or gain) in thermal resistance of square membrane hot-film flow sensors viz-a-viz the sensors on circular membrane, however, decreases with increasing MHR. At MHR = 2, this difference is 5.2%, which reduces to 3.0% and 2.6% at MHR = 3 and MHR = 4, respectively. The study establishes that for membrane based SOI CMOS MEMS hot-film sensors, the optimum MHR is 3.35 for square membranes and 3.30 for circular membranes, beyond which the gain in sensors&rsquo, thermal efficiency (thermal resistance) is not economical due to the associated sharp increase in the sensors&rsquo, (membrane) size, which makes sensors more expensive as well as fragile. This paper hence, provides a key guideline to MEMS researchers for designing the square and circular membranes-supported micro-machined thermal (hot-film) flow sensors that are thermally most-efficient, mechanically robust and economically viable.

This paper summarizes the outcome of the EC FP7 project MSP - Multi Sensor Platform for Smart Building Management (Grant Agreement No. 611887). The MSP consortium comprising 17 partners from 6 European countries developed a full manufacturing chain for 3D system integration, which has never been realized before. It enables 3D-integration of highly sophisticated components and sensor devices on a CMOS electronic platform chip. The final multi-sensor system comprises a variety of gas sensors as well as optical sensors for ultraviolet, visible and infrared light. The MSP demonstrator system implemented in a wearable wristband device integrates a total of 57 sensors - this is a worldwide unique sensor system.

GaN-on-Si is a lateral technology and as such it allows the integration of high voltage High Electron Mobility Transistors and low voltage devices on the same chip, thus enabling the miniaturization and reduction of parasitic inductances. Due to the fact that integrated devices share a common substrate, the performance of one device can be significantly affected by the operation of another. The choice of the substrate bias is particularly important in the integrated half-bridge, a popular topology which includes a low- and a high-side device. A grounded substrate will cause vertical stress on the high-side device, while a floating substrate will couple with the high voltage, resulting in stress on the low-side device. This is highly problematic as the devices may fail to turn on or have a significantly increased RON. In this work, we carefully investigate the substrate coupling of a high-side and low-side device via backgating measurements. We demonstrate that the unwanted RON increase in the high side device could be suppressed by hole injection from the gate, if the gate is formed of a p-type material.

In this paper we review a range of microsensors based on a common CMOS platform technology. The technology features a CMOS core which includes high temperature tungsten metallization and a post-CMOS deep reactive ion etching step of the substrate to release membranes, where the sensing elements are embedded. In one single process we were able to accommodate a variety of sensors such as gas, humidity, pressure, flow, temperature and infra-red detectors and emitters. The benefits of this platform are: (i) ultra-low power consumption, (ii) small form factor, (iii) high reliability and yield (iv) possibility of on-chip electronics and last but not least (v) low unit price.