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Website Fingerprinting attacks aim to track the visited websites in browsers and infer confidential information about users. Several studies showed that recent advancements in Machine Learning (ML) and Deep Learning (DL) algorithms made it possible to implement website fingerprinting attacks even though various defense techniques are present in the network. Nevertheless, trained models for website detection are not analyzed deeply to identify the leakage sources which are not always visible to both attackers and Cyber Threat Intelligence engineers. This study focuses on explaining ML and DL models in the context of microarchitecture-based website fingerprinting attacks. In the attack model, performance counters and cache occupancy side-channels are implemented on Google Chrome and Tor browsers. After ML and DL models are trained, LIME and saliency map XAI methods are applied to examine the leakage points in the side-channel data. In order to match the leakage samples in the measurements to the network traces, a novel dataset is collected by utilizing Google Chrome and Firefox browser developer tools. Next, the efficiency of explainable methods are analyzed with XAI metrics. Finally, an XAI-based obfuscation defense technique is proposed as a countermeasure against microarchitecture-based website fingerprinting attacks

Metamaterials refer to a class of artificial composite structures with supernormal physical properties that natural materials do not have. The emergence of metamaterials has opened up new research directions for classical electromagnetic theory and made it possible to manipulate electromagnetic waves effectively. One of most important applications of metamaterials is metamaterial absorbers (MMAs). The properties of MMAs depend on the material composition, cell size and structure, which could often achieve "perfect" absorption through reasonable design. This review starts with the development of MMAs and describes the status of this absorber, then mainly focuses on bionic design and new artificial design. Specifically, it is to draw inspiration from natural plants and animals, design novel structures to get better absorbing properties. Furthermore, the artificial design can achieve the optimize absorption capacity as well as absorption bandwidth. What's more, this review summarizes the 3D printing technology to prepare MMAs that are different from traditional printed circuit board technology. The MMAs produced by 3D printing technology can prepare more complex shapes, and has light weight and better absorbing properties.

The bottleneck between the processor and memory is the most significant barrier to the ongoing development of efficient processing systems. Therefore, a research effort begun to shift from processor-centric architectures to memory-centric architectures. Various in-memory processor architectures have been proposed to break this barrier to pave the way for ever-demanding memory-bound applications. Associative in-memory processing is a successful candidate for truly in-memory computing, in which processor and memory are combined in the same location to eliminate the expensive data access costs. The architecture exhibits an unmatched advantage for data-intensive applications due to its memory-centric design principles. On the other hand, this advantage can be revealed fully by an efficient design methodology. This study puts further progressive effort by proposing a hardware/software design methodology for associative in-memory processors. The methodology aims to decrease energy consumption and area requirement of the processor architecture specifically programmed to perform a given task. According to the evaluation of nine different benchmarks, such as fast Fourier transform and multiply-accumulate, the proposed design flow accomplishes an average 7% reduction in memory area and 18% savings in total energy consumption.

This brief presents an event-driven spiking multi-kernel convolution architecture for processing address-event representation (AER) streams from dynamic vision sensor (DVS) chips. The processor architecture is designed based on leaky integrate-and-fire (LIF) neural model, and employs pipeline scheme to accelerate data processing. A new scheme for arranging neuron membrane potentials and kernels in memories is proposed, which enables row-by-row kernel processing and accelerates the multi-kernel convolution computation. An FPGA prototype of the proposed architecture is implemented on a Xilinx Zynq FPGA development board with 100 MHz clock frequency. The proposed processor architecture computes 64 filters with configurable kernel size (from 1x1 to 32x32) on input flow, obtaining the latency of 0.10 us to 10.33 us for convoluting an event, and the energy of 0.12 nJ and 12.08 nJ per event per convolution, respectively.

The rapid increase of recent privacy attacks has significantly decreased trust on behalf of the users. A root cause to these problems is that modern computer architectures have always been designed for performance, while security protections are traditionally addressed reactively. Practical security protections, such as Intel SGX, rely on processing unencrypted data in the architectural state, which leaves them exposed to software attacks (e.g., SGXpectre). This work revisits the traditional computation stack and introduces a novel computation paradigm, where data is never decrypted in the architectural state. Through our architecture, data are protected with symmetric or asymmetric encryption and the programmer manipulates them directly in the encrypted domain. To increase performance, we exploit data locality by introducing decryption caches in the microarchitectural state. Our proposal addresses all abstraction levels in the computation stack: from microarchitecture to library support for high-level programming. The proposed architecture is instantiated through new assembly instructions, registers and functional units operating on large integers. In our evaluation, we extend the OpenRISC 1000 architecture and develop open-source libraries for C++. As a case study, we employ data-oblivious benchmarks and observe that for benchmarks with high temporal locality, our architecture can achieve comparable performance to processing unencrypted data.

Osteonecrosis of the femoral head (ONFH) is a recalcitrant ischemic disorder, which could be classified into two major categories: traumatic and nontraumatic. Regardless of different risk factors, it has been testified that ONFH results from primitive vascular problems, leading to temporary or permanent loss of blood supply to bone tissue. Histopathological and microarchitectural alterations ensues, which is a gradual evolutionary process involving bone marrow and osteocyte necrosis, progressive destruction of subchondral bone, unsuccessful reparative process, and eventual articular collapse and degenerative arthritis. Based on the imaging features of ONFH, different classification systems have been developed to evaluate the severity and prognosis of the disease, which is pivotal for implementation of treatment strategy, especially the joint-preserving surgery. However, patients classified with the same severity stage, especially in the peri-collapse stage, sometimes responded differently after similar joint-preserving surgery. The unusual phenomenon may be attributed to the limitation of the current imaging classification systems, which might underestimate the disease severity, especially when referring to the early stages. In this review, we briefly summarize the etiology and pathogenesis of ONFH. The imaging features and staging classification systems of ONFH are also described. More importantly, we focus on histopathological and microstructural alterations of the femoral head, and provide an overview of their essential contribution to ONFH progression. Given the observation of discordance between imaging characteristics and histopathological alterations, a substantial amount of research on the relationship between imaging and histopathological features is required to further modify and revise the current wide-accepted classification systems.

Presilicon modeling is a crucial and integral part of processor microarchitecture definition and optimization. In this article, I attempt to provide a retrospective view of IBM's POWER and PowerPC microprocessors, through the lens of someone who has been associated with such modeling in support of microarchitecture definition and optimization from the earliest days of this particular family of processors. The focus in the early/mid-1980s was on cycle-accurate performance modeling; much later, beginning in 1999 or so, the looming power wall triggered a new era of power-performance modeling at the microarchitecture level. Subsequently, temperature-aware and reliability-aware modeling were added dimensions that CMOS technology evolution drove us into. The problem of model validation is an unavoidable aspect of presilicon modeling. Without that mindset, the microarchitecture definition team can make serious mistakes, which results in unpleasant postsilicon surprises. I provide pointers to early approaches in addressing this issue. The article attempts to mention the contributions of many talented researchers and engineers that have, over the years, contributed immensely to the evolution of the POWER/PowerPC microprocessors from earliest research concepts through the recently announced POWER10—using model-based analysis to ensure competitive performance growth.

It was a different computing world in the late 1980s. Many if not most researchers in the computer architecture area had become convinced that complex instruction sets such as the Intel x86 were doomed in light of the many advantages promised by reduced instruction set architecture publications. There were many voices within Intel urging upper management to abandon x86 and get started on some alternative. Even engineers who had worked on Intel's then-flagship 486 were expressing serious reservations about whether the x86 architecture could be “dragged further up the hill” to be, if not directly competitive with emerging RISC designs, at least close enough for x86 to remain profitable.

Modern microprocessors contain several special function units (SFUs) such as specialized arithmetic units, cryptographic processors, etc. In recent times, applications such as cloud computing, web-based search engines, and network applications are widely used, and place new demands on the microprocessor. Hashing is a key algorithm that is extensively used in such applications. Hashing can reduce the complexity of search and lookup from O( $N$ N ) to O( $N/n$ N / n ), where $n$ n bins are used. Hashing is typically performed in software. Thus, implementing a hardware-based hash unit on a modern microprocessor would potentially increase performance significantly. In this article, we propose a novel hardware hash unit (HU) design for use in modern microprocessors, at the microarchitecture level and at the circuit level. First, we present the design of the HU at the microarchitecture level. We simulate the HU to compare its performance with a software-based hash implementation. We demonstrate a significant speedup (up to 15×) for the HU. Furthermore, the performance scales elegantly with increasing database size and application diversity, without increasing the hardware cost. Second, we present the circuit design of the HU for use in modern microprocessors, using a 45nm technology. Our proposed hardware hash unit is based on the use of a content-addressable memory (CAM) to implement each bin of the hash table. We simulate the HU circuit and compare it with a traditional CAM design. We demonstrate an average power reduction of 5.48× using the HU over the traditional CAM. Also, we show that the HU can operate at a maximum frequency of 1.39 $GHz$ G H z (after accounting for process, voltage and temperature (PVT) variations and accounting for wiring parasitics). Furthermore, we present the delay, power and area trade-offs of the HU design with varying hash table sizes.

Kunpeng 920 is the second generation server processor designed by HiSilicon based on ARM architecture. Kunpeng 920 is able to achieve cost efficiency for various workloads through using a variety of chiplets and hybrid process technologies. The unique recomposition(s) of these flexible chipsets allows new designs to be created. The Kunpeng series processors combine technology innovations from various levels to improve efficiency, eliminate bottlenecks, and deliver value and performance. Its key features are as follows: The Kunpeng 920 core is specifically designed with superscalar architecture with the support of vector extension to provide leading features for high-performance computing applications; the coherent cache subsystem is created to integrate multicores into single chiplet (e.g., 7-nm process node) with a ring design that is ultralow-latency (

This brief presents a neuromorphic processor with asynchronous routers and configurable LIF neuron models. The neurocore microarchitecture revolves around a high- $V_{th}$ SRAM to reduce leakage, alongside reconfigurable neuron compute logic circuits and async routers to maximize energy efficiency. The neuron compute module achieves low power via an area efficient ALU implementation by using only adder and bitshifter circuits. We describe this LIF neuron model ALU design, and also include key neurocore verification scenarios (i.e., router deadlocks and functional coverage), CPU-neurocore control flow, and asynchronous router performance analysis. Our 16-core fabricated chip in 40 nm CMOS process works down to 0.5V. The measured leakage and average energy efficiency are $0.93~\mu \text{W}$ /core and 4.8 pJ/SOP respectively (at 0.5V), which is 20% better than state of the art.

Quantum computing systems are developing rapidly as powerful solvers for a variety of real-world calculations. Traditionally, many of these same applications are solved using conventional high-performance computing (HPC) systems, which have progressed sharply through decades of hardware and software improvements. Here, we present a perspective on the motivations and challenges of pairing quantum computing systems with modern HPC infrastructure. We outline considerations and requirements for the use cases, macroarchitecture, microarchitecture, and programming models needed to integrate near-term quantum computers with HPC system, and we conclude with the expectation that such efforts are well within reach of current technology.

Individuals with diabetes mellitus type 2 (T2DM) have an increased risk of hip fracture, especially if vascular complications are present. However, microstructural origins of increased bone fragility in T2DM are still controversial. DXA measurement of the contralateral hip and three-dimensional microCT analyses of femoral neck trabecular microarchitecture were performed in 32 individuals (26 women and 6 men, 78 ± 7 years). The specimens were divided to two groups: T2DM individuals with hip fracture (DMFx, n = 18) and healthy controls (CTL, n = 14). DMFx group consisted of individuals with vascular complications (DMFx_VD, n = 8) and those without vascular complications (DMFx_NVD, n = 10). T-score was significantly lower in DMFx_VD and DMFx_NVD than in controls (p

An online template attack (OTA) is a powerful technique previously used to attack elliptic curve scalar multiplication algorithms. This attack has only been analyzed in the realm of power consumption and EM side channels, where the signals leak related to the value being processed. However, microarchitecture signals have no such feature, invalidating some assumptions from previous OTA works. In this paper, we revisit previous OTA descriptions, proposing a generic framework and evaluation metrics for any side-channel signal. Our analysis reveals OTA features not previously considered, increasing its application scenarios and requiring a fresh countermeasure analysis to prevent it. In this regard, we demonstrate that OTAs can work in the backward direction, allowing to mount an augmented projective coordinates attack with respect to the proposal by Naccache, Smart and Stern (Eurocrypt 2004). This demonstrates that randomizing the initial targeted algorithm state does not prevent the attack as believed in previous works. We analyze three libraries libgcrypt, mbedTLS, and wolfSSL using two microarchitecture side channels. For the libgcrypt case, we target its EdDSA implementation using Curve25519 twist curve. We obtain similar results for mbedTLS and wolfSSL with curve secp256r1. For each library, we execute extensive attack instances that are able to recover the complete scalar in all cases using a single trace. This work demonstrates that microarchitecture online template attacks are also very powerful in this scenario, recovering secret information without knowing a leakage model. This highlights the importance of developing secure-by-default implementations, instead of fix-on-demand ones. publishedVersion

This letter reveals that performing microarchitecture-dependent, or microarchitecture-independent, or ISA-independent workload characterization alone will lead to misleading or even erroneous conclusions. We present a whole-picture workload characterization (in short, WPC) methodology and the tool. WPC integrates microarchitecture-dependent, microarchitecture-independent, and ISA-independent characterization methodologies. It performs a whole-picture analysis on hierarchical profile data across Intermediate Representation (IR), ISA, and microarchitecture to sum up the inherent workload characteristics and understand the reasons behind the numbers. We contradict an influential observation using the WPC tool: having higher front-end stalls is an intrinsic characteristic of scale-out workloads. Our experiments show collecting microarchitecture metrics at only one level without understanding the reason behind the numbers might lead to erroneous conclusions. We open-source the WPC tool from the project homepage https://www.benchcouncil.org/WPC .

The design of specialized architectures for accelerating the inference procedure of Deep Neural Networks (DNNs) is a booming area of research nowadays. While first-generation rigid accelerator proposals used simple fixed dataflows tailored for dense DNNs, more recent architectures have argued for flexibility to efficiently support a wide variety of layer types, dimensions, and sparsity. As the complexity of these accelerators grows, the analytical models currently being used prove unable to capture execution-time subtleties, thus resulting inexact in many cases. We present STONNE ( S imulation TO ol of N eural N etwork E ngines ), a cycle-level microarchitectural simulator for state-of-the-art rigid and flexible DNN inference accelerators that can plug into any high-level DNN framework as an accelerator device, and perform full-model evaluation of both dense and sparse real, unmodified DNN models.

Hardware data prefetching is a latency hiding technique that mitigates the memory wall problem by fetching data blocks into caches before the processor demands them. For high performing state-of-the-art data prefetchers, this increases dynamic and static energy in memory hierarchy, due to increase in number of requests. A trivial way to improve energy-efficiency of hardware prefetchers is to prefetch instructions on the critical path of execution. As criticality-based data prefetching does not degrade performance significantly; this is an ideal approach to solve the energy-efficiency problem. We discuss limitations of existing critical instruction detection techniques and propose a new technique that uses re-order buffer occupancy as a metric to detect critical instructions and performs prefetcher-specific threshold tuning. With our detector, we achieve maximum memory hierarchy energy savings of 12.3% with 1.4% higher performance, for PPF, and average as follows: (i) SPEC CPU 2017 benchmarks: 2.04% lower energy, 0.3% lower performance, for IPCP at L1D, (ii) client/server benchmarks: 4.7% lower energy, 0.15% lower performance, for PPF, (iii) Cloudsuite benchmarks: 2.99% lower energy, 0.36% higher performance, for IPCP at L1D. IPCP and PPF are state-of-the-art data prefetchers.

The risk of fracture is increased in both type 1 diabetes mellitus (T1DM) and type 2 diabetes mellitus (T2DM). However, in contrast to the former, patients with T2DM usually possess higher bone mineral density. Thus, there is a considerable difference in the pathophysiological basis of poor bone health between the two types of diabetes. Impaired bone strength due to poor bone microarchitecture and low bone turnover along with increased risk of fall are among the major factors behind elevated fracture risk. Moreover, some antidiabetic medications further enhance the fragility of the bone. On the other hand, antiosteoporosis medications can affect the glucose homeostasis in these patients. It is also difficult to predict the fracture risk in these patients because conventional tools such as bone mineral density and Fracture Risk Assessment Tool score assessment can underestimate the risk. Evidence-based recommendations for risk evaluation and management of poor bone health in diabetes are sparse in the literature. With the advancement in imaging technology, newer modalities are available to evaluate the bone quality and risk assessment in patients with diabetes. The purpose of this review is to explore the pathophysiology behind poor bone health in diabetic patients. Approach to the fracture risk evaluation in both T1DM and T2DM as well as the pragmatic use and efficacy of the available treatment options have been discussed in depth.

A self‐timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing‐driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low‐power self‐timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing‐driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing‐driven synthesis and static timing analysis. Finally, two 32‐bit RISC‐V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock‐gating and SynV without clock‐gating.

Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture which is capable of achieving these requirements. The micro-architecture is based on RISC-V Instruction Set Architecture (ISA). The core is implemented and verified on Xilinx Virtex-7 FPGA board with a resource requirement of 7617 LUTs and 2319 FFs. This core could achieve a Dhrystone benchmark score of 1.71 DMIPS per MHz which is higher than ARM Cortex-M3 (1.50 DMIPS per MHz) and ARM Cortex-M4 (1.52 DMIPS per MHz). The Coremark benchmark is also tested on this core and it gives 4.13 Coremark per MHz. The physical design result of the core using commercial tools shows that it can achieve a maximum frequency of 198.02 MHz with 0.036 mm2 area and $17.36~\mu \text{W}$ /MHz power requirement at UMC 40 nm technology node. The core consumes a dynamic power of $19.75~\mu \text{W}$ /MHz at UMC 90nm which is 36% and 40% better than ARM Cortex-M3 and Cortex-M4 respectively and also lower than many others cores. The results show that this core can outperform many existing commercial and open-source cores.

Protecting programs against hardware fault injection requires accurate software fault models. However, typical models, such as the instruction skip, do not take into account the microarchitecture specificities of a processor. We propose in this article an approach to study the relation between faults at the Register Transfer Level (RTL) and faults at the software level. The goal is twofold: accurately model RTL faults at the software level and materialize software fault models to actual RTL injections. These goals lead to a better understanding of a system's security against hardware fault injection, which is important to design effective and cost-efficient countermeasures. Our approach is based on the comparison between results from RTL simulations and software injections (using a program mutation tool). Various analyses are included in this article to give insight on the relevance of software fault models, such as the computation of a coverage and fidelity metric, and to link software fault models to hardware RTL descriptions. These analyses are applied on various single-bit and multiple-bit injection campaigns to study the faulty behaviors of a RISC-V processor.

Cryogenic computing can achieve high performance and power efficiency by dramatically reducing the device’s leakage power and wire resistance at low temperatures. Recent advances in cryogenic computing focus on developing cryogenic-optimal cache and memory devices to overcome memory capacity, latency, and power walls. However, little research has been conducted to develop a cryogenic-optimal core architecture even with its high potentials in performance, power, and area efficiency. In this article, we first develop CryoCore-Model, a cryogenic processor modeling framework that can accurately estimate the maximum clock frequency of processor models running at 77 K. Next, driven by the modeling tool, we design CryoCore, a 77 K-optimal core microarchitecture to maximize the core’s performance and area efficiency while minimizing the cooling cost. The proposed cryogenic processor architecture, in this article, achieves the large performance improvement and power reduction and, thus, contributes to the future of high-performance and power-efficient computer systems.

Scalable server-grade nonvolatile RAM (NVRAM) DIMMs are commercially available with the release of Intel’s Optane DIMM. Recent studies on Optane DIMM-based systems unveil discrepant performance characteristics, compared with what many researchers thought before the product release. To thoroughly analyze the source of the discrepancy and facilitate real-NVRAM-aware system design, we develop an NVRAM microarchitecture characterization and modeling framework, consisting of a Low-level profilEr for Non-volatile memory Systems (LENS) and a Validated cycle-Accurate NVRAM Simulator (VANS). LENS allows users to comprehensively analyze NVRAM performance attributes and reverse engineer NVRAM microarchitectures. We use LENS to reverse engineer the sophisticated microarchitecture design of Optane DIMM and generate a set of architecture implications of industrial NVRAMs. VANS models Optane DIMM microarchitecture and is validated by comparing with the detailed performance characteristics of Optane DIMM-attached servers. VANS adopts a modular design that can be easily modified to extend to other NVRAM architecture designs.

The microprocessor revolution, of which this issue marks the 50th anniversary, drove remarkable innovations in instruction set architecture, microarchitecture, and system design, some of which continue to evolve in current research and commercial products. Many of these features were indeed new, but others have their roots in a line of processor architectures that predates this revolution and that, alone among those ancient species, continues to thrive in modern information technology (IT) world: the IBM mainframe, launched in 1964 as S/360 and now continuing as IBM Z. This article will briefly describe some of the “modern” features that were pioneered there, then recount how the mainframe made the transition into the complementary metal–oxide–semiconductor (CMOS) microprocessor world.

Background Patients with rheumatoid arthritis (RA) are at increased risk of fractures. Although their decline in bone mineral density (BMD) is well-established, data regarding the alterations in bone microarchitecture are limited. In this study, we aimed to evaluate bone microarchitecture, geometry, and volumetric BMD among patients with RA in mainland China using high-resolution peripheral quantitative computed tomography (HRpQCT). Methods In this cross-sectional study, patients with RA were recruited from the Peking Union Medical College Hospital site of the Chinese Registry of rhEumatoiD arthrITis (CREDIT). Each participant underwent HRpQCT scanning (Scanco XtremeCT II), thoracolumbar X-ray and dual-energy X-ray absorptiometry. The primary outcomes were HRpQCT-related measures at distal radius and tibia. Data regarding demographic features, RA-related characteristics, and history of fragility fractures were collected. Correlation between HRpQCT parameters and potentially related factors were analyzed using linear regression analysis. A group of age- and sex-matched healthy controls was included for comparison. Results A total of 81 patients with RA [69 women, aged 57.9 ± 8.7 years, disease duration 5.7 (IQR 1.4–11.2) years] and 81 matched healthy controls were included. Compared with controls, patients with RA had significantly larger bone area and lower total and trabecular vBMD at both the distal radius and tibia. Lower cortical bone thickness was also shown at the distal tibia. Among patients with RA, advanced age, low BMI, female sex, disease duration, and activity were associated with decreased vBMD and impaired bone microstructure. Female reproductive factors including menopause, late menarche, breast feeding, and early childbirth also showed negative correlation with these parameters. Compared to patients with RA without fractures, patients with fragility fractures (n = 11) showed lower trabecular and cortical vBMD, thinner cortical bone, impaired trabecular microstructure, and a trend of declined bone strength. Current glucocorticoid intake was related to decreased vBMD, trabecular number, increased trabecular separation, and inhomogeneity. Conclusions In this study, we observed alterations in bone mineral density, geometry, and microarchitecture among patients with RA compared to healthy individuals, which may impair bone strength and lead to increased risk of fractures. Both traditional risk factors for osteoporosis and RA-associated factors need to be considered in the assessment of the bone quality.

In typical embedded applications, the precise execution time of the program does not matter, and it is sufficient to meet a real-time deadline. However, modern applications in information security have become much more time-sensitive, due to the risk of timing side-channel leakage. The timing of such programs needs to be data-independent and precise. We describe a parallel synchronous software model, which executes as N parallel threads on a processor with word-length N. Each thread is a single-bit synchronous machine with precise, contention-free timing, while each of the N threads still executes as an independent machine. The resulting software supports fine-grained parallel execution. In contrast to earlier work to obtain precise and repeatable timing in software, our solution does not require modifications to the processor architecture nor specialized instruction scheduling techniques. In addition, all threads run in parallel and without contention, which eliminates the problem of thread scheduling. We use hardware (HDL) semantics to describe a thread as a single-bit synchronous machine. Using logic synthesis and code generation, we derive a parallel synchronous implementation of this design. We illustrate the synchronous parallel programming model with practical examples from cryptography and other applications with precise timing requirements., Comment: Accepted in IEEE Embedded Systems Letters

When deploying deep neural networks (DNNs) onto deep learning processors, we usually exploit mixed-precision quantization and voltage–frequency scaling to make tradeoffs among accuracy, latency, and energy. Conventional methods usually determine the quantization–voltage–frequency (QVF) policy before DNNs are deployed onto local devices. However, they are difficult to make optimal customizations for local user scenarios. In this article, we solve the problem by enabling on-device QVF tuning with a new deep learning processor architecture Evolver. Evolver has a QVF tuning mode to deploy DNNs with local customizations before normal execution. In this mode, Evolver uses reinforcement learning to search the optimal QVF policy based on direct hardware feedbacks from the chip itself. After that, Evolver runs the newly quantized DNN inference under the searched voltage and frequency. To improve the performance and energy efficiency of both training and inference, we introduce bidirectional speculation and runtime reconfiguration techniques into the architecture. To the best of our knowledge, Evolver is the first deep learning processor that utilizes on-device QVF tuning to achieve both customized and optimal DNN deployment.

in this article, a Reconfigurable Microarchi- tecture-based PMDC prototype is developed with the help of dynamic pipeline stages. The Reconfigurable Microarchitecture is intended for the Internet of Things (IoT) edge level computing utilization purposes. This microarchitecture is implemented using a reconfigurable computing system with the help of an FPGA board. The reconfigurable microarchitecture is used as a feedback circuit of the PMDC motor to come out with a developed speed control prototype that can be sufficiently integrated with IoT technology. The number of pipeline stages will dynamically change as per user speed requirements. Several methods of speed measurement are tested using different pipeline structures to find out an appropriate method for the IoT edge level. Resource utilization, throughput and latency for those methods are analyzed. Additionally, the reconfigurable microarchitecture gives dynamic power consumption which more suitable for IoT edge level computations. The Real-Time behavior of the developed prototype is carried out with a pseudo-random binary sequence (PRBS) test for its system identification, a particle swarm optimization (PSO) technique for its optimal controller design and edge level computations for its IoT integration procedure.

Rowhammer is a destructive software-induced DRAM fault, which an attacker can leverage to break system security. Both individual customers and enterprise users (e.g., cloud providers) might refrain from using a computing system if it is vulnerable to rowhammer vulnerability. In this paper, we provide the first end-to-end tool, coined BitMine, that systematically assesses a DRAM chip’s vulnerability to rowhammer bit flips. BitMine is an extension of DRAMDig. As DRAM address mappings are proprietary techniques and critical in inducing rowhammer bit flips, DRAMDig, our prior work, leverages domain knowledge to efficiently and deterministically reverse-engineer DRAM address mappings on Intel machines. By incorporating DRAMDig, BitMine configures three key parameters, i.e., hammer methods , hammer patterns , data patterns , on the effectiveness of finding rowhammer bit flips. BitMine by default implements 13 hammer methods, 4 hammer patterns and 16 data patterns and is extensible to support more. We evaluate DRAMDig and BitMine against multiple machine models that combine different DRAM chips and Intel microarchitectures. Our experiment results show that DRAMDig efficiently uncovers a deterministic DRAM address mapping for each machine model, and every implemented parameter in BitMine has its distinct effectiveness in triggering bit flips for different machine models.

This article proposes reconfigurable maximum a posteriori (MAP) decoding algorithm which operates in multiple radix modes to hard decode the information bits with variable throughput by consuming constant power. Subsequently, a new digital decoder-architecture for this MAP decoding algorithm has been designed that operates in radix-2/4/8 modes. Furthermore, reconfigurable microarchitectures of state-metric and logarithmic-likelihood-ratio (LLR) computation units are presented in this article. Performance analyses of the proposed algorithm have been performed in additive-white Gaussian-noise (AWGN) channel environment where it achieved a bit-error-rate (BER) of 10−4 at a signal-to-noise ratio (SNR) of 5 dB. Suggested multiple-radix MAP-decoder is fabricated in united-microelectronics-corporation (UMC) 130-nm-CMOS technology node and it occupies die and core areas of 2.35 and 1.28 mm2, respectively, operating at a maximum clock frequency of 204 MHz. This MAP decoder ASIC-chip delivers throughputs of 201, 403, and 605 Mb/s while operating in radix-2, 4 and 8 modes, respectively, consuming a total power of 92 mW. Our chip achieves 0.15 nJ/bit of energy efficiency, which is 30% better than the most energy-efficient implementation from literature. Likewise, it delivers 39% higher throughput and $70\times $ better area-efficiency than the state-of-the-art work.

This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes ( ${m}$ OISC), capable of running at a reasonable performance level to enable basic usability in microcontroller applications. The purpose of ${m}$ OISC is to enable simple data transfer tasks and run small programs while maintaining ultimate simplicity. We present the internal organization for a computer architecture including an 8bit I/O register, and 64kB central Random Access Memory (RAM), organized in two-bytes words. The processor can run code generated assuming an OISC or a Complex Instruction Set Computer (CISC) scheme (op-code based), depending on the programmer’s demands and based on the initial setting of a register during start-up. To enable practical applications and demonstrate successful exploitation of ${m}$ OISC in view of integration in a compiler back-end, we designed a custom Proof-of-Concept (PoC) software design toolchain based on LLVM and clang. Although not targeting all the features of commercial ISA, the toolchain is capable of compiling C code from LLVM intermediate representation or generating ${m}$ OISC code translated from ARM, x86, RISC-V, and MIPS assembly. The toolchain also enables practical Value Change Dump (VCD) simulations output with graphical plots of the CPU state and associated symbols. A PoC microcontroller system has been synthesized in a low power Field Programmable Gate Array (FPGA) and verified in a basic wireless telemetry application including a Synchronous Peripheral Interface (SPI) RFM9x Long RAnge (LoRA) transceiver and a MAX30205 Inter Integrated Circuit (I2C) temperature sensor, using its 8bit I/O port, with software bus interface implementation. ${m}$ OISC occupies ~6% of resources on a Cyclone 10LP FPGA, for 1397 Adaptive Look-Up Tables (ALUTs) and 461 dedicated logic registers. The measured dynamic current consumption of the complete FPGA board with synthesized ${m}$ OISC is 12mA at 100MHz clock.

Side-channel attacks are one of the greatest practical threats to security-related applications, because they are capable of breaking ciphers that are assumed to be mathematically secure. Lots of studies have been devoted to power or electro-magnetic (EM) analysis against desktop CPUs, mobile CPUs (including ARM, MSP, AVR, etc) and FPGAs, but rarely targeted modern GPUs. Modern GPUs feature their special and specific single instruction multiple threads (SIMT) execution fashion, which makes their power/EM leakage more sophisticated in practical scenarios. In this article, we study side-channel attacks with leakage from SIMT systems, and propose leakage models suited to any SIMT systems and specifically to CUDA-enabled GPUs. Afterwards, we instantiate the models with a GPU AES implementation, which is also used for performance evaluations. In addition to the models, we provide optimizations on the attacks that are based on the models. To evaluate the models and optimizations, we run the GPU AES implementation on a CUDA-enabled GPU and, at the same time, collect its EM leakage. The experimental results show that the proposed models are more efficient and the optimizations are effective as well. Our study suggests that GPU-based cryptographic implementations may be much vulnerable to microarchitecture-based side-channel attacks. Therefore, GPU-specific countermeasures should be considered for GPU-based cryptographic implementations in practical applications.

This paper studies the design requirements and challenges of SDR (Software-Defined Radio) vector processors for 5G micro base stations. Pareto principle reflects the rule of “vital few and trivial many”, which states that 80% of consequences stem from 20% of causes. Since 20% of the instructions account for about 80% of the running time of the micro base station processor, it is essential to speed up the 20% instructions as the complex vector operations consuming most of the runtime. This paper proposes instruction fusion strategy and black-box acceleration strategy to speed up the kernel function of the micro base station algorithms. The experimental results show that the instruction fusion strategy can make the performance improvement ratio reach up to 17% while running the BDTI/ EEMBC benchmark, and the black-box acceleration strategy can make the performance improvement ratio reach about 5% while running the kernel of matrix inversion. In addition, our SIMD micro architecture is designed as a vector processor to eliminate the extra costs when implementing kernel micro scheduling. This paper provides a reference for the hardware implementation of 5G micro base stations with low cost and low-power consumption.

Cloud detection is one of the essential procedures in optical remote sensing image processing because clouds are widely distributed in remote sensing images and cause a lot of challenges, such as climate research and object detection. In this article, a lightweight deep-learning-based framework is proposed to detect cloud in remote sensing imagery. First, a multiple features fusion strategy is designed to extract learnable manual features and convolution features from visible and near-infrared bands. Then, a lightweight fully convolutional neural network (ClouDet) with a microarchitecture named dilated separable convolutional module is used to extract the multiscale contextual information and gradually recovers segmentation results with the same size as input image, which is more effective for large-scale cloud detection with larger receptive field, less parameters, and lower compute complexity. Third, context pooling is designed to amend the possible misjudgments. Visual and quantitative comparison experiments are conducted on several public cloud detection datasets, which indicates that our proposed method can accurately detect clouds under different conditions, which is more effective and accurate than the compared state-of-the-art methods.

Power consumption and electromagnetic emissions analyses are well established attack avenues for secret values extraction in a large range of embedded devices. Countermeasures against these attacks are approached at different levels, from modified logic styles, to changes in the software implementations. In this work, we propose a microarchitectural modification to a compact RISC-V SoC, the OpenTitan open source silicon root of trust, providing a code morphing countermeasure against power and electromagnetic emissions side channel attacks. Our approach allows the countermeasure to be applied transparently, without the need for any software modification to the cryptographic primitive running on OpenTitan. Our microarchitecture integration of a morphing engine also allows us to provide transparent protection to memory operations. We validate our approach through measurements on an actual FPGA prototype on a Xilinx Artix-7. Our integrated morphing engine increases the FPGA resource consumption by less than 8%, plus the resources required by an RNG of choice, with respect to the original OpenTitan SoC. Our design shows a side channel attack resistance improvement of at least $250\times $ in the Measurements-To-Disclose metric with respect to the unprotected design. We benchmark the performance of our proposed architecture on all the ISO/IEC standard symmetric block ciphers, including, among the other AES, reducing the execution time overhead by $21\times $ to $141\times $ with respect to a continuously morphing software solution.

This article presents the design and implementation of an embedded programmable processor with a custom instruction set architecture for efficient realization of artificial neural networks (ANNs). The ANN processor architecture is scalable, supporting an arbitrary number of layers and number of artificial neurons (ANs) per layer. Moreover, the processor supports ANNs with arbitrary interconnect structures among ANs to realize both feed-forward and dynamic recurrent networks. The processor architecture is customizable in which the numerical representation of inputs, outputs, and signals among ANs can be parameterized to an arbitrary fixed-point format. An ASIC implementation of the designed programmable ANN processor for networks with up to 512 ANs and 262,000 interconnects is presented and is estimated to occupy 2.23 mm2 of silicon area and consume 1.25 mW of power from a 1.6 V supply while operating at 74 MHz in a standard 32-nm CMOS technology. In order to assess and compare the efficiency of the designed ANN processor, we have designed and implemented a dedicated reconfigurable hardware architecture for the direct realization of ANNs. Characteristics and implementation results of the designed programmable ANN processor and the dedicated ANN hardware on a Xilinx Artix-7 field-programmable gate array (FPGA) are presented and compared using two benchmarks, the MNIST benchmark using a feed-forward ANN and a movie review sentiment analysis benchmark using a recurrent neural network.

The development of dataflow processor architecture is a promising direction for improving the performance of computing systems. The dataflow processors have several advantages in contrast with the von Neumann architecture processors. These advantages are express in explicit parallelism of calculations, since in the presentation of programs for the dataflow processors the execution of instructions is limited solely by the fact of input data’s ready state. The concept of using tokens as data storage for instructions allows you to remove many problems associated with data conflicts and simplifies the program logic. One of the most important elements in the implementation of the logic of the dataflow processor is the associative token memory, which should provide storage and quick search for ready-made data for instructions that can be transferred for execution. This article discusses the functionality of the dataflow processor emulator and its parts including associative token memory and the logic of its operation using the example of a simple dataflow graph.

Chip manufacturers introduce redundancy at various levels of CPU design to guarantee correct operation, even for worst-case combinations of non-idealities in process variation and system operating conditions. This redundancy is implemented partly in the form of voltage margins. However, for a wide range of real-world execution scenarios these margins are excessive and merely translate to increased power consumption, hindering the effort towards higher energy efficiency in both HPC and general purpose computing. Our study on the x86-64 Haswell and Skylake multicore microarchitectures reveals wide voltage margins, which vary across different microarchitectures, different chip parts of the same microarchitecture, and across different workloads. We find that it is necessary to quantify voltage margins using multi-threaded and multi-instance workloads, as characterization with single-threaded and single-instance workloads that do not stress the CPU to its full capacity typically identifies overly optimistic margins that lead to errors when applied in realistic program execution scenarios. In addition, we introduce, deploy and evaluate a run-time governor that dynamically reduces the supply voltage of modern multicore x86-64 CPUs. Our governor employs a model that takes as input a set of performance metrics which are directly measurable via performance monitoring counters and have high predictive value for the minimum tolerable supply voltage ( $V_{min}$ V m i n ), to predict and apply the appropriate reduction for the workload at hand. Compared with the conventional DVFS governor, our approach achieves up to 42 percent energy savings for the Skylake family and 34 percent for the Haswell family for complex, real-world applications.

Due to a lack of security design as well as the specific characteristics of IoT devices such as the heterogeneity of processor architecture, IoT malware detection has to deal with very unique challenges, especially on detecting cross-architecture IoT malware. Therefore, the IoT malware detection domain is the focus of research by the security community in recent years. There are many studies taking advantage of well-known dynamic or static analysis for detecting IoT malware; however, static-based methods are more effective when addressing the multi-architecture issue. In this paper, we give a thorough survey of static IoT malware detection. We first introduce the definition, evolution and security threats of IoT malware. Then, we summarize, compare and analyze existing IoT malware detection methods proposed in recent years. Finally, we carry out exactly the methods of existing studies based on the same IoT malware dataset and an experimental configuration to evaluate objectively and increasing the reliability of these studies in detecting IoT malware.

Hardware virtualization allows multiple security-critical and ordinary (insecure) processes to co-execute on a processor. These processes temporally share hardware resources and endure numerous security threats on the microarchitecture state. State-of-the-art secure processor architectures, such as MI6 and IRONHIDE enable capabilities to execute security-critical processes in hardware isolated enclaves utilizing the strong isolation security primitive. The MI6 processor purges small state resources on each enclave entry/exit and statically partitions the last-level cache and DRAM regions to ensure strong isolation. IRONHIDE takes a spatial approach and creates two isolated clusters of cores in a multicore processor to ensure strong isolation for processes executing in the enclave cluster. Both architectures observe performance degradation due to static partitioning of shared hardware resources. OPTIMUS proposes a security-centric dynamic hardware resource partitioning scheme that operates entirely at runtime and ensures strong isolation. It enables deterministic resource allocations at the application level granularity, and limits the number of hardware reconfigurations to ensure bounded information leakage via the timing and termination channels. The dynamic hardware resource partitioning capability of OPTIMUS is shown to co-optimize performance and security for the MI6 and IRONHIDE architectures.

IBM Z is both the oldest and among the most modern of computing platforms. Launched as S/360 in 1964, the mainframe became synonymous with large-scale computing for business and remains the workhorse of enterprise computing for businesses worldwide. Most of the world's largest banks, insurers, retailers, airlines, and enterprises from many other industries have IBM Z at the center of their IT infrastructure. This article presents an overview of the evolution of the IBM Z microprocessors over the past six generations. The article discusses some of the underlying workload characteristics and how these have influenced the microarchitecture enhancements driving the performance and capacity improvements. The article then describes how the focus shifted over time from speeds and feeds to new features, functions, and accelerators, and presents some examples on improved availability, enhanced security and cryptography, and embedded data compression acceleration.

Deep neural network (DNN) has been widely studied due to its high performance and usability for various applications such as image classification, detection, segmentation, translation, and action recognition. Thanks to the universal applications and high performance of DNN algorithm, DNN is adopted for various AI platforms, including edge/mobile devices as well as cloud servers. However, high-performance DNN requires a large amount of computation and memory access, making it challenging to implement DNN operation on edge/mobile. There have been several ways to solve these problems, including algorithms as well as hardware for DNN. Algorithms that help accelerate DNN in hardware enable much more efficient operation of high-performance AI. This article aims to provide an overview of the recent hardware and algorithm co-design schemes enabling efficient processing of DNNs. Specifically, it will provide algorithm optimization methods for DNN structure, neurons, synapses, and data types. This paper also introduces optimization methods for hardware architectures, PE array, data-path control, and microarchitecture of PE. And we will also show examples of DNN algorithm and hardware co-designed ASICs.

This work introduces reconfiguration for energy–performance adaptation beyond conventional voltage scaling in microcontroller-based systems. Coordinated thread-level processor and row-level memory reconfiguration are enabled by an architecture-agnostic methodology. The latter requires low design and integration effort while reusing existing macros, including third-party intellectual properties (IPs) in an obfuscated or encrypted form. The methodology represents a drop-in solution that is applicable to extend the energy–performance tradeoff in existing designs. The proposed approach was demonstrated with a testchip implementing an ARM Cortex-M0 processor with 16-KB SRAM in 40 nm. The system demonstrates 1.8X throughput boost at nominal voltage (1.1 V) and 1.3X energy reduction at the minimum energy point (0.51 V) compared to voltage scaling with no reconfiguration. Such energy–performance range extension is achieved at 10.3% area overhead, which is mostly due to processor reconfiguration. Overall, the proposed approach reduces energy in the common case and increases performance when demanded, surpassing the capabilities of conventional voltage scaling, while reusing existing IPs and retaining the original software stack.

This article addresses the challenges of memory safety in life-critical medical devices. Since the last decade, healthcare manufacturers have embraced the Internet of Things, pushing technological innovations to increase market share. Medical devices, including the most critical ones, tend to be increasingly connected to the Internet. Unfortunately, as critical devices often rely on unsafe programming languages such as C, they are no exception to memory safety issues. Given a memory vulnerability, a skillful attacker can take over a system and perform remote code execution. Combined with the fact that medical devices directly impact the safety of their users, a security vulnerability can lead to disastrous scenarios. To address this issue, this article presents TrustFlow-X, a novel hardware/software co-designed framework that provides efficient fine-grained control-flow integrity protection against memory-based attacks. The TrustFlow-X framework is composed of an LLVM-based compiler toolchain that generates a secure code. This secure code is then executed on an extended RISC-V processor that keeps track of sensitive data using a trusted memory. The obtained results show that the contribution is practical, providing a high level of trust in life-critical embedded systems.

Objectives Residual hip dysplasia is the most common underlying condition leading to secondary osteoarthritis (OA) of the hip. Subchondral bone alterations in OA secondary to hip dysplasia (HD-OA) are poorly investigated. The aim of the present study was to analyse the microarchitecture, bone remodelling and pathological alterations of subchondral bone in femoral heads from patients with HD-OA. Methods Subchondral bone specimens were extracted from both weight-bearing and non–weight-bearing regions of femoral heads from 20 patients with HD-OA and 20 patients with osteoporotic femoral neck fracture, during hip replacement surgery. Micro-CT and histological examination were performed to assess the microarchitecture and histopathological changes. Results The weight-bearing subchondral bone showed significantly more sclerotic microarchitecture and higher bone remodelling level in HD-OA as compared with osteoporosis. In the non–weight-bearing region, the two diseases shared similar microarchitectural characteristics, but higher bone remodelling level was detected in HD-OA. Distinct regional differences were observed in HD-OA, whereas the two regions exhibited similar characteristics in osteoporosis. In addition, HD-OA displayed more serious pathological alterations, including subchondral bone cyst, metaplastic cartilaginous tissue, bone marrow oedema and fibrous tissue, especially in the weight-bearing region. Conclusions Osteoarthritic deteriorations of subchondral bone induced by hip dysplasia spread throughout the whole joint, but exhibit region-dependent variations, with the weight-bearing region more seriously affected. Biomechanical stress might exert a pivotal impact on subchondral bone homeostasis in hip dysplasia. The translational potential of this article The histomorphometric findings in the project indicate an early intervention for the development of hip dysplasia in clinic.

Small-footprint implementations of the advanced encryption standard (AES) algorithm are of interest in resource-constrained applications like Internet of Things (IoT). Symmetries in AES allow the datapath to be scaled down to the S-Box width of 8 bits, but the ShiftRows operation leads to a potential data hazard that must be avoided. The common method for resolving the ShiftRows hazard wastes power by moving data through a sequence of pipelined registers. We present in this article a novel 8-bit AES architecture that solves data movement inefficiencies by renaming registers and saves clock power with a single state update per AES round. We then extend register renaming to include microarchitectural randomization to mitigate susceptibility to side-channel attacks, which are a concern especially for low power implementations of AES. We fabricate and evaluate our designs in a commercial 16-nm FinFET technology. Testchip measurements show that the register renaming architecture encrypts data at 0.55 pJ/bit at nominal voltage, a $2.2\times $ improvement over a state-of-the-art reference 8-bit design implemented in the same technology. Side-channel evaluation indicates that the randomized variant of register renaming significantly reduces vulnerability to differential power analysis (DPA).

There are currently no population-based reference data sets available for volumetric bone mineral density and microarchitecture parameters measured using the second-generation high-resolution peripheral quantitative computed tomography (HR-pQCT), yet the technology is rapidly becoming a standard for studies of bone microarchitecture. Although cross-calibrated data sets from the first-generation HR-pQCT have been reported, they are not suitable for second-generation bone microarchitecture properties because of fundamental differences between scanner generations. This study provides site- and sex-specific centile curves across the adult life span for second-generation HR-pQCT properties. A total of 1236 adult participants (768 female and 468 male) from the Calgary area between the ages of 18 and 90 years were scanned at the distal tibia and radius using the second-generation HR-pQCT. Bone densities, microarchitectural properties, and failure load estimated using finite element analysis were determined using standard in vivo protocol. Site- and sex-specific centile curves were generated using the generalized additive models for location, scale, and shape (GAMLSS) method. These data provide reference curves appropriate for predominantly white male and female adults, which can be used as a tool to assess patient- or cohort-specific bone health. © 2020 American Society for Bone and Mineral Research.

Memory access latencies and low data transfer bandwidth limit the processing speed of many data intensive applications such as Convolutional Neural Networks (CNNs) in conventional Von Neumann architectures. Processing in Memory (PIM) is envisioned as a potential hardware solution for such applications as the data access bottlenecks can be avoided in PIM by performing computations within the memory die. However, PIM realizations with logic-based complex processing units within the memory present complicated fabrication challenges. In this letter, we propose to leverage the existing memory infrastructure to implement a programmable PIM (pPIM), a novel Look-Up-Table (LUT)-based PIM where all the processing units are implemented solely with LUTs, as opposed to prior LUT-based PIM implementations that combine LUT with logic circuitry for computations. This enables pPIM to perform ultra-low power & low-latency operations with minimal fabrication complications. Moreover, the complete LUT-based design offers simple ‘memory write’ based programmability in pPIM. Enabling precision scaling further improves the performance and the power consumption for CNN applications. The programmability feature potentially makes it easier for online training implementations. Our preliminary simulations demonstrate that our proposed pPIM can achieve 2000x, 657.5x and 1.46x improvement in inference throughput per unit power consumption compared to state-of-the-art conventional processor architecture, Graphics Processing Unit (GPUs) and a prior hybrid LUT-logic based PIM respectively. Furthermore, precision scaling improves the energy efficiency of the pPIM approximately by 1.35x over its full-precision operation.