Search

We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2-mm flop-to-flop distance is distributed throughout the chiplet for high-speed on-die data transport above 4.0 GHz. The chiplets communicate with each other through ultrashort reach (0.5 mm long) interposer channels using a Low-voltage-In-Package-INterCONnect (LIPINCON) clock-forwarded parallel interface. The scalable link module offers 320 GB/s of aggregate bandwidth, operating at 8.0 Gb/s/pin and 0.3-V transmitter swing without receiver termination to achieve 0.56-pJ/bit energy efficiency and 1.6-Tb/s/mm2 bandwidth density. Measurements of the fabricated SiP validate the functionality and performance of the cores, on-die data bus, and inter-chiplet link. The built-in LIPINCON eye-scan feature validates inter-chiplet connectivity at 8.0 Gb/s with an eye opening of 244 mV and 0.69 UI.

Background: Behcet’s disease (BD) is a multisystemic, chronic inflammatory disorder with a broad range of manifestations including within the cardiovascular system. Cardiac involvement like intracardiac thrombus (ICT) and valvular involvement in BD are rarely seen entities and often associated with poor prognosis. Case Presentation: We present the case of a young patient with vascular-Behcet diagnosed by the presence of intracardiac thrombus in the right ventricle, unresponsive to medical treatment. Even though the intracardiac lesion was successfully treated by surgical excision, he presented a severe tricuspid dysfunction some years later due to the extension of fibrosis with no surgical therapeutic option. Conclusion: Intracardiac thrombosis is a rare but early manifestation of Behcet’s disease, which is difficult to diagnose and has a poor prognosis.

Metastatic melanoma is a fatal disease with poor prognosis. Ever since targeted therapy against oncogenic BRAF was approved, molecular profiling has become an integral part of the management of such patients. While molecular testing is not available in all pathology laboratories, immunohistochemistry (IHC) is a reliable screening option. The major objective of the present study was to evaluate whether IHC detection of BRAF and the tumor (suppressor) protein 53 gene (TP53) are reliable surrogates for mutation detection. Formalin-fixed paraffin-embedded samples of melanomas for which molecular data were previously obtained by targeted next-generation sequencing (NGS) between January 2014 and February 2019 were immunostained with BRAF V600E and p53 antibodies. A blinded evaluation of the IHC slides was performed by two pathologists in order to evaluate inter-observer concordance (discordant cases were reviewed by a third observer). The associations between the results of IHC and molecular profiling were evaluated. The study included a series of 37 cases of which 15 harbored a BRAF mutation and five a TP53 mutation. IHC had an overall diagnostic accuracy of 93.9% for BRAF V600E and 68.8% for TP53 compared to NGS. A statistically significant association between the two diagnostic methods was obtained for BRAF V600E (P=0.0004) but not for p53 (P=0.3098) IHC. The κ coefficient for IHC assessment of p53 was 0.55 and that for BRAF V600E was 0.72. In conclusion, the present results evidenced that IHC staining is a reliable surrogate for NGS in identifying the BRAF V600E mutation, which may become an efficient screening tool. Aberrant expression of p53 on IHC is at times associated with TP53 mutations but it was not possible to establish a direct link.

Autopsy is an important quality assurance indicator and a tool to advance medical knowledge. This study aims to compare the premortem clinical and postmortem pathology findings in patients who died in the Intensive Care Unit (ICU), to analyze if there are any discrepancies between them, and to compare the results to two similar studies performed in our institution in 2004 and 2007. Between January 1, 2016, and December 31, 2018, 888 patients died in the ICU and 473 underwent post-mortem examination (PME) of whom 437 were included in the present study. Autopsies revealed discrepancies between clinical diagnosis and pathologic findings according to in 101 cases (23.1%) according to Goldman classification. Forty-eight major discrepancies (class I and class II) were identified in 44 cases and the most frequent identified discrepancies were pulmonary embolism (3/12) as class I and malignancies (13/35) as class II. They were more frequent in patients hospitalized for less than 10 days then in the group with more than 10 days of hospitalization (13.8% vs 4.5%; p = 0.002). No statistical difference has been noticed concerning age, gender, and ICU stay. We observed an increase of performed autopsies and a total discrepancy rate similar to the studies performed in the same institution in 2004 (22.5%) and 2007 (21%). In conclusion, discrepancies between clinical and PME diagnoses persist despite the medical progress. Secondly, the autopsy after a short hospital stay may reveal unexpected findings whose diagnosis is challenging even if it may be suspected by the intensivist. Supplementary Information The online version contains supplementary material available at 10.1007/s00428-020-03016-y.

We demonstrate two heterogeneous solutions to improve power delivery to High-Performance Computing (HPC) processors. The scalable HPC vehicle integrates two 7nm CMOS processor chiplets, each with four ARM® Cortex®-A72 cores, that are mounted on a Chip-on-Wafer-on-Substrate (CoWoS®) silicon interposer [1]. In the first solution, Integrated Passive Device (IPD) capacitors are placed directly beneath the interposer to provide more accessible and effective supply noise decoupling. The result is 3.9% higher maximum clock frequency at a core supply of 1.135V. In the second solution, the processor is powered by a laterally mounted in-Package Voltage Regulator (PVR) built in 28nm CMOS augmented with high-per-meability on-die inductors. The processor performance provided by the buck converter-based PVR matches that by an off-package External Voltage Regulator (EVR). As processor power increases with higher core counts, PVRs with on-die inductors will be increasingly compelling for efficient system power delivery.

This Special Section of the IEEE Journal of Solid-State Circuits (JSSC) features expanded versions of papers selected from those presented at the 48th ESSCIRC Conference, held at Technische Universitat Dresden, Dresden, Germany, during September 3–6, 2018.

A dual-chiplet Chip-on-Wafer-on-Substrate (CoWoS®) was implemented in 7nm 15M process. Each SoC chiplet has four Arm® Cortex®-A72 processors operating at 4GHz. The on-die interconnect mesh bus operates above 4GHz at 2mm distance. The inter-chiplet connection features a scalable, 0.56pJ/bit power efficiency, 1.6Tb/s/mm2 bandwidth density, and 0.3V Lowvoltage- In-Package-INterCONnect (LIPINCONTM) interface achieving 8Gb/s/pin and 320GB/s bandwidth. Silicon test-chip measurements validate the processor, on-die interconnects and inter-chiplet interface performance. The built-in eye-scan feature shows the inter-chiplet connection achieves 244mV eye-height and 69% UI eye-width.

Dear Readers, The editorial board is pleased to welcome you to the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS). Our first papers will soon be available online via the IEEEXplore® platform.

This paper describes a 4.3B transistors, 15-cores, 30-threads enterprise Xeon® processor with a 37.5 MB shared L3 cache implemented in a 22 nm 9M Hi-K metal gate tri-gate process. A modular floorplan methodology enables easy chops to 10 and 6 cores. Multiple clock and voltage domains are used to reduce power consumption. The clock distribution uses a single PLL per column to save power and minimize deskew crossing points. Integrated PCIe Gen3 and Quick Path Interconnect® (QPI) ports operate at 8GT/s. The 4-channel memory interface supports both 1866 MT/s DDR3 and a new memory buffer interface running at 2667 MT/s on the same pins. The core, cache and I/O recovery techniques improve manufacturing yields and enable multiple product flavors from the same silicon die.

Welcome to this special issue of the Journal covering the 40th European Solid-State Circuits Conference, ESSCIRC 2015. The conference was held in Graz, Austria, September 14–18, 2015. From the 102 papers presented at the conference, a selection of 18 papers was made for inclusion in this special issue. As Guest Editors, we have used the inputs of the technical program committee and the session chairs, as well as the audience ratings. The selected papers are briefly introduced below.

The papers in this special section were presented at the 2014 IEEE Asian Solid-State Circuits Conference (ASSCC), which was held in KaoHsiung, Taiwan, on November 10–12, 2014.

The Echinococcus granulosus tapeworm is responsible for cystic echinococcosis (CE), a zoonotic disease with worldwide distribution. The life cycle of the parasite is mainly domestic and takes place between dogs and livestock species. A slaughterhouse survey was conducted in 2012 in the Republic of Moldova in order to estimate the prevalence of CE. A total of 1525 cattle, 5580 sheep and 12,700 pigs were surveyed. No CE infection was observed in pigs, while prevalence was estimated at 59.3% in cattle and 61.9% in sheep. Infection was significantly higher in animals raised in private households than in those from collective farms. The frequency of infection increased with age in both species. In cattle and in sheep, infection of both the liver and lungs was the most common, while infection in the lungs only was much less frequent. Farm type appears to be an important factor in CE infection in Moldova, due to the extensive farming and the home-slaughtering undertaken in the majority private sector, despite a high prevalence of CE also recorded in the public sector. The low fertility of cysts in cattle (1.1%) compared to sheep (47.6%) confirmed the maintenance of E. granulosussensu stricto in a dog–sheep life cycle which excludes cattle. Further studies are needed to obtain a complete overview of the parasite's epidemiology in its intermediate and definitive hosts, in order to implement control and preventive measures, with specific attention given to farms in the private sector.

There are few papers which aim to analyze the effects of laser marking for traceability on various materials; therefore, the present paper proposes a study of the influences of such radiation processing on a titanium alloy, a vastly used material base within several industry fields. For the novelty impact, femtolaser marking has been carried out, besides the commercial nanosecond standard engraving. All marks have been analyzed using scanning electron microscopy, energy dispersive X-ray spectroscopy and X-ray diffractometry.

The articles in this special issue were preseted at the 39th European Solid-State Circuits Conference (ESSCIRC).

This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the unterminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

This issue includes a total of 16 analog/RF papers and four digital papers. The papers are briefly introduced here.

The 16-way set associative, single-ported 16-MB cache for the Dual-Core Intel Xeon Processor 7100 Series uses a 0.624 mum2 cell in a 65-nm 8-metal technology. Low power techniques are implemented in the L3 cache to minimize both leakage and dynamic power. Sleep transistors are used in the SRAM array and peripherals, reducing the cache leakage by more than 2X. Only 0.8% of the cache is powered up for a cache access. Dynamic cache line disable (Intel Cache Safe Technology) with a history buffer protects the cache from latent defects and infant mortality failures

This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm2 die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes. Long channel transistors are used to reduce subthreshold leakage in cores and uncore (all portions of the die that are outside the cores) control logic. Multiple voltage and clock domains are employed to reduce power

The 18-way set-associative, single-ported 9 MB cache for the Itanium 2 processor uses 210 identical 48-kB sub-arrays with a 2.21-/spl mu/m/sup 2/ cell in a 130-nm 6-metal technology. The processor runs at 1.7 GHz at 1.35 V and dissipates 130 W. The 432-mm/sup 2/ die contains 592 M transistors, the largest transistor count reported for a microprocessor. This paper reviews circuit design and implementation details for the L3 cache data and tag arrays. The staged mode ECC scheme avoids a latency increase in the L3 tag. A high V/sub t/ implant improves the read stability and reduces the sub-threshold leakage.

This paper describes the design of a system bus interface for the 130-nm Itanium/sup /spl reg//2 processor that operates at 400MT/s (1 megatransfer = 1 Mb/s/pin) with a peak bandwidth of 6.4 GB/s. The high-speed operation is achieved by employing source-synchronous transfer with differential strobes. Short flight time is accomplished by double-sided placement of the processors. Preboost and postboost edge-rate control enables fast clock-to-output timing with tight edge-rate range. The built-in input/output (I/O) loopback test feature enables I/O parameters to be tested on die, using a delay-locked loop and interpolator with 21-ps phase-skew error and 15-ps rms jitter. Power modeling methodology facilitates accurate prediction of system performance.

The next-generation enterprise Xeon® server processor has 15 dual-threaded 64b Ivybridge cores [1] and 37.5MB shared L3 cache. The system interface includes two on-chip memory controllers, each with two memory channels and supports multiple system topologies. The processor has 4.31B transistors in a high-κ metal-gate tri-gate 22nm CMOS technology with 9 metal layers [2]. The design supports a wide array of product offerings with thermal design power ranging from 40 to 150W and frequencies ranging from 1.4 to 3.8GHz. Fig. 5.4.1(a) shows the processor block diagram. The floorplan (Fig. 5.4.1(b)) is driven by the ring bus routability and latency, as well as the chop requirements to smaller core counts. The cores and associated L3 cache are organized in columns of five, with the ring bus segment embedded. The fully populated die has 15-cores in three columns. The 10-core chop removes the rightmost 3rd column and its dedicated top and bottom IOs. CMOS muxes embedded in the ring bus are programmably operable in a 2-or-3-columns configuration. The 6-core chop removes the 2nd and 4th rows from the 10-core die.

The 13 papers in this special issue are extended versions of papers presented at the 35th European Solid-State Circuits Conference (ESSCIRC), held September 14-18, 2009, in Athens, Greece. There are a total of six RF papers, five analog papers and two digital papers.

The first implementation of the IA-64 architecture achieves high performance by using a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set. Explicitly parallel instruction computing (EPIC) design maximizes performance through hardware and software synergy. The processor contains 25.4 million transistors and operates at 800 MHz. The chip is fabricated in a 0.18-/spl mu/m CMOS process with six metal layers and packaged in a 1012-pad organic land grid array using C4 (flip chip) assembly technology. A core speed back-side bus connects the processor to a 4-MB L3 cache.

The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market.

This special issue contains 21 extended papers from the 34th ESSCIRC, held September 15-19, 2008, in Edinburgh, United Kingdom.

Processors have long been the leading edge of integration and process technology and this year's papers emphatically demonstrate that this is still the case. This year's crop of processors exhibit astounding increases in chip integration levels with more cores, special-function units and huge increases in the bandwidth of both on- and off-die interconnect. Emerging markets combine the attributes of network processors (many-threaded low-power cores) and server processors (large cores with virtualization and RAS). Higher levels of memory integration are achieved by using embedded DRAM in these large processors to support the higher-bandwidth demands of throughput computing. The challenges of managing the dramatic growth in dynamic power and leakage (if all integrated components were allowed to activate simultaneously) are addressed with a variety of innovative power management methods such as on-die gating and multiple voltage and frequency domains. Moore's law continues as the first 32nm processors from Intel and AMD are described, together with the latest implementation of the POWER and SPARC architectures.

This 45nm 1.1V unidirectional differential point-to-point link interface achieves 6.4GT/s transfer rate. To support 17 inches, 2-connector channel topology required by MultiProcessor (MP) platform, it utilizes two novel current compensation techniques that optimize the performance/power ratio of the transmitter output swing level and receiver gain/bandwidth.

A 2.3B transistors, 8-core, 16-thread 64-bit Xeon® EX processor with a 24MB shared L3 cache was implemented in a 45nm 9-metal process. Multiple clock and voltage domains are employed to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors using the same silicon die and package. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

This paper presents the power reduction and management techniques for the 45nm, 8-core Nehalem-EX processor. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. Clock and power gating minimize power consumed by disabled blocks. An on-die microcontroller manages voltage and frequency operating points, as well as power and thermal events. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

Multiple clock and power domains are widely used to manage power in modern nanoscale designs. This Forum will present the latest design techniques in multiple-domain clock and power management for high-performance processors, as well as low-power systems-on-chip (SoC). Topics include clock and data synchronization, power gating, floorplan and layout implications, clock and power grids, test requirements, modular design techniques. Practical examples will be presented from both industry and academia.

A 65 nm 1.2 V GTL bus interface achieves 800 MT/s 6.4 GB/S data rate in a 3-load multi-processor (MP) environment. To enable a 20% increase in data rate compared to previous design, it utilizes a staged driver, DLL controlled predriver, Tco compensation, data/strobe time shifter, high gain differential amplifier as well as advanced process, voltage and temperature (PVT) compensation design.

This paper describes a 95 W dual-core 64-bit Xeonreg MP processor implemented in a 65 nm 8 metal layer process. Each processor core has a unified 1MB L2 cache and supports the Intelreg Extended Memory 64 Technology and the Hyper-Threading Technology. The shared L3 cache has extensive RAS features including the Intelreg Cache Safe Technology and Error Correction Codes (ECC). The processor is designed and optimized to operate at a 95W thermal design power envelope at the target product frequency. The front-side bus operates at 667 MT/s or 800 MT/s in a 3 load topology that is compatible with existing platforms.

A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm2 die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes

A 130nm 1.2V GTL bus interface with compensated slew rate and termination achieves 667MT/S 10.7GB/S data rate in a 3-load MP environment. The design utilizes preboost and postboost methods, current steering circuit to minimize simultaneous switching noise and negative hysteresis to speed up the common-clock delay. The design also incorporates system-level I/O loopback for system timing marginality test

This 130nm Itanium/spl reg/ 2 processor implements the Explicitly Parallel Instruction Computing (EPIC) architecture and features an on-die 6MB, 24-way set associative L3 cache. The 374mm/sup 2/ die contains 410M transistors and is implemented in a dual-Vt process with 6 layers copper interconnect and FSG dielectric. The processor runs at 1.5GHz at 1.3V and dissipates a maximum of 130W. This paper reviews circuit design and package details, power delivery, RAS, DFT and DFM features, as well as an overview of the design and verification methodology. The fuse-based clock de-skew circuit achieves 24ps skew across the entire die, while the scan-based skew control further reduces it to 7ps. The 128-bit front-side bus supports up to 4 processors on a single bus with a bandwidth of up to 6.4GB/s.

Describes a RISC (reduced-instruction-set computer) BiCMOS superscalar microprocessor containing 3.1 M transistors which executes up to three instructions per clock cycle. Clock frequency is 40 MHz with 8 mW dissipation. The chip includes a 32-b integer pipeline (IU), a memory management unit (MMU), a 20-kB instruction cache (I cache), a 16-kB data cache (D cache), an IEEE-compatible double-precision floating-point unit (FU), and a bus interface (BU). The chip supports built-in self-test, internal and JTAG boundary scan, in-circuit emulation for remote symbolic source-code debugging, and hardware to support multiprocessor system architecture. An on-chip phase-locked loop synchronizes external and internal clock edges. The chip is implemented in a 0.8- mu m triple-layer-metal salacided BiCMOS process. The die is 15.98*15.98 mm/sup 2/, with 166 active pins and 127 power/ground pins. >

A description is given of a BiCMOS 50-MHz, 2.2 M-transistor cache controller (CC) chip which supports up to 2 MB of direct-mapped secondary cache for a superscalar microprocessor chip (PU) and interfaces with two multiprocessor (MP) buses. One is the MBus, a circuit-switched MP system bus operating at TTL (transistor-transistor logic) levels. The other is the XBus, a local packet-switched bus operating at either TTL or Gunning-transceiver logic (GTL) levels. In XBus mode, the CC connects to MP buses through buswatcher chips, up to four of which can be connected to the CC to support 4 MP buses. With XBus interface, the CC can support customized MP buses. >

Due to the increased number of metal layers and flip-chip packaging, most high-performance microprocessors use optical solutions to probe internal nodes from the backside of the die. Existing probing systems use a focused infrared (1.064/spl mu/m) laser to probe internal diffusions from the backside of a chip thinned down to 100/spl mu/m. However, this optical probing setup does not provide accurate information about DC voltage levels. Also, because of the stroboscopic sampling used in laser probing, jitter measurements are difficult. This approach overcomes these limitations using alternative optical non-invasive techniques based on the infrared radiation emitted by hot electrons in saturated nMOS transistors under both static bias and switching conditions.

The Itanium processor is Intel's first 64-bit microprocessor [1] and features a highly parallel architecture fabricated using the 0.18um process. This higher integration of features requires a significant silicon real estate and high clock loading. These factors, coupled with more prominent on-die variations because of reduced device geometries, call for special techniques to manage the clock design. The Itanium processor employs very well balanced clock routing along with distributed deskew buffers (DSK) to achieve low skew. The ItaniumTM processor also includes additional features to aid performance tuning and timing debug. This paper highlights the salient features of the Itanium processor clock design and presents clock characterization data from initial silicon.

The extended versions of 14 analog/RF papers and four digital papers were selected from the 128 papers presented at the 32nd European Solid-State Circuits Conference (ESSCIRC), held September 18-22, 2006, in Montreux, Switzerland.