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This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current ($I_{\text {ON}}$). The capacitance matching and ON-state performance are evaluated using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current ($I_{\text {OFF}}$) and $I_{\text {ON}}$ relative to International Roadmap for Devices and Systems (IRDS) projections. There is a significant long-term advantage to integrated circuit (IC) power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing. [ABSTRACT FROM AUTHOR]

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and 2 μm, in an inverter circuit. At 2-μm gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors. [ABSTRACT FROM AUTHOR]

Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency (Ft) by ~10% and minimum number of substacks and minimum substack spacing should be used. [ABSTRACT FROM AUTHOR]

In this article, we will analyze and provide new insights into the polarization gradient effect of a ferroelectric using TCAD simulation and demonstrate how to model the polarization gradient effect using the negative capacitance FET (NCFET) compact model based on the BSIM framework. A larger value of g (the coefficient of polarization gradient effect) results in improved subthreshold slope, smaller OFF-current, smaller drain-induced barrier lowering (DIBL), and smaller output conductance. Inclusion of the polarization gradient effect in the NCFET compact model improves usability because it accurately captures the effects of negative DIBL and negative output conductance. [ABSTRACT FROM AUTHOR]

The Negative Capacitance Field Effect Transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOSFET theory. This benefit arises from an effect which acts similarly to decreasing the equivalent-oxide thickness at short gate lengths. The effect is observed in both TCAD simulations and experiments, and is explained by the conjunction of the source/drain inner fringing field and the nonlinear polarizability of ferroelectric materials. The results present a sharp contrast to conventional scaling theory and bode well for extending the MOSFET gate length scaling limit. [ABSTRACT FROM AUTHOR]

We report on negative capacitance FETs (NCFETs) with a 1.8-nm-thick Zr-doped HfO2 gate oxide layer fabricated on an FDSOI wafer. Hysteresis-free operation is demonstrated. When compared to a baseline that uses HfO2 gate oxide with the same thickness, a subthreshold swing (SS) steeper by more than 20 mV/decade and larger than 10X reduction in the OFF current (${I}_{ \mathrm{OFF}}$) is observed at 30-nm channel length at constant ${I}_{ \mathrm{\scriptscriptstyle ON}}$. On the other hand, at matched ${I} _{ \mathrm{\scriptscriptstyle OFF}}$ , the NCFET provides a larger ON current at constant ${V}_{\mathrm {DD}}$. Our results indicate that the beneficial characteristic offered by the NCFETs can be obtained at scaled channel lengths, while using oxide layers whose thickness is comparable to the high- ${K}$ oxide layer used in ultra-scaled nodes. [ABSTRACT FROM AUTHOR]

The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate capacitance but also the drain current due to the additional gate control from the outer fringing field. It is found that in a heavily loaded circuit although the fin corner spacer improves the inverter propagation delay of the baseline FinFET, the NC-FinFET requires the fin selective spacer with the spacer height up to the ferroelectric thickness for better capacitance matching. When the wire capacitance is ~3 times larger than the gate capacitance, the inverter propagation delay of the NC-FinFET with the fin selective spacer can be improved by ~8% against the full spacer design. However, with the consideration of process complexity, the air spacer may still be attractive in the NC-FinFET, since it does not suffer from the amplified gate capacitance. [ABSTRACT FROM AUTHOR]

In this brief, we present an improved model of bulk charge effect for both drain current (${I}_{\text {DS}}$) and capacitances and its implementation in the industry standard Berkeley short-channel IGFET model (BSIM)-BULK model. The proposed model captures all the well-known and important bulk charge effects, as the Abulk term does for BSIM3/BSIM4. The model is validated with the experimental and technology computer-aided design (TCAD) data. The proposed model enhances the fitting accuracy for ${I}_{\text {DS}}$ , and more importantly its derivatives and capacitances too. [ABSTRACT FROM AUTHOR]

A new design to overcome the nonuniformity of capacitance matching along the channel of a negative capacitance field-effect transistor is presented in this letter. By introducing nonuniform oxidation, the thickness of SiO2 at the edge regions of the channel can be increased while maintaining the thickness of SiO2 at the center region of the channel. As a result, the capacitance along the channel becomes more uniform, and better capacitance matching between the dielectric and ferroelectric can be achieved. The Sentaurus TCAD results show improvement of matching in the center region and a significant boost of ON-current (20% improvement). [ABSTRACT FROM AUTHOR]

We investigate the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node. The 8-/7-nm technology node of the p-type body NC-FinFET is modeled using the Sentaurus technology-aided design (TCAD), which couples Poisson with Landau equations. It is found that the NC effect is beneficial for device scaling. The OFF current is well suppressed in short-channel devices (64.4% reduction at LG = 16 nm) because the inner fringing field induces negative gate charges and decreases the channel potential. For longer channel devices, the influence of inner fringing field disappears, and the depletion charges dominate the subthreshold characteristics. As reducing remnant polarization, the ON current is boosted (11.4% improvement at LG = 16 nm) for all lengths due to better matching between MOSFET and ferroelectric capacitances. In comparison with FinFET, the drain-induced barrier lowering of NC-FinFET is also well controlled (50% reduction at LG = 16 nm) due to the inner fringing field-induced gate charges, showing the scaling capability of NC-FinFET. Furthermore, a compact model to capture the spatial distribution of the inner fringing field is also proposed based on the Gaussian quadrature method, and it is validated with the TCAD simulated data with multiple gate lengths and remnant polarizations. [ABSTRACT FROM AUTHOR]

In this letter, we investigate annealing effects in ferroelectric HfZrOx dielectric in metal–insulator–metal devices and metal–oxide–semiconductor capacitors by comparing two annealing methods: rapid thermal annealing (RTA) and microwave annealing (MWA). The tradeoff characteristics between the annealing conditions, polarization–electric field characteristics, gate leakage current, and interface state density (${D} _{\textsf {it}}$) are discussed. We show that: 1) a positive correlation between the remanent polarization (Pr), the gate leakage current, and ${D}_{\textsf {it}}$ as the annealing temperature (RTA) and the annealing power (MWA) increase and 2) the MWA is promising for ferroelectric transistors technology, since its low thermal budget can minimize ${D}_{\textsf {it}}$ and avoid increase in the gate leakage current. [ABSTRACT FROM AUTHOR]

Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance (${C}_{\textsf {fe}}$) and the underlying MOS transistor (${C}_{\textsf {MOS}}$). Since both ${C}_{\textsf {MOS}}$ and ${C}_{\textsf {fe}}$ have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of ${C}_{\textsf {fe}}$. The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-threshold swing as well as lower power supply ${V}_{\textsf {dd}}$ compared with a prototype single-layer negative-capacitance field-effect transistor. [ABSTRACT FROM AUTHOR]

We propose a new scheme to consider the dielectric (DE) phases inside polycrystalline ferroelectric (FE) materials. The scheme is used to extract material parameters from experimental polarization-electric field (P-E) measurements from the literature. A Sentaurus TCAD structure is constructed with the extracted parameters, and the simulated P-E curve is in a good agreement with the experimental data. Furthermore, variation of the device performance in a negative capacitance field-effect transistor (NCFET) due to the spatial distribution of DE and FE phases is studied using Sentaurus TCAD. It is found that the resultant variations of on and off currents can be up to 14.44% and 30.23%, respectively, thus showing the impact of inhomogeneous crystalline phases of the FE material on device performance. [ABSTRACT FROM AUTHOR]

Negative capacitance field-effect transistors (NCFETs) boost the electric field at the semiconductor-channel interface by virtue of the gate voltage amplification effect of a ferroelectric (fe) layer. NCFETs should be designed in such a way that this elevated field does not exceed the maximum electric field ( ${E}_{\max}$ ) determined by the reliability limit of the interfacial dielectric or NBTI/PBTI reliability. In this letter, a compact model-based methodology is presented to determine the NCFET design space considering several variables of the fe-layer and the baseline transistor, including the fe-layer thickness ( ${T}_{\mathrm {fe}}$ ), coercive field ( ${E}_{c}$ ), remnant polarization ( ${P}_{r}$ ), baseline transistor equivalent oxide thickness, supply voltage ( ${V}_{\mathrm {dd}}$ ), threshold voltage ( ${V}_{\mathrm {th}}$ ), and ${E}_{\max}$. Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better ${I}_ \mathrm{\scriptstyle ON}/{I}_ \mathrm{\scriptstyle OFF}$ ratio and sub-threshold swing while operating at lower ${V}_{\mathrm {dd}}$. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

Negative capacitance (NC) FETs with channel lengths from 30 nm to 50~\mu \textm , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse drain induced barrier lowering characteristics of the NC operation. [ABSTRACT FROM PUBLISHER]

We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-annealing is necessary to induce the formation of the ferroelectric phase in this oxide stack, the integrity of the oxide/silicon interface must be preserved after high-temperature processing. As such, we show that a nitrided interlayer provides an improved midgap interface state density among all interfacial oxides investigated. Furthermore, we quantify the interface states using the ac conductance technique and model the interface trap distribution across the silicon bandgap in order to explain and verify the experimental measurements. [ABSTRACT FROM PUBLISHER]

In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation. [ABSTRACT FROM PUBLISHER]

We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau–Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET. [ABSTRACT FROM PUBLISHER]

An electrostatic nonuniformity in the cantilever vertical tunneling FETs intrinsically exists in the InAs/GaSb junction to InAs cantilever transition region. The effects of the coupling ratio (CR) nonuniformity are investigated in this paper. The results show that the switching characteristics are degraded by the CR nonuniformity, especially in the case of large InAs/GaSb band offset. This paper also reveals that the nonuniformity in InAs/GaSb vertical tunneling FETs can be mitigated with the optimized band offset of heterojunction, scaling of oxide thickness, and acute angle etching profile. [ABSTRACT FROM AUTHOR]

Accurate determination of the flat band voltage ( V\mathrm {{FB}} ) is very important for extracting the effective work function of metal, and it will affect the prediction of the threshold voltage of the metal–oxide–semiconductor (MOS) devices. A modified method to accurately determine V\mathrm {{FB}} of the In0.53Ga0.47As n-type MOS device is presented. The effects of capacitance voltage hysteresis and interface trap density at the oxide/semiconductor interface on the accuracy of the extracted V\mathrm {{FB}} values are discussed. The results are also applicable to other MOS devices with high mobility channel materials. [ABSTRACT FROM PUBLISHER]

We demonstrate p-channel gate-source/drain underlapped silicon FinFET with HfO2 high- $\kappa $ spacer and compare it with its counterpart having SiO2 low- $\kappa $ spacer. The HfO2 spacer structure reduces series resistance in the underlap regions due to the large capacitive coupling between the gate and the underlap regions. Both drain current and transconductance of p-channel FinFET are higher than those of the SiO2 spacer device by about $3\times $ when biased in the saturation region, and about $1.6\times $ and $2\times $ , respectively, when biased in the linear region. Subthreshold swing and drain-induced barrier lowering are also improved by incorporating the HfO2 spacer. [ABSTRACT FROM PUBLISHER]

In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained. [ABSTRACT FROM AUTHOR]

We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length Lg=100 nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We show that a self-consistent simulation scheme based on Berkeley SPICE Insulated-Gate-FET Model:Common Multi Gate model and Landau–Devonshire formalism could quantitatively match the experimental NC-FinFET transfer characteristics. This also allows a general procedure to extract the effective $S$ -shaped ferroelectric charge–voltage characteristics that provides important insights into the device operation. [ABSTRACT FROM PUBLISHER]

In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently. An experimental NC-FinFET device is accurately modeled and the experimentally calibrated parameters are used to analyze the NC-FinFETs device performance and its dependence on several key parameters. [ABSTRACT FROM PUBLISHER]

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source–drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node. [ABSTRACT FROM PUBLISHER]

We study the effects of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs (NCFETs). Based on this, we propose the concept of conservative design of NCFETs, where any unintentional yet reasonable and simultaneous variation ( $\sim \pm 3$ %) in ferroelectric parameters does not result in the emergence of hysteresis and causes only a reasonable variation in the ON-current (≤5%) and, within these constraints, the enhancement of ON-current due to the addition of the ferroelectric gate oxide, which is is maximized. [ABSTRACT FROM AUTHOR]

The performance of a tunnel field effect transistor (TFET) with a raised germanium (Ge) source region is investigated via 2-D device simulation with a tunneling model calibrated to experimental data. The comparison of various Ge-source TFET designs shows that a fully elevated Ge-source design provides for the steepest subthreshold swing and, therefore, the largest on-state drive current for low-voltage operation. Mixed-mode (dc and ac) simulations are used to assess the energy-delay performance. In comparison with a MOSFET, an optimized Ge-source TFET is projected to provide for a lower energy per operation for throughput in the frequency range of up to \sim1 GHz for sub-0.5-V operation. [ABSTRACT FROM PUBLISHER]