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Device surface properties are critical for its performance such as channel electron density, leakage current, subthreshold swing (SS), and noise in gallium nitride high-electron-mobility transistors (HEMTs). In this article, the improved surface property of InAlN/GaN HEMTs with forming gas (FG, 5% H2, and 95% N2) annealing is demonstrated. X-ray photoelectron spectra (XPS) show that the number of Ga–O bonds decreases while that of the Ga–N bonds increases, an indication of the surface native oxide removal after FG annealing. Compared with N2 annealing, an increase of two-dimensional electron gas (2DEG) electron density with FG annealing is determined by both energy band simulation and capacitance–voltage measurement. Transmission line measurement (TLM) shows that N2 annealing offers a lower ohmic contact resistance ( ${R}_{\text {C}}$ ) while FG annealing features a lower sheet resistance ( ${R}_{\text {sheet}}$ ). Herein, a FG/N2 two-step ohmic contact annealing is developed to achieve a SS of 110 mV/dec, a transconductance ( ${g}_{\text {m}}$ ) peak of 415 mS/mm, a record low drain-induced barrier lowing (DIBL) of 65 mV/V, and a record high power gain cutoff frequency ( ${f}_{\text {max}}$ ) of 270 GHz on a 50-nm InAlN/GaN HEMT on Si.

Germanium tin (GeSn) with a Sn content of >12% has a great potential for optoelectronic devices due to its direct bandgap property. In this work, the anisotropic etching of GeSn with Sn content of 12.5% and selective etching of Ge over GeSn were explored by inductively couple plasma (ICP) dry etching to obtain various microstructures. Through adding oxygen into chlorine and argon and adjusting the process pressure, the anisotropic etching of GeSn was optimized with an ideal sidewall angle of 89o. The optimized process is compatible with both positive and negative resists. By altering the ICP power, Ge etching recipes with low and high etching rates were developed, which are favorable for fabricating GeSn nano- and micro-structures, respectively. An etching selectivity of >126 for Ge over GeSn with Sn content of >10% can be achieved. With the optimized dry etching recipes, suspended GeSn microribbons and microdisks were realized. Ultimately, the suspended GeSn microstructures were transferred onto 40-nm-thick ZrO2 on p+-Si to form a GeSn-on-insulator (GeSnOI) substrate. For a fabricated 45-nm-thick Ge0.875Sn0.125OI back-gated transistor, the subthreshold swing (SS) of 240 mV/dec is reasonably low for a non-optimized device, suggesting that the explored dry etching methods are promising for device processing.

In this letter, a subthreshold swing (SS) of sub-60 mV/dec is for the first time observed in InAlN/GaN high electron mobility transistors (HMETs). With a 40-nm gate length ( ${L} _{{\text {g}}}$ ), an average SS of 30 mV/dec over three orders of magnitude in drain current ( I d) and a minimum point-by-point SS of 15 mV/dec are achieved. The transistor body factor ( m ) of 4.99/6.98 (in forward/reverse sweep) determined from temperature-variation measurements indicates that the sub-60 mV/dec SS characteristic is not attributed to the negative capacitance effect. The negative differential resistance (NDR) of gate current ( I g) is observed and the hot electron transfer from channel to gate is believed to account for the sub-60 mV/dec SS characteristic. It is further confirmed by the fact that, SS decreases as drain-source voltage ( V ds) increases and L g decreases. Due to the increased V ds and decreased $L_{\text {g,}}$ the channel lateral electric field is strengthened, leading to the hot electron formation and thus the enhanced effect of hot electron transfer on the SS. This sub-60 mV/dec SS characteristic in the nanoscale devices shows the great potential of the InAlN/GaN HEMTs to be applied in future logic switches.

Metal-oxide thin-film transistors (TFTs) promise to enable lightweight and low-power applications, such as ultrathin active matrix displays and low-cost RF identification tags. However, most reported high-performance metal-oxide TFTs contain high-cost indium and gallium elements, leading to constraints in cost-sensitive application. Herein, we present enhancement-/depletion-mode (E-/D-mode) TiO2 TFTs via $\text{O}_{{2}}/\text{N}_{{2}}$ preannealing of TiO2 channel material prior to device fabrication process. It is found that the O2-annealed TiO2 TFTs exhibit improved performances compared to N2-annealed TiO2 TFTs, including increased mobility ( $\mu $ ), higher ON-/OFF-current ratio (ION/IOFF), and lower subthreshold swing (SS). This can be attributed to the passivation effects of O2 annealing, which leads to less oxygen vacancies at the channel and channel/oxide interface. On the other hand, the ionized oxygen vacancies result in the increased electron concentration in N2-annealed films and, thus, the negative shift of ${V}_{\text {th}}$ in the TFT performance. This article delivers a possible approach to improve oxide TFT performance by passivation of oxygen vacancies. Furthermore, the controlled annealing process has a great potential in the logic inverter applications when both E- and D-mode TFTs are implemented.

Dielectric polymer composites consisting of inorganic fillers and polymers have wide applications in high energy density electronic devices. However, development of dielectric polymer composites with enhanced energy storage density and thermal conductivity is desired but challenge. Herein, we report polymer composites consisting of epoxy resin and silver nanoparticle-decorated Al2O3 microspheres (Al2O3-AgNPs), which show enhanced energy storage density and thermal conductivity (1.11 W/m K), at 70 wt% Al2O3-AgNPs. The discharged energy density of Al2O3-AgNPs/epoxy resin composites with 70 wt% hybrid fillers is 4.28 × 10-3 J cm−3, while the composites without AgNPs is 3.09 × 10-3 J cm−3 at 200 kV cm−1. The enhanced energy storage density and thermal conductivity are attributed to the enhanced the interfacial polarization and the bridge role of AgNp in facilitating the heat flow across the interfacial boundary, respectively. The results support the potential applications of the Al2O3-AgNPs/epoxy resin composites used as dielectric materials in modern electronics and electric power systems.

Over decades, the electrical properties of metal oxides have been a myth, stimulating rigorous debate and research. It is commonly accepted that the oxygen vacancy, working as shallow donors, gives rise to the n-type semiconductor behavior in these metal oxides. However, the function of the oxygen vacancy has been doubted, the energy level of which is reported to be far below conduction band to be responsible for the n-type conductivity [1] . In addition, metal oxides with oxygen deficiency in nature is susceptible to the spurious oxidation from the environment, resulting in stability and reliability issue in electronic device. In this work, we observe the conductivity transition from insulator to semiconductor of the stoichiometric TiO 2 films via judicious control of the crystallinity, highlighting the important role of crystallinity in the electrical properties of metal oxide. Based on this observation, high-performance thin film transistors (TFTs) with polycrystalline TiO 2 (poly-TiO 2 ) as the active channel and InAlN/GaN metal-insulator-semiconductor high-mobility-electron-transistors (MISHEMTs) with amorphous TiO 2 (a-TiO 2 ) as the gate dielectrics are demonstrated, indicating the full potential of stoichiometric TiO 2 films as functional electronic materials in device applications.

We report on, for the first time, high-performance, sub-2 volts TiO 2 thin film transistors (TFTs) enabled by ultrathin ZrO 2 gate dielectrics. The effect of ZrO 2 thickness on TFT performance is systematically studied. It is found that the TFT performances are enhanced with the reduced ZrO 2 thickness, benefiting from the increased gate oxide capacitance $(\mathrm{C}_{\text{ox}})$ . The TiO 2 TFTs with an ultrathin ZrO 2 dielectric of 5 nm show a high $\mathrm{I}_{\text{on}}/\mathrm{I}_{\text{off}}$ of $7.7\times 10^{7}$ and a nearly ideal SS of 72 mV under an ultra-low voltage of 2 V. The highperformance, sub-2 volts TiO 2 TFTs show great promise for future portable electronic applications.

Due to the thin InAlN barrier layer, leakage current is a serious problem in InAlN/GaN high-electron-mobility transistors (HEMTs). The InGaN back-barrier can raise the conduction band of the GaN buffer layer and enhance the carrier confinement, resulting in a reduced buffer leakage current. The surface oxidation treatment prior to gate deposition can form an oxide layer and reduce the barrier leakage current. In this study, using both technologies, a record low off current (Ioff) and a record high on/off current (Ion/Ioff) ratio are achieved on InAlN/GaN HEMTs on silicon substrate. The InAlN/GaN HEMT with a 70-nm rectangular gate presents a low Ioff of 7.15 × 10−8 A/mm, a high Ion/Ioff ratio of 2.20 × 107, an average subthreshold swing (SS) of 69 mV/dec, and a low drain-induced barrier lowering (DIBL) of 90 mV/V. The InAlN/GaN HEMT with a 70-nm T-shaped gate exhibits a low Ioff of 3.26 × 10−8 A/mm, a high Ion/Ioff of 4.5 × 107, an average SS of 60 mV/dec, and a DIBL of 30 mV/V. To the best of our knowledge, these are record values among the reported InAlN/GaN HEMTs on Si. RF measurements present that current/power gain cutoff frequency (fT/fmax) of 215/45 GHz and 130/160 GHz are achieved on the 70-nm InAlN/GaN HEMTs with rectangular and T-shaped gate, respectively.

GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted much attention owing to the low-cost and the large area availability of the Si substrate. In this paper, the 90-nm-gate-length InAlN/GaN HEMT on silicon was fabricated and the device electrical properties were studied. The device presents a low drain-induced barrier lowing (DIBL) of 43 mV/V, a parasitic source resistance (RS) of 0.91 Ω⸱mm, and a peak of the intrinsic transconductance (gm0) of 553 mS/mm. To the best of our knowledge, this is the lowest DIBL value among the reported GaN HMET on Si with gate length (Lg ) below 100 nm. The low-filed two-dimensional electron gas (2DEG) electron mobility ( μn) was extracted and the dominated polarization Coulomb field scattering contributed to the increased μn with the increased of two-dimensional electron gas electron density (n2D). A current gain cutoff frequency (fT) of 175 GHz was achieved on InAlN/GaN HEMTs with a gate length of 90-nm.

Recently, oxide-based thin film transistors (TFTs) are considered as a potential alternative to Si -based TFTs in backplane technology for the active-matrix display application due to its good optical transparency and excellent uniformity over large area [1]–[2]. Among all the oxide semiconductors, TiO 2 , with its high transparency to visible light, low-cost growth method, as well as great chemical and mechanical stability, has attracted more attentions [2]–[4]. TiO 2 -based TFTs with appreciable performances have been reported in some previous works, demonstrating their potential in display applications [2]–[6]. Herein, we present high-performance TFTs based on 15 nm ultrathin body TiO 2 with record on/off current ratio of $4.87\times 10^{8}$ and average subthreshold swing (SS) of 129 mV/dec.

In this work, the effects of bis(trifluoromethane) sulfonimide (TFSI) (a superacid) surface treatment on electrical properties of nickel/InAs contacts and InAs material are investigated with transmission line measurements (TLMs). After TFSI treatments on bare InAs TLM patterns, the contact resistance between InAs and Ni contact increased. While for InAs TLM structure passivated with a ZrO2 thin film, the total resistance of InAs decreased drastically after TFSI treatments. X-ray photoelectron spectroscopy measurements revealed that the TFSI reduced the indium oxide at the InAs/ZrO2 interface. This novel passivation method can be adopted in III–V semiconductor device fabrication process to reduce contact resistance and, therefore, enhance device performances, providing a new guidance for III–V fabrication process technology.

In this paper, a post superacid (SA) treatment was proposed to enhance the performance of InAs FinFETs on SiO2/Si substrates. Typically, the subthreshold swing (SS) has reduced from 217 to 170 mV/decade and the transconductance ( ${g}_{m}$ ) has increased from 6.44 to 26.5 $\mu \text{S}/\mu \text{m}$ after SA treatment. It was found that the interfacial In2O3 at the InAs/ZrO2 interface was effectively reduced after SA treatment due to the strong protonating nature of the SA solution. As a result, the interface trap density was reduced leading to a pronounced reduction of sheet resistance after SA treatment. The modeling of transfer characteristics indicates that the carrier mobility is enhanced by 5.8~7.1 folds after SA treatment due to interfacial traps reduction. The results suggest that SA treatment can be potentially extended to other III–V MOSFETs to enhance the device performances.

This paper demonstrates the design strategy in the self-aligned quantum-well InAs MOSFETs with T-shape S/D. A 2-D TCAD simulation is performed based on the experimental data. The effect of air gap between the T-shape metal contacts is taken into account. It is found that the fringing effects induced by the air gap has significant impacts on both DC and RF performances. Further study is carried out based on this TCAD simulation platform. The channel extension region, which is simply considered as part of series resistances, needs to be properly designed to maximize fT and fMAX. RF performances can’t be further improved even if the gate length is aggressively scaled down. However, the reduction of contact resistance can improve fT and fMAX without any limitations. This contact resistance reduction can be realized by incorporating the additional annealing process in the self-aligned gate-last T-S/D process.

A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm-thin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The overlap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 μA/μm2 at $V_{{\rm GS}} = V_{{\rm DS}} = 0.4$ V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K.

In this work, the operation of n- and p-type field-effect transistors (FETs) on the same WSe2 flake is realized,and a complementary logic inverter is demonstrated. The p-FET is fabricated by contacting WSe2 with a high work function metal, Pt, which facilities hole injection at the source contact. The n-FET is realized by utilizing selective surface charge transfer doping with potassium to form degenerately doped n+ contacts for electron injection. An ON/OFF current ratio of >104 is achieved for both n- and p-FETs with similar ON current densities. A dc voltage gain of >12 is measured for the complementary WSe2 inverter. This work presents an important advance toward realization of complementary logic devices based on layered chalcogenide semiconductors for electronic applications.

Low-power, nonvolatile transistors are demanded in the digital electronics development. In our work, molybdenum disulfide (MoS2) acts as the channel material integrated with TiN, which is used as a floating gate to build a floating gate transistor. Our transistor exhibits a large hysteresis of 4 V (Vd = 0.1 V), high on/off ratio of 105, and symmetry writing and erase voltage. The excellent device characteristics such as nondestructive data readout, low operation voltage, and wide memory window inherent in single-layer MoS2 show their great potential to be applied in nonvolatile memory cells.

A systematic study on radiation decontamination in lanthanum oxide production from ion-adsorption rare earth ores in China was conducted. The distribution characteristics of radiation levels during the production process was clarified, and effective measures for radiation decontamination were proposed. The results showed that during the lanthanum oxide production process, radiation would be separated from lanthanum and enter the production wastewater along with calcium, which is easily decontaminated through sodium carbonate precipitation. The percentage decontamination of calcium was close to and less than those of total α and total β, and it could be used for evaluating the percentage decontamination of radiation to ensure that the radiation level is controlled at a low level, as required in practice, instead of waiting for 140 days to analyse the values of total α and total β. Under the optimal condition of maintaining the terminal pH at 8.0–10.0, 99.66% of total α and 99.56% of total β in the production wastewater were decontaminated, and the radiation level of total α and total β could be drastically decontaminated to much lower than the national discharge standard of China, GB8978-1996 (total α

We report an 80-nm-gate-length Inalt;subagt;0.17alt;/subagt;Alalt;subagt;0.83alt;/subagt;N/GaN high-electron mobility transistor (HEMT) on silicon substrate with a record low gate leakage current of 7.12 × 10alt;supagt;-7alt;/supagt; A/mm, a record high on/off current ratio of 1.58 × 10alt;supagt;6alt;/supagt;, and a steep subthreshold swing of 65 mV/dec, which are excellent features among the reported InAlN/GaN HEMTs on Si. Due to the excellent DC performance, a current gain cutoff frequency alt;iagt;falt;/iagt;alt;subagt;Talt;/subagt; of 200 GHz is achieved, resulting in alt;iagt;falt;/iagt;alt;subagt;Talt;/subagt; × alt;iagt;Lalt;/iagt;alt;subagt;galt;/subagt; = 16 GHz μm for GaN HEMTs on Si which to the best of our knowledge is a new record.

(Ga,In)P/GaAsSb DHBTs with different emitter sizes were fabricated with the standard triple-mesa process on wafers with GaInP [Ga] emitter contents of 0, 0.15, 0.24 in the emitter. The effect of the gallium content on the DC and RF characteristics of the DHBTs was studied. It was found that gain increases as the Ga mole fraction increases. This is due to a reduced surface recombination current and intrinsic recombination current with increasing [Ga]. 0.45 × 9.5 μm2 devices with a Ga content of 0.24 show the highest cut-off frequency of 387 GHz. This is attributed to the reducing barrier at the E/B interface, which eases the injection of electrons from the emitter into the GaAsSb base. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

A series of nanostructured iron compounds including cubic Fe3O4 and orthorhombic FeOOH were synthesized via a facile low temperature (in the range of 60−100°C) solution method. In the whole process, the interaction between FeCl2·4H2O and methenamine (C6H12N4) was carried out through a reflux device under different reaction conditions such as temperature, solvent, and duration. The samples were detected by XRD, TEM, SAED, physical property measurement system, and Mossbauer spectroscopy, separately. The experiments showed that magnetic mixture nanoparticles had flake and rod morphologies, and cubic Fe3O4 took on grain nanostructure. Magnetism measurements indicated that the saturated magnetization of the as-obtained magnetic mixture was lower than that of the cubic magnetite. Mossbauer spectroscopy testified the sample consisting of cubic magnetite rather than γ-Fe2O3. In addition, a possible growth mechanism of cubic magnetic nanoparticles under different conditions was discussed.

The static gain characteristics of N–p–N InP/GaAs x Sb 1− x /InP double heterojunction bipolar transistors (DHBTs) were studied as a function of the base arsenic (As) mole fraction x . Compared to the devices with a lattice-matched base ( x = 0.51), a current gain improvement largely arising from a base current reduction is observed in DHBTs with higher As base mole fractions (and consequently a reduced type-II conduction band discontinuity Δ E C at the emitter-base heterojunction). Both the surface periphery and the intrinsic recombination currents decrease markedly as the base arsenic concentration increases. The present work therefore unambiguously demonstrates that the emitter type-II conduction band discontinuity between the InP emitter and the GaAs x Sb 1− x base enhances the undesirable emitter size effects (ESEs) and increases intrinsic recombination currents directly under the emitter contact.

Combining a pseudomorphically strained (Ga,In)P emitter with a GaAs0.6Sb0.4 base effectively eliminates the emitter heterojunction type-II conduction band offset in InP/GaAsSb double heterojunction bipolar transistors (DHBTs). A peak fT of 436 GHz at JC = 10 mA/mum2, with BVCEO = 3.8 V, is achieved with 0.6 times 5 mum2 InP/GalnP/GaAsSb DHBTs with a 75-nm InP collector. Compared to a binary InP emitter, the (Ga,In)P emitter doubles the DC current gain from 166 to 338 for otherwise identical devices. These are the highest DC current gain and cutoff frequencies to date in uniform base GaAsSb DHBTs. The gain improvement reported here will greatly facilitate device design tradeoffs that are encountered while scaling InP/GaAsSb DHBTs toward higher frequencies by allowing higher base doping levels and smaller emitter geometries.

Type-II n-p-n InP/GaAsSb/InP double heterostructure bipolar transistors (DHBTs) that are fabricated by optical lithography with a 0.6 times 5 mum2 emitter on a 20-nm compositionally uniform GaAsSbxSb1-x, carbon-doped base with x = 0.60 and a 75-nm InP collector show current-gain cutoff frequencies as high as 423 GHz at 10 mA/mum2 and feature a BVCEO = 4 V. The pseudomorphic As-rich InP/GaAsSb DHBTs feature a high maximum dc current gain of > 160, owing to the reduction of the type-II conduction band discontinuity DeltaEC and the associated recombination at the InP/GaAsSb emitter-base interface. This brief demonstrates that the InP/GaAsSb DHBT technology can combine high gain, wide bandwidths, high-current drivability, and structural simplicity.

Good-quality metamorphic InP buffer layers have been successfully grown on GaAs substrates by metal-organic chemical vapor deposition. Characterization by atomic force microscope, transmission electron microscopy, high-resolution X-ray diffraction, and Hall measurements indicated that the layers are of high crystalline quality, good mobility, and excellent surface morphology. On this buffer, we demonstrated the first metamorphic InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with good material quality and device performance. Metamorphic DHBTs showed direct-current and radio-frequency characteristics that are comparable to those grown on lattice-matched InP substrates.

Porous SiC ceramics were fabricated without and with Y 2 O 3 addition from SiC, Al 2 O 3 and graphite in air by the in situ reaction bonding process. This process is based on the oxidation of SiC and the mullitization between Al 2 O 3 and oxidation-derived SiO 2 . SiC particles are bonded by the mullite (3Al 2 O 3 ·2SiO 2 ) and SiO 2 . The pores are produced by both stacking SiC particles and burning out graphite. Comparison of phase composition, microstructure, flexural strength, open porosity and pore size distribution of reaction-bonded porous SiC ceramics without and with Y 2 O 3 addition was conducted. Moreover, the effect of Y 2 O 3 content was investigated. Due to the enhancement of neck formation (bonding part between SiC particles) by the addition of Y 2 O 3 , a high strength of 27.5 MPa was achieved at an open porosity of 44.4%.

Raman spectroscopy was used to investigate excimer laser annealing and thickness determination of amorphous silicon (a-Si) layers which are less than 20 nm thick. The a-Si layers wer ep roduced on silicon (Si) substrates using Si + ion implantation with an energy of 10 keV and a dose of 1 × 10 15 cm −2 .E xcimer laser annealing was applied to re-crystallize the a-Si layers. The dependence of re-crystallization on laser fluence was investigated using Raman spectroscopy. A threshold laser fluence of 0. 4Jc m −2 wa sr equired to re-crystallize the a-Si layers. In Raman spectroscopy, the Raman intensity shows a periodical variation with a period of 90 ◦ as a function of the angle between the Si orientation and the laser polarization. Based on this phenomenon, a method to determine nanoscale a-Si film thickness was proposed in two ways. One way was carried out without sample rotation to determine the a-Si thickness provided that the reference c-Si and a-Si/c-Si samples ar ei n the same crystal orientation. The other way was carried out with sample rotation to determine the a-Si thickness without knowing the crystal orientation beforehand.

We report the realization of 0.3-μm emitter InP/GaAsSb/InP DHBTs with cutoff frequencies fT = 365 GHz and fMAX = 501 GHz. Our devices were implemented with a 15-nm C-doped graded base and a 125-nm InP collector and feature a peak current gain β = 35, with a base sheet resistance RSH = 1160 Ω/sq. The present transistors are the first InP/GaAsSb DHBTs to feature fMAX = 500 GHz, according to three extraction schemes. The present transistor performance is limited by an undepleted collector layer associated with a doping tail extending from the subcollector.

We report self-aligned 0.3-μm emitter InP/GaAsSb/ InP DHBTs featuring a common-emitter current gain of 46 and cutoff frequencies fT = 400 GHz and fMAX = 322 GHz for devices implemented with a 20-nm C-doped base and a 75-nm InP collector. Our DHBTs display attractive noise properties with a minimum noise figure NFmin = 1.2 dB at 20 GHz, which is nearly independent of frequency over the 2-20-GHz measurement band. This represents an improvement of at least 2.3 dB with respect to previously published results for GaAsSb-based devices, due to process improvements that allow good RF characteristics to be maintained at the low current levels required for low noise operation. Analysis shows that the low-frequency NFmin is limited by the relatively low current gain values typical of III-V HBTs. InP/GaAsSb DHBTs could be attractive low-noise devices for higher frequencies.

Ripple structures by KrF excimer laser irradiation have been observed on a silicon surface capped with a thin layer of patterned silicon oxide. The ripples are highly dependent on the patterns of the silicon oxide. They are centered and enhanced at the boundaries of the opened windows, forming a radial-wavelike structure. The formation of the ripples is attributed to the combined effect of surface stress, surface scattered wave and boundary effects.

InP/GaAsSb/InP DHBTs with 125 and 150 nm collector thicknesses were fabricated by optical contact lithography in a standard triple mesa process. It is shown that a peak current-gain cut-off frequency f T = 343 GHz and maximum oscillation frequency f MAX = 351 GHz were simultaneously achieved on devices with an emitter area of 0.6 × 11.5 μm2 and a 150 nm collector. To the best of our knowledge, these are the first InP/GaAsSb DHBTs to offer balanced figures-of-merit exceeding 300 GHz and a current gain β > 60. Similar devices with a thinner collector (125 nm) exhibit a peak f T = 377 GHz with f MAX = 318 GHz due to the interplay between a reduced collector transit time and the increased collector-base depletion capacitance. For the devices under study, the extrinsic collector-base capacitance was observed to have a small impact on f MAX . However, the base mesa over-etching is essential to reduce the extrinsic capacitance and thus improve f T .

In response to the continually increasing appetite for bandwidth, most transistor technologies have recently made great strides towards higher cutoff frequencies: Silicon MOSFETs, SiGe HBTs, InP-based HEMTs and a variety of InP -based HBTs all show cutoff frequencies fT and/or fMAX exceeding 300 GHz, and in some cases approaching 800 GHz. Proponents of various technologies have stated that the development of THz bandwidth devices is an attainable milestone for their technology of choice. Such ambitious goals naturally raise the question of whether such performances are in fact realistic given the well-known trends relating breakdown voltages and cutoff frequencies. Can the contending technologies be scaled in a way enabling THz cutoff frequencies while maintaining the well-behaved characteristics of less aggressively scaled previous generations? The present Invited Paper focuses on our efforts to push InP/GaAsSb DHBTs toward THz bandwidths.

The static gain characteristics of NpN InP/GaAsxSb1-x/InP double heterojunction bipolar transistors (DHBTs) were studied as a function of the base arsenic (As) mole fraction x. Compared to the devices with a lattice-matched base (x=0.51), a current gain improvement arising principally from a base current reduction is observed in DHBTs having higher As- base mole fractions (and consequently, with a reduced type-II conduction band discontinuity DeltaEC at the emitter-base junction). Both the surface periphery and the intrinsic recombination currents decrease markedly as the base arsenic concentration increases. The present work therefore unambiguously demonstrates that the emitter type-II conduction band discontinuity between the InP emitter and the GaAsxSb1-x base enhances the undesirable emitter-size effects (ESEs) and increases intrinsic recombination currents directly under the emitter contact.

The impact of growth conditions in the presence of CBr4 is examined for the MOVPE growth of GaAsSb intended for high-performance DHBT applications. We show that the growth is controlled by competing gas phase reactions and by effective V/III flux ratios that can be quite different from those set at the gas inlet. For example, under specific conditions, the C-doping efficiency is shown to increase and then decrease with increasing CBr4 flux.

We describe the realization of ternary base InP/Ga(As,Sb) DHBTs, where the grading is implemented by ramping the base As/Sb composition ratio from the collector to the emitter side: this enables a cutoff frequency fT of 603 GHz at room temperature with a breakdown voltage BVCEO = 4.2 V, for a record fTxBVCEO product of 2.53 THz-V. Device performance improves further with cooling to reach fT ≫ 700 GHz with BVCEO= 4.4 V at 5K. To the best of our knowledge, this represents the highest fT ever reported for a DHBT of any kind. The fTxBVCEO ≫ 3.10 THz-V at 5 K is also unprecedented.

In order to suppress lasing and obtain high superluminescent power, we analyzed the lasing mechanism of integrated devices and three new schemes had been proposed in this paper. More than 300 mW pulsed power was obtained.

Reported is the first experimental microwave noise characterisation of 0.9 times 11.5 mum 2 emitter AlInAs/GaAsSb/InP double heterojunction bipolar transistors with a `type-I` AlInAs emitter. The devices feature cutoff frequencies of f T = 210 GHz and f MAX = 127 GHz, and achieve a minimum noise figure NF min G A = 12 dB at 10 GHz.

In this paper, we investigate the transformation of TiSi 2 from the high-resistivity C40 phase to the low-resistivity C54 phase. In particular, the effect of C40 film thickness on the transition temperature, which has notbeen studied in the literature, is scrutinized. Two types of laser, i.e., Nd:YAG (yttrium aluminum garnet) and excimer laser, were used to induce C40 TiSi 2 on samples of 350 A of Ti deposited on (100) Si substrates. It was also found that the thicker C40 TiSi 2 (40 nm) induced by the Nd:YAG laser required a very high temperature of more than 1000°C and an activation energy of 6.5 eV for the formation of the stable C54 TiSi 2 , whereas a thinner C40 TiSi 2 (15 nm) produced by the excimer laser required a low temperature of 700°C and an activation energy of 2.5 eV to transform into C54 TiSi 2 . The much lower transition temperature for the thin samples is attributed to the compressive strain in these samples.