45 results on '"Tuck, Barbara"'
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2. Testing fully diffused blocks embedded in complex ASICs
3. OVI, IEEE meet on standardization of Verilog HDL
4. The VHDL/Verilog debate continues. How will they share the coveted crown?
5. Analog designers still trail behind their digital counterparts
6. ASIC testability tools force trade-offs in silicon, performance and coverage
7. Technologies move toward hardware/software codesign
8. FPGAs race for the gold in product development
9. Pinouts and performance drive PAL choices
10. What do digital designers need to master the art of analog design?
11. Designers must look beyond the obvious to discover the promise of synthesis
12. High-density ASICs force focus on testability; getting an ASIC of 20,000-plus gates to market on time means building testability into the design flow
13. Network-distributed processing reduces run times for complex designs
14. Are designers' expectations for synthesis realistic?
15. European consumer products replete with mixed-signal, DSP technology
16. High-speed PALs keep pace with today's processors
17. High-density gate arrays: products too far ahead of technology?
18. FPGA, complex PLD vendors rush to support silicon with advanced tools
19. EDA leaders getting serious about automatic test generation
20. ASIC choices increase for mixed 3-V/5-V designs
21. VHDL poised to overtake Verilog as support grows
22. High-level synthesis unlocks potential of FPGAs
23. Chase for process portability prompts advances in cell library tools
24. Denser, faster FPGAs encroach further on masked gate arrays
25. Vendor-independent floorplanner links synthesis with ASIC layout
26. Timing-driven partitioning tool splits design into multiple FPGAs after mapping
27. Split decision on HDLs forces VHDL/Verilog coexistence
28. Claims by FPGA tool vendors bury reality in noise
29. Fault simulator uses cycle-based algorithm
30. 1.25-GHz ECL array has on-chip phased-lock loop
31. Windows 3.0 extends PC-based PLD design limits
32. Verilog HDL simulator targets deep submicron ASIC designs
33. Behavioral synthesis tool generates state machine controller, datapath and memory
34. Floorplanner supports multiple place-and-route tools, block generators
35. FPGA tool features architecture-specific optimization
36. Low-cost VHDL synthesis tool for programmable logic line
37. 0.6-(micron) CMOS ASICs offer system performance solutions
38. Blox eliminates gate-level design for FPGAs
39. VHDL PLD compiler for state-machines
40. Mask-programmed device integrates up to 40 EPLDs
41. FPGA synthesis tool has architecture-specific optimizers
42. Valid integrates PLD and FPGA synthesis within system design
43. Software lets ASIC designers compare FPGAs up front
44. Users want migration path
45. ASIC designers get first Japanese EDA supplier
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