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ASIC advances are forcing us to make radical changes in the way we simulate and sign off silicon. To keep pace with increasing complexity and to achieve the timing accuracy […]

Is BIST the best strategy for embedded memory? Will the overhead for testability be worth it? What are the testability issues for analog blocks? How important is at-speed emulation for […]

This month, Open Verilog International (OVI) presents its case for the standardization of the Verilog hardware description language (HDL), long the de facto standard in the field, to members of […]

Verilog has refused to die and OVI's patrons are breathing new life into it. At the same time, VHDL is thriving in the worldwide arena. Will you have to choose […]

Still dealing with custom more than semicustom, analog designers plod along the trail without the help of synthesis, a standard analog HDL or test methodology. But the determined can still […]

Although testability is finally getting the respect it deserves from both vendors and users, it's clear that if you're designing testability into complex ASICs using today's tools, you'll still have […]

Recent advances in high-level synthesis technology and system verification through reprogrammable hardware emulation have pushed in the direction of hardware/software codesign and promise to enhance your ability to bring error-free […]

Gate arrays and standard-cell ASICs are still the big winners when it comes to product development, but FPGAs are closing in with competitive benefits such as design flexibility, reduced cost […]

Not much has happened with 5-ns-and-faster PAL products since focusing on that technology a year ago (see 'High-speed PALs keep pace with today's processors,' Computer Design, Oct. 1990, p 75). […]

Analog design is still an art because the sophisticated analog specialist is the only one aware of all the nuances and complexity of a design. But for digital and system […]

Synthesis is no longer perceived as a mysterious technology. Rather, it's being recognized as the design methodology that unlocks the silicon opportunities of the 1990s. Designers who have been exposed […]

High-density ASICs force focus on testability High gate counts and maturing software tools have changed the economics of ASIC design. While ever-more-sophisticated tools have automated other tasks, the reliance on […]

The elongated run times of increasingly complex IC and board designs have forced silicon and software vendors alike to chase after network-distributed processing. ASIC designers are finally getting a taste […]

High-speed PALs keep pace with today's processors About the only thing that makers of high-speed PALs agree on is that designers will need parts fast enough to support their 40- […]

Caught up in the integration race, ASIC vendors have pushed silicon beyond the design, assembly and test resources of most OEMs. Advanced processes with submicron geometries have brought to market […]

Because silicon is only as competitive as the tools used to design it, vendors involved in the hot FPGA and complex PLD market have been scurrying to deliver what they […]

The complexity of both silicon and the systems into which it's going is forcing designers to higher levels of abstraction for complex ASICs, and the use of synthesis is putting […]

Leading ASIC vendors have been preparing for the rush to notebook, palmtop and penbased computers by introducing low-voltage cell-based and gate array products. Among the latest to turn out 3-V […]

So far, VHDL's user acceptance is still behind that of Verilog, which is perceived to be a de facto industry standard. Core issues such as the lack of tools and […]

High-level synthesis unlocks potential of FPGAs Field programmable gate arrays (FPGAs) are proving to be not only the hottest technology but also the most unfathomable. Promising close to a magical […]

Chase for process portability prompts advances in cell library tools With the trend toward technology-independent design, library developers require parameterized cell representations that can be modified and reused as design […]

In a market where a product can be a dinosaur 18 months after it's first shipped, design teams are being encouraged to explore alternative, cost-effective technologies to speed product development. […]

A new floorplanning tool for submicron gate arrays, Compass Design Automation's ChipPlanner gives ASIC vendors and designers placement and timing analysis features that bridge the gap between design intent and […]

Prism from NeoCAD is the first timing-driven software tool to provide automatic post-map partitioning of logic functions into multiple FPGAs in the same family. Available as an option to the […]

If you're fed up with arguments concerning the advantages of VHDL over Verilog or vice versa, and you simply want libraries and tools that help get your job done, you […]

Fueled by expectations that by 1995 the field-programmable gate array (FPGA) market will be more than five times what it was last year (consuming 1/3 of the gate array market), […]

The ADAS fault simulator from start-up ADAS Software employs a proprietary algorithm based on parallel differential fault simulation to achieve fast simulation time and reduce hardware memory requirements. With the […]

The Q20P025 ECL array from Applied MicroCircuits offers users digital logic gates and an on-chip phased-lock loop (PLL), with operating frequencies from 200 MHz to 1.25 GHz, to serialize and […]

Programmable logic devices have traditionally been designed on personal computers, but a family of PLDs from Altera Semiconductor (San Jose, CA), with as many as 20,000 gates and 280 pins, […]

Aimed at high-end ASIC designers using deep submicron technologies, the SimLine Verilog HDL simulator from FrontLine Design Automation has several characteristics that distinguish it from Verilog-XL and other Verilog HDL […]

A new behavioral synthesis tool developed by Synopsys can be used for virtually any design that can be described by an algorithm. The Behavioral Compiler is targeted at time-to-market-sensitive ASIC […]

High Level Design (HLD) Systems' Design Planner 2.0 floorplanner for structured custom ICs and ASICs incorporates a backplane that provides access to multiple place-and-route engines and block generators. At this […]

For the first time, Synopsys is shipping a synthesis solution specifically for FPGAS. The FPGA Compiler offers technology-independent synthesis and architecture-specific logic optimization and mapping, as well as state-machine optimization. […]

Unlike its predecessor, whose support was limited to a single device, the Warp2 VHDL compiler from Cypress Semiconductor supports many PLDs and complex PLDs in the company's programmable logic product […]

The 300K ASIC family from LSI Logic is based on a 0.6μm CMOS process and has up to 600,000 usable gates per device. The family includes gate array, cell-based and […]

A synthesis tool from Xilinx called Blox (Blocks of Logic Optimized for Xilinx) eliminates gate-level design entry for FPGAs. With Blox, the FPGA user can describe a design at the […]

The Cypress Semiconductor Warp 1 PLD Compiler uses a subset of VHDL to describe state-machine PLD designs. Specifically, Warp 1 provides high-level language design synthesis support for the Cypress 125-MHz […]

The altera N-to-1 mask-programmed logic device can merge up to 40 erasable programmable logic devices that have been used for prototyping and early production into a single MPLD for volume […]

The AutoLogic field-programmable gate array (FPGA) synthesis tool from Mentor Graphics offers architecture-specific optimization for Xilinx, Actel, and Altera FPGA technologies. Based on Mentor's AutoLogic synthesis product for ASIC and […]

Valid integrates PLD and FPGA synthesis within system design Focusing on programmable logic device and field-programmable gate array synthesis in the context of system design, Valid Logic Systems has integrated […]

Software lets ASIC designers compare FPGAs up front A new translation package from Exemplar Logic promises to be a cost-effective aid for ASIC designers. The FPGA Compiler lets designers analyze […]

Users want migration path The energy level in Silicon Valley is at a more-fevered pitch than usual. And most of that energy is connected in some way to field-programmable gate […]

ASIC designers get first Japanese EDA supplier SAN JOSE, CA--Sometime this quarter, ASIC and full-custom IC designers will for the first time be able to buy framework-based EDA systems from […]