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This paper presents a methodology for designing balanced VLIW architectures. Since we are interested in the architectural aspects of those processors we have developed a framework to evaluate the relationship among the main components of a VLIW machine. Our framework includes the simulator of an actual processor, software tools both to detect the instruction level parallelism of application programs and to generate the parallel object code for each specific machine configuration derived from our basic model of VLIW architecture, and an interpreter which reproduces the behavior of each member of the VLIW family. By interpreting the optimized code derived from a suite of benchmark programs, we have determined the best VLIW configuration for each test program. From these experiments we have discovered which relationship among the machine components should be observed during the specification of a VLIW machine in order to obtain a balanced processor.

This paper presents a study of the impact of conditional branch instructions on the performance of Superscalar processors. By interpreting non-optimised code of a real processor on various configurations derived from a Superscalar architecture model, we have evaluated the execution time percentages in which the associative dispatch algorithm remains idle, waiting for the completion of conditional branch instructions. In addition, we have assessed the volume of instruction level parallelism that can be extracted from application programs if the target machine is equipped with an omniscient branch predictor.

The development of Computer Architectures capable of executing several different instructions per clock cycle is a recent trend in processor design. These machines are called Super-Scalar architectures, and they represent an important member of parallel processors: machines incorporating several independent functional devices that can be programmed to operate in parallel. The main problem regarding this class of architectures is how the machine code should be generated in order to exploit their potential parallelism. This work describes some experiments leading to the generation of parallel code for Super-Scalar machines. The experiments have been carried out with traditional concurrency extraction techniques that have been modified in order to satisfy the requirements of some target machines with low level concurrency. The paper outlines the main details of the project, and shows that speed-up ratios ranging from 1.91 up to 2.91 have been obtained by some versions of our algorithm.

The gap between memory and processor speeds is responsible for the substantial amount of idle time of current processors. To reduce the impact provoked by the so-called "memory gap problem," many, software techniques (e.g., the code layout reorganization) together with hardware mechanisms (cache memory, translation look-aside buffer branch prediction, speculative execution, trace cache, instruction reuse, and so on) have been successfully implemented. In this paper we present some experiments that explain why these mechanisms and techniques are so efficient. We found that only a small fraction of the object code is actually executed: our experiments disclosed that more than 50% of the instructions remain untouched during the whole execution, and the percentages of basic blocks which remain unused are slightly greater. In addition to the usage of instructions and blocks, the paper provides further insights regarding the behavior of application programs, and gives some suggestions for extra performance gains.

In an earlier work we have introduced an Architecture Description Language (ADL for short) and its support system implemented in a machine-independent fashion [5]. This system provides facilities for teaching and research in computer architecture: target machines described in ADL are fed into the support system, and the corresponding interpreter programs are automatically generated. These programs reproduced the run-time environment of the target, as specified by the ADL description, including the interpretation of the target code. This paper presents a brief review of the language and the implementation of its support system. Next, the new constructs that have been incorporated into ADL to give an extended version (ADL-X) are described. Through these mechanisms, designers can specify and synchronize target machine activities occuring in parallel. Finally, we show how the new support system is being implemented, and give a description of a pipeline machine, using the new language features.