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This paper proposes a delta-sigma modulator (DSM) for audio band applications with low-area cost and high-resolution performance characteristics. The proposed circuit is implemented by discrete-time switched capacitor circuits. It employs an assisted 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) as the quantizer. Most importantly, it combines and shares the resistive digital-to-analog (DAC) in DSM and SAR ADC. Therefore, it can achieve high-efficiency advantages and reduce the chip layout cost. After all, the chip area is only 0.096 mm2 by the 0.18 um 1P6M CMOS process. It achieves 96 dB dynamic range (DR), 83.1 dB signal to noise and distortion ratio (SNDR), and 93.4 dB signal to noise ratio (SNR) with 25 kHz signal bandwidth and oversampling ratio (OSR) of 64. [ABSTRACT FROM AUTHOR]

Recently, with the aim of extending the use of the CP in all those applications where a time-variant signal must be amplified with its DC component above the positive power supply rail, the signal amplification feature of a conventional Dickson charge pump (CP) has been investigated, introducing a small-signal model for each particular condition in which a CP can work. In this paper this idea is further investigated, especially under the slow switching limit (SSL) condition, and experimental validation has been carried out using a 65 nm CMOS technology for four different voltage gain values. Starting from an equivalent model of the CP, the main small- and large-signal parameters are analytically derived and discussed in depth. As a proof of concept, experimental measurements on four CPs with different numbers of stages confirm the validity of this unconventional application and the effectiveness of the CP when used as an amplifier. [ABSTRACT FROM AUTHOR]

This article proposes a fully dynamic, low-power, wideband, time-interleaved (TI), noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) based on the cascade of integrators with feedforward (CIFF) architecture. Both the interleaving operation and the loop filter are implemented by using the fully passive switched-capacitor circuits. The feedforward summation is realized by a multi-path dynamic comparator. The overall noise transfer function (NTF) is highly robust against process, voltage, and temperature (PVT) variations since the NTF is determined by device ratios. This allows the NTF zeros to be close to 1, with a good NS effect. Compared with a recently published TI NS SAR based on the error-feedback (EF) architecture, this work does not need a static amplifier, thus leading to the fully dynamic operation. Meanwhile, it eliminates the dependence of NTF on the PVT-sensitive amplifier gain. Implemented in a 40-nm CMOS process, the prototype ADC achieves an SNDR of 69.1 dB, a bandwidth of 50 MHz, and a power consumption of 8.5 mW under a 1.1-V supply, leading to a Walden FoM of 36.3 fJ/conv.-step. [ABSTRACT FROM AUTHOR]

This paper presents a 4-bit, 2–2 multi-stage noise shaping (MASH) delta-sigma modulator (DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The DSM was designed using a cascade-of-integrators with a feedforward (CIFF) structure. The first integrator was designed to reduce the loading effect of the system's front-end circuit using a switched-resistor integrator instead of the conventional switched-capacitor method. The CIFF structure requires an active adder, which is generally implemented with a high-bandwidth high-swing amplifier. In this paper, the active adder is eliminated and an adder-less integrator is implemented in the MASH DSM. The DSM prototype has an over-sampling ratio (OSR) of 16 and a 160 MHz sampling frequency. The prototype's measured signal-to-noise ratio (SNR) is 82.4 dB and the signal-to-noise-plus-distortion ratio (SNDR) is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm2. The energy required per conversion step is 0.4 pJ/conv. [ABSTRACT FROM AUTHOR]

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter “doubles” the supply voltage to all the digital circuitry and particularly regulates the time-to-digital converter (TDC) supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, and temperature (PVT). The ADPLL supports a two-point modulation and forms a Bluetooth low-energy (BLE) transmitter realized in 28-nm CMOS. It maintains in-band PN of −106 dBc/Hz [figure of merit (FoM) of −239.2 dB] and rms jitter of 0.86 ps while dissipating only 1.6 mW at 40-MHz reference. The power consumption reduces to 0.8 mW during the BLE transmission when the DCO switches to open loop. [ABSTRACT FROM AUTHOR]

This paper presents an inductorless dual-output switched-capacitor DC-DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The switched capacitor DC-DC converter was implemented in a standard 0.18-μm 3.3-V CMOS process. Measurements were used to verify that the proposed converter provides dual independently regulated output voltages without cross regulation. The two outputs were regulated at 2.5 and 0.8 V with input ranges of 1.7-2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz, and a maximum power efficiency of 92.1% was achieved for a total output power of 210 mW. The maximal peak-to-peak output ripple voltages for the two outputs at 100 mA load currents were suppressed to below 26 and 20 mV, respectively. [ABSTRACT FROM AUTHOR]

This research paper focuses on the design, development and implementation of a pipelined analog to digital (A/D) converter of 8 bits with sampling rate of 25 MHz in 350 nm CMOS process technology. The architecture utilizes the digital correction for each stage based on a 1.5 bit per stage structure. A differential switched capacitor circuit consisting of a cascade gm-C op-amp with 200 MHz ft is used for sampling and amplification in each stage. Differential dynamic comparators are used to implement the decision levels required for the 1.5 bit per stage structure. Correction of the pipeline is accomplished by using digital correction circuit consist of D-latches and full adders. Finally, the paper describes the floorplan and layout of design. [ABSTRACT FROM AUTHOR]

A low-voltage low-power Sigma-Delta modulator for health monitoring system is designed using a standard 0.18m CMOS technology. To achieve high accuracy with low power consumption in low supply voltage environment, the designed modulator is implemented with a one-bit third-order topology, in which the input-feedforward structure and switched-opamp (SO) technique are combined. Using the proposed design method, the SO meets the system requirements with the minimal power consumption and good stability in a feedback loop. The modulator achieves 86dB dynamic range (DR) over a 300Hz bandwidth with an oversampling ratio (OSR) of 128, while it occupies 0.16mm2 and consumes 12W under a 1.1V supply. [ABSTRACT FROM AUTHOR]

A new model to predict the dynamic behavior of a self-timed autonomous digital system powered by a capacitor is derived. The model demonstrates the hyperbolic shape of the discharging process on the capacitor. It allows a symbolic analysis of the discharging process for complex digital loads comprised of series (stack) and parallel configurations of digital circuits. For example, for a stack configuration, important non-trivial relationships between the hyperbolic discharging rates have been derived based on the knowledge of the velocity saturation index (alpha) of the semiconductor devices used in the digital part. For a realistic (modern complementary metal oxide semiconductor (CMOS) devices) value of alpha = 1.5, the discharging process for a stack of two identical circuits proceeds nearly three times slower than that of any of the stand-alone circuits. This shows a potential way of extending the lifetime of the energy sources by means of stacking self-timed circuits. Although the analysis is based on configurations consisting of ring oscillators in CMOS technology, the analysis method can be extended to other types of self-timed systems and other semiconductor technologies in which the instantaneous switching activity of the digital load is determined by the instantaneous voltage levels provided by the capacitive power transfer mechanism. The analytical derivations have been validated by simulations and experiments carried out with real hardware. © 2014 The Authors. International Journal of Circuit Theory and Applications published by John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper presents a 2:1 low power switched-capacitor DC-DC converter designed in $$180$$ nm Standard CMOS technology. The converter operates from $$1.8$$ V input and delivers a $$0.8$$ V power supply with $$50$$ mA load current. Simplicity and power efficiency improvement is the main goal of this design. The achieved efficiency of the converter is more than $$80\,\%$$ . Also, high power efficiency, high current delivery, small size, low output voltage ripples are some main properties of the proposed DC-DC converters. The converter occupies about an area of $$1$$ mm $$^2$$ . Besides, switching frequency of the switched-capacitor DC-DC converter has been increased to reduce output voltage ripples. Maximum output voltage ripple is about $$21$$ mV. Power saving in gate driver stage is the method used in this design to improve the power efficiency. Also, a little changes applied in non-overlapping clock signal generator to gain a better power efficiency. During the design procedure, the main power loss sources have been explained and their solutions have been presented. [ABSTRACT FROM AUTHOR]

Switch conductance modulation techniques are demonstrated in a fully integrated multi-ratio switched-capacitor voltage regulator with hysteretic control, in 22 nm tri-gate CMOS with high-density MIM capacitor. We present (i) an adaptive switch-size scaling scheme for maximum efficiency tracking across a wide range of voltages and currents, governed by a frequency-based control law that is experimentally validated across multiple dies and temperatures and, (ii) a simple active ripple mitigation technique that modulates the gate drive of select MOSFET switches effectively in all conversion modes. Efficiency improvements up to 15% are measured under low output voltage and load conditions. Load-independent output ripple of < 50 mV is achieved, enabling reduced interleaving. Test chip implementations and measurements demonstrate ease of integration in SoC designs, power efficiency benefits and EMI/RFI improvements. [ABSTRACT FROM PUBLISHER]

A power-efficient wireless switched-capacitor based stimulating (SCS) system for electrical/optical deep brain stimulation (DBS) is presented. The SCS system efficiently charges storage capacitors directly from an inductive link and delivers accurately balanced charge to the tissue, improving the overall stimulator efficiency. In addition, the decaying exponential stimulus pulses generated by SCS can be more effective than conventional rectangular and ramp stimuli in activating neural tissue when consuming the same amount of energy, leading to higher stimulus efficacy. A 4-channel wireless SCS system in 0.35 µm CMOS process achieves stimulator efficiency of 80.4% with capacitor pairs charged to ±2V, while the decaying exponential stimulus requires equal or less stimulus energy and injected charge than other stimuli depending on pulse width to activate the same tissue area. The SCS system has also been utilized for power-efficient wireless optogenetic stimulation by periodically discharging capacitors into high-current micro-LED arrays. Results from acute in vivo experiments have verified the utility of the SCS system prototype in both electrical and optical stimulation. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a comparator-based switched-capacitor (CBSC) architecture using a multi-level input tracking preset voltage scheme. The CBSC is used to compensate for technology scaling and to reduce the power consumption of a 2.8 MS/s 10-bit cyclic analog-to-digital converter (ADC). A multi-level preset voltage tracks the input voltage in order to improve the conversion rate without consuming additional power. Additionally, a comparator, current sources, and a feedback capacitor are shared to reduce the power and area of this cyclic ADC. Near the Nyquist-rate, a prototype implemented in 0.18 μm CMOS technology has a signal-to-noise and distortion ratio of 53.69 dB and a spurious-free dynamic-range of 62.36 dB, while consuming 0.73 mW of power. [ABSTRACT FROM AUTHOR]

A 16 Gb/s I/O link receiver fabricated in 22 nm CMOS SOI technology is presented. Attenuation and ISI of transmitted NRZ data across PCB channels are equalized with a CTLE feeding an 8-tap DFE. The first tap uses digital speculation and the following seven taps are realized by means of the switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud-rate CDR. The architecture is half-rate and requires one phase rotator. In total, each slice has six comparators to recover data and timing information. The second-order digital CDR operates at quarter-rate and features a low-latency implementation of the proportional path. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization is recovered across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 31 kppm (16 GHz ± 496 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered (BER < 10^-12) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver. [ABSTRACT FROM AUTHOR]

A novel “quad-path” radiation hardening technique is implemented in a switched-capacitor sample/hold amplifier and validated by laser testing. The proposed technique eliminates the signal-range limitations of the original dual-path hardening technique by using both n- and p-type switches with separate dual and complementary signal paths. Single-event effect sample errors are reduced by up to 90%, with minimal speed, power and area penalties. [ABSTRACT FROM PUBLISHER]

A fully integrated high power density capacitive 2:1 step-down DC–DC converter is designed in a standard CMOS technology. The converter implements the presented flying well technique and intrinsic charge recycling technique to deliver a maximum output power of 1.65 W on a chip area of 2.14 mm^2, resulting in a power conversion density of \0.77\, \W/mm^2. A peak power conversion efficiency of \69\\% is achieved, leading to an efficiency enhancement factor of +\36\\% with respect to a linear regulator. This is for a voltage step-down conversion from twice the nominal supply voltage of a \90 nm technology (\2V{\bf dd} = \2.4\, \V) to \1\, \V. [ABSTRACT FROM AUTHOR]

The traditional inductor-based buck converter has been the default design for switched-mode voltage regulators for decades. Switched capacitor (SC) dc–dc converters, on the other hand, have traditionally been used in low-power (<10 mW) and low conversion ratio (<4:1) applications where neither regulation nor efficiency is critical. This study encompasses the complete successful design, fabrication, and test of a CMOS-based SC dc–dc converter, addressing the ubiquitous 12–1.5 V board-mounted point-of-load application. In particular, the circuit developed in this study attains higher efficiency (92% peak, and >80% over a load range of 5 mA to 1 A) than surveyed competitive buck converters, while requiring less board area and less costly passive components. The topology and controller enable a wide input range of 7.5–13.5 V. Controls based on feedback and feedforward provide tight regulation under worst case line and load step conditions. This study shows that the SC converter can outperform the buck converter, and thus, the scope of SC converter application can and should be expanded. [ABSTRACT FROM AUTHOR]

Abstract: In this work, a 10-bit dual-plate sampling capacitive DAC with a capacitor reuse on-chip reference voltage generator is proposed. Instead of using the conventional two element switched-capacitor circuit that consists of the charge sampling and summing capacitors, the proposed dual-plate sampling scheme performs the identical operation using a single capacitor. As a result, the capacitor area can be significantly reduced compared to conventional capacitive DACs. Furthermore, the capacitor reuse reference voltage generator does not add much area and power overhead, and the reference amplifier offset cancellation alleviates the reference matching requirements. The proposed DAC is implemented using the CMOS 0.35µm technology with core size of 0.11mm2 and power consumption of 0.8mW for conversion rate of 1.75MS/s. The maximum INL and DNL showed 0.89LSB and 0.47LSB, respectively. [Copyright &y& Elsevier]

In this paper, a new second-order discrete-time ΔΣ ADC using a noise-shaped two-step integrating quantizer is presented. The first quantization step (coarse) is utilized with a flash ADC. The second quantization step (fine) is implemented using a noise-shaped integrating quantizer. As a result, both high resolution and first-order noise shaping is achieved. High quantization resolution enhances the modulator stability whereas the extra order of noise-shaping improves the overall performance. The proposed ΔΣ ADC incorporating the noise-shaped two-step integrating quantizer manifests a second-order noise-shaping with a first-order loop filter. To accommodate the large number of quantization levels of the feedback-DAC, a new feedback topology is presented which uses both analog and digital signals. The prototype ADC is implemented in 0.13 µm CMOS and demonstrates peak SNDR of 70.7 dB while consuming 8.1 mW under a 1.2 V supply, with an OSR of 8 at 80 MHz sampling frequency. [ABSTRACT FROM AUTHOR]

This paper presents a precision mismatch measurement method to characterize an integrated capacitor array. Conventional mismatch measurement methods using floating gate capacitance measurement (FGCM) have measurement error due to the large input-referred noise and the small input signal range of the source follower. In order to improve the measurement accuracy, we propose a new measurement method using a parasitic-insensitive switched capacitor amplifier and the correlated double sampling (CDS) technique. The CDS technique eliminates the measurement error from parasitic capacitances, switching errors, and the offset voltage of the amplifier. In order to verify the proposed method, a test chip was fabricated using a 0.18-\mmb\mum CMOS process. The chip consists of a 4\,\times\,16 metal–insulator–metal capacitor array and a measurement circuit. The measured standard deviation of the capacitance mismatch, \sigma(\DeltaCn{{<}C{>}}), ranges from 0.0067% to 0.0130%, and the measured standard deviation of the short-term repeatability, \sigma(\Delta (\DeltaCn/{<}C{>})), is 0.0025%. These results show that the measurement accuracy of the proposed method is improved by ten times over that of the FGCM method. [ABSTRACT FROM PUBLISHER]

A 64\,\times\,64-pixel ultra-low power vision sensor is presented, performing pixel-level dynamic background subtraction as the low-level processing layer of an algorithm for scene interpretation. The pixel embeds two digitally-programmable Switched-Capacitors Low-Pass Filters (SC-LPF) and two clocked comparators, aimed at detecting any anomalous behavior of the current photo-generated signal with respect to its past history. The 45 T, 26 \mum square pixel has a fill-factor of 12%. The vision sensor has been fabricated in a 0.35 \mum 2P3M CMOS process, powered with 3.3 V, and consumes 33 \muW at 13 fps, which corresponds to 620 pW/frame.pixel. [ABSTRACT FROM PUBLISHER]

The present work analyses the non-ideal effects of pipelined analog-to-digital converters (ADCs), also sometimes referred to as pipeline ADCs, including the non-ideal effects in operational amplifiers (op-amps or OAs), switches and sampling circuits. We study these nonlinear effects in pipelined ADCs built using CMOS technology and switched-capacitor (SC) techniques. The proposed improved model of a pipelined ADC includes most of the non-idealities which affect its performance. This model, simulated using MATLAB, can determine the basic blocks specifications that allow the designer to meet given data converter requirements. [ABSTRACT FROM AUTHOR]

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS analog-to-digital converter (ADC) for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate gain mismatches within channels. Moreover, the channel offset mismatches are calibrated through the digital- controlled corrective current sources embedded in the track-and-hold amplifiers of each sub-ADC. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm^2 chip area and consuming 40 mW at 2.2 GS/s from a 1 V supply. Measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate. The effective number of bits (ENOB) is 6.0 bits at Nyquist rate, and the figure-of-merit (F.O.M.) is 0.28 pJ/conv.-step. This prototype has also been integrated into a gigabit self-healing wireless transceiver SoC. [ABSTRACT FROM AUTHOR]

A dynamic comparator-based OTA is introduced as a replacement for a conventional OTA. It performs charge transfer in a switched-capacitor circuit by repeatedly evaluating the polarity of the differential input using a dynamic clocked comparator and injecting current pulses at the output to move the input voltage toward zero. The amplitude of the current pulse is reduced each time the input voltage crosses zero to provide fast but accurate settling of the output voltage. Dynamic comparator-based OTAs are applied to the design of a 1-1-1-1 MASH delta-sigma modulator. The 65-nm CMOS prototype achieves a 70.4 dB peak SNDR over a 2.5-MHz bandwidth while consuming 3.73 mW from a 1.2-V supply. The 276-fJ/conv-step FoM represents a four times improvement over previously-reported delta-sigma modulators using zero-crossing-based circuits or comparator-based switched capacitors. Because of the dynamic operation of the OTAs and discrete-time delta-sigma modulator architecture, both bandwidth and power consumption linearly scale with the sampling frequency without any reconfiguration of the modulator. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a merged two-stage dc-dc power converter for low-voltage power delivery. By separating the transformation and regulation function of a dc-dc power converter into two stages, both large voltage transformation and high switching frequency can be achieved. We show how the switched-capacitor stage can operate under soft charging conditions by suitable control and integration (merging) of the two stages. This mode of operation enables improved efficiency and/or power density in the switched-capacitor stage. A 5-to-1 V, 0.8 W integrated dc-dc converter has been developed in 180 nm CMOS. The converter achieves a peak efficiency of 81%, with a regulation stage switching frequency of 10 MHz. [ABSTRACT FROM PUBLISHER]

Here, we propose an integrated hybrid DC–DC converter suitable for high drop-out energy conscious applications. In the hybrid converter topology, along with a linear regulator two switched capacitors are used to store and recycle charge for better power efficiency. Without significant power loss the switched capacitors step down the supply voltage for the linear regulator working in low drop-out mode. The linear regulator, on the other hand, attenuates the voltage ripple that originates from the switched capacitors converter on its power supply rejection ratio. It also helps for line and load regulation. Additionally, a synthesised counter ripple is injected through the linear regulator to further reduce the output ripple. With these two techniques, for a moderate load current and an acceptable output ripple, the switching and load capacitors are reduced to a value which can be implemented within the chip. The proposed integrated converter circuit has been designed, implemented and tested in a 0.18 mm CMOS process for 3.3–1.3V conversion. With two switching capacitors of 210 pF each and 100 pF load capacitor, more than 13 mA of load current, measured peak-to-peak output voltage ripple is 146 mV. The achieved measured power efficiency is 64.97%. Exhaustive silicon characterisation of the converter is done to observe the power efficiency and ripple variation at different frequency of operations. [ABSTRACT FROM AUTHOR]

The work deals with the design of the 12-bit Delta-Sigma (ΔΣ) modulator using switched capacitors (SC) technique. The modulator serves to vibration sensor output processing. The first part describes the ΔΣmodulator parameters definition. Results of the proposed topology ideal model were presented as well. Next, the ΔΣ modulator circuitry on the transistor level was done. The ONSemiconductor I2T100 0.7 µm CMOS technology was used for design. Then, the Δ Σmodulator nonidealities were simulated and implemented into the MATLAB ideal model of the modulator. The model of real ΔΣ modulator was derived. Consequently, modulator coefficients were optimized. Finally, the corner analysis of the ΔΣ modulator with the optimized coefficients was simulated. The value of SNDR = 82.2 dB (ENOB = 13.4 bits) was achieved. [ABSTRACT FROM AUTHOR]

This paper presents a 0.5-V 1.5-bit double-sampled \Delta\Sigma modulator for audio applications. Unlike existing double-sampled designs, the proposed double-sampled \Delta\Sigma modulator employs an input-feedforward topology to reduce internal signal swings, thereby relaxing design requirements for the low-voltage building blocks and reducing distortion. Moreover, in order to avoid instability and noise shaping degradation, the proposed architecture restores the noise transfer function (NTF) of the double-sampled modulator to its single-sampled equivalent with the help of compensation loops. In the circuit implementation, the proposed fully-differential amplifier adopts an inverter output stage and a common-mode feedback (CMFB) circuit with a global feedback loop in order to reduce power consumption. A resistor-string-reference switch matrix based on a direct summation quantizer is used to simplify the analog compensation loop. The chip prototype has been fabricated in a 0.13-\mum CMOS technology with a core area of 0.57 \mm^2. The measured results show that when operating from a 0.5-V supply and clocked at 1.25∼MHz, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 81.7 dB, a peak signal-to-noise ratio (SNR) of 82.4 dB and a dynamic range (DR) of 85.0 dB while consuming 35.2\ \mu\W for a 20-kHz signal bandwidth. [ABSTRACT FROM AUTHOR]

An ultra-low voltage switched-capacitor (SC) \Delta\Sigma converter running at a record low supply voltage of only 250 mV is introduced. System level aspects are discussed and special circuit techniques described, that enable robust operation at such a low supply voltage. Using a SC biasing approach, inverter-based integrators are realized with overdrives close to the transistor threshold voltage Vth while compensating for process, voltage and temperature (PVT) variation. Biasing voltages are generated on-chip using a novel level shifting circuit, that overcomes headroom limitations due to saturation voltage Vsat. With an oversampling ratio (OSR) of 70 and a sampling frequency (fS) of 1.4 MHz at 250 mV power supply the converter achieves 61 dB SNDR in 10 kHz bandwidth while consuming a total power of 7.5 \mu\W. [ABSTRACT FROM AUTHOR]

This paper describes a new analog-to-digital converter based on the traditional dual-slope ADC operation. With a small modification to the discharging phase of the dual-slope ADC, first-order quantization noise shaping is achieved. This quantizer is used in a second-order loop filter and results in an overall third-order quantization noise shaping. To remove the need for any extra active element, this quantizer is merged with the active adder. In this fashion, the multi-bit flash ADC is removed and hence the loading of the active-adder is reduced to a single continuous-time comparator. Furthermore, to alleviate the speed of the counting-clock and the common-mode biasing accuracy requirements, a bi-directional discharging scheme is proposed. As a proof of concept, the second-order loop filter with the proposed quantizer is fabricated in a 0.18 \mu\m CMOS technology and achieves over 78 dB SNDR with an oversampling ratio of 24 and 50 MHz sampling speed. The power consumption is 2.9 mW from a 1.5 V power supply. [ABSTRACT FROM AUTHOR]

A 1–4-GHz 4-element phased array receiver front-end demonstrates spatial interferer rejection using null steering. Element phase and amplitude control are performed by a switched-capacitor vector modulator with integrated downconversion, utilizing a rational sine/cosine approximation. The 65-nm CMOS receiver achieves more than 20 dB of spatial interferer rejection up to an angular separation of 15^\circ. [ABSTRACT FROM AUTHOR]

Switch capacitor DC-DC converter is an emerging concept for high dropout application. This paper discusses techniques for output voltage ripple reduction of an embedded dual-switch capacitor - linear regulator-based hybrid DC-DC converter. In spite of deploying the advantage of PSRR property of the linear regulator, the ripple at the output of the convertor is still high. To alleviate this, a new technique of further reduction of the output ripple by introducing synthesised counter ripples through the linear regulator is presented. The conventional and new technique of ripple reduction has been analysed with the help of small signal equivalent circuits. These techniques have been implemented with a hybrid converter for 3.3 V-to-1.35 V conversions. A test chip is fabricated in a 0.18-µm standard digital CMOS process to demonstrate the efficacy of the proposed technique. It is found that the trend of ripple reduction by ripple synthesiser in measured results is consistent with the simulation results and also observed in the measured results that the ripple synthesiser reduces the output ripple of a hybrid converter by the factor of 0.52 and 0.45 for the load current of 2.2 mA and 7.3 mA, respectively. [ABSTRACT FROM AUTHOR]

This paper presents the design and experimental results of a low-power multi-band RF receiver including a multi-band low-noise amplifier (LNA) and a down-conversion mixer based on the IEEE 802.15.4 standard for sensor node applications. A multi-band LNA with two inputs is tuned to two resonant frequencies by controlling the voltage on a switched MOS. The implemented RF receiver front-end achieves a maximum voltage conversion gain of 38 and 30 dB, NF of 6.2 and 9.2 dB at the 868/915 MHz and the 2.45 GHz bands, respectively. The RF receiver front-end dissipates total 3.0 mA (including I/Q mixers) under supply voltage of 1.8 V at both operation bands. [ABSTRACT FROM AUTHOR]

This manuscript presents a 0.5-V audio-band continuous-time Delta-Sigma modulator with a new method implementing switched-capacitor-resistor (SCR) feedback to reduce clock jitter-induced noise. An ultra-low voltage (ULV) amplifier with self-compensated CMFB loop is used to meet the stricter amplifier speed required by SCR feedback. Fabricated in a 0.13 μm CMOS process, the modulator achieves a peak SNDR of 81.2 dB over 25-kHz signal bandwidth and consumes 625 μW at 0.5-V supply. [ABSTRACT FROM AUTHOR]

An ultra low-power, precise voltage reference using a switched-capacitor technique in 0.35-\mum CMOS is presented in this paper. The temperature dependence of the carrier mobility and channel length modulation effect can be effectively minimized by using 3.3 and 5 V N-type transistors to operate in the saturation and subthreshold regions, respectively. In place of resistors, a precise reference voltage with flexible trimming capability is achieved by using capacitors. When the supply voltage is 1 V and the temperature is 80 ^\circC, the supply current is 250 nA. The line sensitivity is 0.76%/V; the PSRR is - 41 dB at 100 Hz and - 17 dB at 10 MHz. Moreover, the occupied die area is 0.049 mm^2. [ABSTRACT FROM PUBLISHER]

MEMS-based oscillators have recently become a topic of interest as integrated alternatives are sought for quartz-based frequency references. When seeking a programmable solution, a key component of such systems is a low power, low area fractional-N synthesizer, which also provides a convenient path for compensating changes in the MEMS resonant frequency with temperature and process. We present several techniques enabling efficient implementation of this synthesizer, including a switched-resistor loop filter topology that avoids a charge pump and boosts effective resistance to save area, a high gain phase detector that lowers the impact of loop filter noise, and a switched capacitor frequency detector that provides initial frequency acquisition. The entire synthesizer with LC VCO occupies less than 0.36~sq. mm in 0.18 \mum CMOS. Chip power consumption is 3.7~mA at 3.3 V supply (20 MHz output, no load). [ABSTRACT FROM AUTHOR]

Abstract: The impact of operational amplifier (op-amp) phase margin on switched-capacitor (SC) sigma-delta modulator (ΣΔΜ) performance is investigated in this paper. An ad-hoc integrator settling model is developed and verified by circuit simulations performed in a commercial 0.35μm CMOS technology. The model allows the effect of op-amp phase margin to be taken into account in ΣΔΜ behavioural analysis. Behavioural simulations of a typical single-bit second-order modulator are presented, as an example. As shown, the proposed analysis allows well-found specifications for the op-amp unity-gain frequency, slew rate and phase margin to be defined since the preliminary behavioural simulation phase. [Copyright &y& Elsevier]

The opamp in the first integrator of a high resolution single-bit continuous-time ΔΣ modulator has stringent slew rate requirements, which increases power dissipation. We introduce the "assisted opamp" integrator, which is a way of achieving low distortion operation with low power consumption. We present circuit implementations of our technique for single-bit modulators using NRZ and switched-capacitor-resistor (SCR) feedback DACs. Audio modulators designed in a 0.18 µm CMOS technology are used as vehicles to demonstrate the effectiveness of our techniques. The modulator with an NRZ DAC achieves a dynamic range of 92.5 dB in a 24 kHz bandwidth and dissipates 110 µW froma 1.8 V supply. A second design, which employs an SCR-DAC, achieves a dynamic range of 91.5 dB and dissipates 122 µW. The figures of merit (FOM) of these modulators, 175.9 dB and 174.4 dB respectively, are comparable with those of state-of-the-art multibit designs. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and optimization for conventional Comparator- Based Switched-Capacitor (CBSC) gain-stage, and proposes a solution to modify the tight tradeoff between accuracy, speed, and input swing by interposing a middle-phase in charge-transfer mode. The required digital controller for current sources and comparators in the modified CBSC gain-stage are described, and its performance is compared to that of conventional CBSC gainstage. Simulation, using a TSMC 0.13-μm CMOS-technology with IV power-supply, shows that the modified structure improves the accuracy by typically 1.5bits, and lowers the settling time by 15% without extra power dissipation. [ABSTRACT FROM AUTHOR]

This paper addresses design strategies and tradeoffs of a series of newly developed interleaving switched-capacitor power converters. In such a design, a converter consists of multiple sub-cells in the power stage, and is regulated with interleaving power flow control. By splitting the power flow in a time-sequenced manner, the converter maintains a continuous power delivery flow to the output VOUT, with significant reductions on the in-rush input current and the output voltage ripples. System modeling and optimization focusing on power efficiency and z-domain closed-loop gain enhancement are discussed. An experimental prototype was successfully fabricated with a standard 0.35-µm digital CMOS N-well process. The entire die area, including fully integrated pads and power devices, is 3.84 mm². Measurement results show that, with a supply voltage of 1.5 V and a load of 250 mA, the output of the converter is well regulated at 2.5 V with 16-mV ripple. The maximum efficiency of 82.3% is achieved at the output power of 625 mW. [ABSTRACT FROM AUTHOR]

Since the first demonstration of a comparator-based switched-capacitor circuit, analog-to-digital (A/D) converters based on virtual ground detection have made steady and significant progress. Comparators have been replaced by zero-crossing detectors, leading to the development of zero-crossing based circuits for faster speed and lower power. All facets of performance including the sampling rate, effective number of bits, noise floor, and figure-of-merit have improved substantially. This paper focuses on recent implementations of zero-crossing based A/D converters and discusses the technical issues unique to these A/D converters as well as solutions that have been developed to improve their performance and practicality. A series of prototype designs whose performance ranges from 8 bit, 200 MS/s to 12 bit, 50 MS/s are described. The ultimate low power potentials of these A/D converters are compared with various different types of complementary metal-oxide-semiconductor A/D converters from a fundamental thermal noise standpoint. [ABSTRACT FROM AUTHOR]

We report on a CMOS-based microelectrode array (MEA) featuring 11,011 metal electrodes and 126 channels, each of which comprises recording and stimulation electronics, for extracellular bidirectional communication with electrogenic cells, such as neurons or cardiomyocytes. The important features include: (i) high spatial resolution at (sub)cellular level with 3150 electrodes per mm2 (electrode diameter 7 μm, electrode pitch 18 μm); (ii) a reconfigurable routing of the recording sites to the 126 channels; and (iii) low noise levels. [ABSTRACT FROM AUTHOR]

A pipelined analog-to-digital converter (ADC) uses switched-capacitor stages that settle in two steps that occur sequentially in time. The first step of settling places charge onto the load capacitance using charge pumps, and the second fulfills the settling requirements using typical negative feedback around an operational amplifier. Hence, the design combines the efficiency of a fast charge-transfer phase with the gain and noise-immunity advantages of amplifier-driven settling. Improved conversion efficiency results from a higher ratio of current delivered to the load to that consumed in static biasing. Additional circuitry constrains critical amplifier node voltages during the charge transfer, facilitating a graceful transition to amplifier-driven settling. The two-step settling technique is demonstrated in a 2.5 bit/stage 10-bit pipelined ADC that consumes 11.1 mW while sampling a 21.3 MHz input signal at 42 MS/s. The resulting SNDR is 55.6 dB (ENOB = 8.94) and the SFDR is 67.5 dB. [ABSTRACT FROM AUTHOR]

Zero-crossing based switch capacitor circuits have been introduced as alternatives to op-amp based circuits for eased design considerations and improved power efficiency. This work further improves the resolution, power efficiency, and robustness of previous zero-crossing based circuits (ZCBCs) and features a 90 nm CMOS, offset compensated, fully differential, zero-crossing based, 12b, 50 MS/s, pipelined ADC requiring no CMFB. The power consumption is 4.5 mW. The FOM is 88 fJ/step. Fully differential signaling is used to improve power supply rejection and power efficiency. A power efficient chopping offset compensation technique is presented. Reference voltage switching is improved to avoid gate boosted switches. Redundancy is used to reduce output range requirements for increased signal range. Two regenerative latch architectures used for bit decision comparison are analyzed and measured for offset, noise, and speed. [ABSTRACT FROM AUTHOR]

A 33-dBm P 0.1-dB single-pole double-throw antenna switch is designed and implemented using a standard 0.18-μm CMOS process at 1.8 GHz. An analysis shows a relation between parasitic junction capacitors and substrate resistance for low insertion loss (IL). The power-handling capability of the switch was also investigated through the voltage dividing mechanism through the substrate in the case of an ON-state NMOS switch implemented in a triple-well structure. A multistacked field-effect transistor (FET) structure with feed-forward capacitors in an Rx switch was chosen as the method of designing an antenna switch with high power-handling capability. Low IL of the switch in the multistacked FET structure is achieved by the optimization of layout and minimization of junction capacitors through the deep N-well bias. Allowance of a negative voltage swing at either the source or drain port is ensured by a floated well structure with a negatively biased P-well for each switch device of the multistacked FET structure. Intentional unequal division of the voltage swing level at each NMOS device by feed-forward capacitors with negative biases of the OFF-state switches helps to prevent channel formation in the OFF-state device. Experimental data shows that the proposed design achieves a 0.1-dR compression point at 33-dBm input power at 1.8 GHz with a negative bias supply to control the voltage at the OFF-state switches and the P-well of each device. The IL of the Tx switch is 0.5 and 0.73 dB at 900 MHz and 1.8 GHz, respectively. The Rx switch has 0.7- and 1.1-dB IL at 900 MHz and 1.8 GHz, respectively. In addition, a reliability issue related to antenna load mismatch was tested using a load-pull measurement setup. [ABSTRACT FROM AUTHOR]

We describe the development of a CMOS read-out chip for an x-ray pixel array detector that accumulates into analog storage elements with time resolution typical of synchrotron bunch spacings. Each pixel contains multiple analog storage elements to allow capture of full-frame images at submicrosecond separation. Additionally, each storage element is re-addressable, which allows accumulation of signal from temporally distinct acquisition windows. Test results show the ability to slew and settle the equivalent of 650 8-keV x-rays (1.21 Me-) in less than 100 ns. The detector RMS read-noise was measured to be 2350 e- and grows with the square-root of the number of accumulations with a coefficient of 415 e (equivalent to 1.07 and 0.19 8-keV x-rays respectively). The saturation value for each storage element, in terms of 8 keV x-rays, was measured to exceed 1880 x-rays (6.42 Me-). The complete detector is anticipated to contain around 400 × 200 pixels with pixel size near 150 μm × 150 μm. Possible experimental applications include study of material failures, transient phase transformations, and high-speed x-radiography. [ABSTRACT FROM AUTHOR]

Abstract: A systematic design approach for low-power 10-bit, 100MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57dB at 2MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/−0.3151LSB and the maximum integral nonlinearity (INL) is +0.4271/−0.4712LSB. The dynamic range of the ADC is 58.72dB for full-scale input signal at 2MHz input frequency. The ADC consumes 52.6mW at 100MS/s sampling rate. The circuit is implemented using UMC-180nm digital CMOS technology. [Copyright &y& Elsevier]

This paper presents the measurement results of a micropower switched-capacitor front end that was designed for three-axis capacitive microaccelerometers. The designed front end can reduce the distorting effects of the electrostatic forces and can be used in single-ended and differential modes. The front end was realized with a 0.13-μm bipolar complimentary metal-oxide-semiconductor process. The silicon area of the front end is 0.30 mm². The measurements show that the functionality of the front end follows the theory in both modes Consuming 20 μA from a 1.8-V supply, it achieves noise densities of 424, 607, and 590 μg/√Hz in the x-, y-, and z-directions, respectively, when each mass is sampled at 1 kHz in the differential mode. [ABSTRACT FROM AUTHOR]