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Nowadays there is no doubt on the susceptibility of cryptographic devices to side-channel analysis attacks. During the last decade, integration of corresponding countermeasures into devices which deal with security and privacy of users has become a must. This motivated several research on designing countermeasures, one of which is to make use of power-balancing feature of adiabatic logic families originally motivated for low-power applications. In this work we introduce the first such a construction which operates in three phases compared to the entire state-of-the-art schemes requiring at least four phases. We especially designed our proposed scheme to harden power-analysis attacks. To this end, we considered several relevant design criteria. For example, we payed particular attention to the symmetry of the fundamental gates of our proposed 3-phase construction. Based on simulation results and information-theoretic based SCA evaluations we claim that our construction can harden power analysis attacks more than the state-of-the-art adiabatic logic families. We further highlight the importance of the way power clocks are generated for an adiabatic circuit, and show the negative effect of the widely-known stepwise charge sharing power clock generator on the SCA security. Accordingly, we present an adjustment on such a circuit followed by corresponding SCA evaluation.

Modern cryptographic circuits are increasingly demanding security requirements. Since its invention, power analysis attacks are a threat to the security of such circuits. In order to contribute to the design of secure circuits, designers may employ countermeasures in different abstraction levels. This work presents a brief survey of countermeasures to help designers to find good solutions for the design of secure cryptographic systems. A summary is highlighted to compare the pros and cons of the approaches to help designers choose a better solution, or even provide subsidies so that new solutions can be proposed.

Temporarily ambiguous sentences that are disambiguated in favor of a less preferred parse are read more slowly than their unambiguous counterparts. This slowdown is referred to as a garden path effect. Recent self-paced reading studies have found that this effect decreased over the course of the experiment as participants were exposed to such syntactically ambiguous sentences. This decrease in the magnitude of the effect has been interpreted as evidence that readers calibrate their expectations to the context; this minimizes their surprise when they encounter these initially unexpected syntactic structures. Such recalibration of syntactic expectations, referred to as syntactic adaptation, is only one possible explanation for the decrease in garden path effect, however; this decrease could also be driven instead by increased familiarity with the self-paced reading paradigm (task adaptation). The goal of this paper is to adjudicate between these two explanations. In a large between-group study (n = 642), we find evidence for syntactic adaptation over and above task adaptation. The magnitude of syntactic adaptation compared to task adaptation is very small, however. Power analyses show that a large number of participants is required to detect, with adequate power, syntactic adaptation in future between-subject self-paced reading studies. This issue is exacerbated in experiments designed to detect modulations of the basic syntactic adaptation effect; such experiments are likely to be underpowered even with more than 1200 participants. We conclude that while, contrary to recent suggestions, syntactic adaptation can be detected using self-paced reading, this paradigm is not very effective for studying this phenomenon. © 2021, American Psychological Association. This paper is not the copy of record and may not exactly replicate the final, authoritative version of the article. Please do not copy or cite without authors' permission. The final article will be available, upon publication, via its DOI: 10.1037/xlm0001046

Editor’s note: This article proposes a formal design system for automatically generating provably secure register transfer level description of cryptographic hardware based on generalized masking scheme. —Rosario Cammarota, Intel Labs —Francesco Regazzoni, University of Amsterdam and Universita della Svizzera Italiana

A method for the vulnerability assessment of Internet-of-Things (IoT) medical transducers cybersecurity at varying the power countermeasures is proposed. The implemented countermeasures reinforce the most popular cryptographic algorithm, advanced encryption standard (AES), running on a low-cost, low-energy, and low-performance smart transducer for IoT medical devices. The proposed method is based on attacks standardized in the smart-card industry: differential power analysis (DPA) and correlation power analysis (CPA). Adopting a methodically rigorous framework, a boost for the study of power countermeasures was offered for IoT medical transducers. An experimental comparison of security performance among different power countermeasures was realized. Each countermeasure increases the number of power traces needed to discover the AES secret key. Random delay, random SBox, and masking strengthen the AES of 1.3, 208, and 318 factors, respectively. The masking countermeasure was by far the most effective.

In the pharmaceutical industry, in vivo animal experiments are conducted to test the effects of novel preclinical drug compounds. Well-planned animal studies involve a sample size and statistical power analysis to provide a basis for the number of animals allocated into comparator arms of a future study. These calculations require approximate values for the parameters of a statistical model that will be applied to the future data and used to test for differences via statistical hypotheses. If the prestudy parameter estimates are nearly correct, the power analysis guarantees that a difference will be detected from the study data, up to a prespecified probability. Traditional power computations, however, are not calculated with reproducibility in mind. In this work, the issue of reproducibility in drug discovery is tackled from the point of view that study-to-study variability is not included in a typical sample size and power analysis. Three proposed methods that yield a reproducible mean-comparison analysis are derived and compared.

This paper presents a reconfigurable frequency response masking (FRM) wideband channelizer architecture which is characterized by low computational and hardware complexity. The proposed hardware efficient architecture is realized by incorporating resource shared non-maximally decimated filter bank in the implementation of the FRM wideband channelizer structure. The coefficients of the proposed architecture are optimized and made multiplier-free using Pareto based meta-heuristic algorithm in the canonic signed digit (CSD) space for reducing the total power consumption of the architecture. The architecture is finally designed and synthesized using Xilinx Vivado and Cadence RTL Encounter compiler for the area and power analysis and is compared with existing channnelizer architectures. The comparison highlights the advantages of the proposed architecture in terms of hardware complexity, power and workload in realizing sharp wideband channel filters.

The CMERE algorithm was designed to resist DPA attacks on modular exponentiation. It was implemented and tested at the algorithmic level for different key sizes of the RSA cryptosystems. The streng...

Comparative biological studies typically require plenty of samples to ensure full representation of the given problem. A frequently-encountered question is how many samples are sufficient for a particular study. This question is traditionally assessed using the statistical power, but it alone may not guarantee the full and reproducible discovery of features truly discriminating biological groups. Two new types of statistical criteria have thus been introduced to assess sample sufficiency from different perspectives by considering diagnostic accuracy and robustness. Due to the complementary nature of these criteria, a comprehensive evaluation based on all criteria is necessary for achieving a more accurate assessment. However, no such tool is available yet. Herein, an online tool SSizer (https://idrblab.org/ssizer/) was developed and validated to enable the assessment of the sample sufficiency for a user-input biological dataset, and three statistical criteria were adopted to achieve comprehensive and collective assessment. A sample simulation based on a user-input dataset was performed to expand the data and then determine the sample size required by the particular study. In sum, SSizer is unique for its ability to comprehensively evaluate whether the sample size is sufficient and determine the required number of samples for the user-input dataset, which, therefore, facilitates the comparative and OMIC-based biological studies.

Athough side-channel attacks appeared more than two decades ago, they remain very little discussed by security professionals outside the academia or very specific sectors (e.g., smartcard industry, governments). However, with the increasing generalisation of Internet of Things systems, they are a threat that can no longer be ignored by the operational world. This work aims to demonstrate that side-channel attacks can be practically achieved by an attacker, with reasonable means, effort, knowledge, and time. For this purpose, the contribution of this work is twofold. First, it is shown how a side-channel attack setup exploiting power leakages through electro-magnetic radiations, and making use of general-purpose and affordable equipment, can be built. The acquisition of attack power traces is made thanks to a Red Pitaya STEMlab platform coupled with a home-built radio front-end. Second, it is shown how an attack can be conducted against targets that are representative of Internet of Things devices: 8-bit and 32-bit Arduino boards.

The significance of the Internet of Drones (IoD) is increasing steadily and now IoD is being practiced in many military and civilian-based applications. IoD facilitates real-time data access to the users especially the surveillance data in smart cities using the current cellular networks. However, due to the openness of communication channel and battery operations, the drones and the sensitive data collected through drones are subject to many security threats. To cope the security challenges, recently, Srinivas et al. proposed a temporal credential based anonymous lightweight authentication scheme (TCALAS) for IoD networks. Contrary to the IoD monitoring framework proposed by Srinivas et al., their own scheme can work only when there is one and only one cluster/fiying zone and is not scalable. Moreover, despite their claim of robustness, the investigation in this paper reveals that Srinivas et al.'s scheme cannot resist traceability and stolen verifier attacks. Using the lightweight symmetric key primitives and temporal credentials, an improved scheme (iTCALAS) is then proposed. The proposed scheme while maintaining the lightweightness provides security against many known attacks including traceability and stolen verifier. The proposed iTCALAS extends scalability and can work when there are several fiying zone/clusters in the IoD environment. The formal security proof along with automated verification using ProVerif show robustness of proposed iTCALAS. Moreover, the security discussion and performance comparisons show that the iTCALAS provides the known security features and completes authentication in just 2:295 ms, Funding Agency: Deanship of Scientific Research (DSR), King Abdulaziz University, Jeddah Grant Number: D-480-611-1441 This work was supported by the Deanship of Scientific Research (DSR), King Abdulaziz University, Jeddah, under Grant D-480-611-1441.

Reliably and power efficiently securing integrated systems against advanced power analysis attacks (PAAs) is a significant design challenge in modern integrated circuits. Power masking and hiding are typical countermeasures for increasing system resilience for power attacks at the expense of the overall system performance and power efficiency. These method are, however, not able to alert the user or trigger additional protective actions in case of the attack. In this paper, a method for detecting power attacks in real-time is proposed. The proposed approach exploits statistical methods to analyze the on-chip voltage variations across an on-chip power grid and detect the attacker probe connected to the system. The problem of the full security coverage of the power grid is formulated and solved in this paper. Adjusting the density of the on-chip sensors and exploiting sparse analysis techniques is considered to simultaneously enhance the accuracy and power efficiency of the proposed solution. The proposed attack detection system is designed, simulated, and evaluated in Simulink based on IBM microprocessor benchmark data. Machine learning (ML) models are trained in Python and with scikit-learn ML library. The proposed system has been demonstrated to efficiently detect PAA within a period of time that is orders of magnitude shorter than a typical attack duration length. The system is expected to exhibit high detection accuracy and power efficiency across a wide spectrum of integrated systems.

With the advent of Next Generation Sequencing, RNA-sequencing (RNA-seq) has become the major method for quantitative gene expression analysis. Reducing library costs by early barcoding has propelled single-cell RNA-seq, but has not yet caught on for bulk RNA-seq. Here, we optimized and validated a bulk RNA-seq method we call prime-seq. We show that with respect to library complexity, measurement accuracy, and statistical power it performs equivalent to TruSeq, a standard bulk RNA-seq method, but is four-fold more cost-efficient due to almost 50-fold cheaper library costs. We also validate a direct RNA isolation step that further improves cost and time-efficiency, show that intronic reads are derived from RNA, validate that prime-seq performs optimal with only 1,000 cells as input, and calculate that prime-seq is the most cost-efficient bulk RNA-seq method currently available. We discuss why many labs would profit from a cost-efficient early barcoding RNA-seq protocol and argue that prime-seq is well suited for setting up such a protocol as it is well validated, well documented, and requires no specialized equipment.

Deep-learning side-channel attacks, applying deep neural networks to side-channel attacks, are known that can easily attack some existing side-channel attack countermeasures such as masking and random jitter. While there have been many studies on profiled deep-learning side-channel attacks, a new approach that involves applying deep learning to non-profiled attacks was proposed in 2018. In our study, we investigate the structure of multi-layer perceptrons and points of interest for non-profiled deep-learning side-channel attacks using the ANSSI database with a masking countermeasure. The results of investigations indicate that it is better to use a simple network model, apply regularization to prevent over-fitting, and select a wide range of power traces that contain side-channel information as the points of interest. We also implemented AES-128 software implementation protected with the Rotating Sboxes Masking countermeasure, which has never been attacked by non-profiled deep-learning side-channel attacks, on the Xmega128 microcontroller and carried out non-profiled deep-learning side-channel attacks against it. Non-profiled deep-learning side-channel attacks successfully recovered all partial keys while the conventional power analysis could not. The attack results also showed that the least significant bit is the adequate selection for successful non-profiled deep-learning side-channel attacks, but the best labeling method may vary depending on the implementation of the countermeasure algorithm. We conducted two experimental analyses to clarify that deep-learning side-channel attacks learn mask values used in the masking countermeasure. One is the gradient visualization used in previous studies, and the other is a new analysis method using partial removal of power traces.

LoRaWAN has gained significant attention for Internet-of-Things (IOT) applications due to its low power consumption and long range potential for data transmission. While there is a significant body of work assessing LoRA coverage and data transmission characteristics, there is a lack of data available about commercially available LoRa prototyping boards and their power consumption, in relation to their features. It is currently difficult to estimate the power consumption of a LoRa module operating under different transmission profiles, due to a lack of manufacturer data available. In this study, power testing has been carried out on physical hardware and significant variation was found in the power consumption of competing boards, all marketed as “extremely low power”. In this paper, testing results are presented alongside an experimentally-derived power model for the lowest power LoRa module, and power requirements are compared to firmware settings. The power analysis adds to existing work showing trends in data-rate and transmission power settings effects on electrical power consumption. The model’s accuracy is experimentally verified and shows acceptable agreement to estimated values. Finally, applications for the model are presented by way of a hypothetical scenario and calculations performed in order to estimate battery life and energy consumption for varying data transmission intervals.

The article addresses the redesign of a landing gear for a light aircraft that suffered from manufacturing and assembly problems. Numerical parameters of design features are related to design guidelines for identifying fabrication and assembly issues within 3D model analysis. For this work, the Lucas method of the DFMA integrated with reverse engineering was used as a methodology for the redesign, and its evaluation parameters for resizing the assembly item. Subsequently, the geometry of the redesigned component was defined, where significant reductions were obtained for the evaluation rates of the method used. Reduction from 20 pieces to just 6, which corresponds to a gain of 42% for functional analysis, reductions of 72% for power analysis and 84% for assembly analysis.

In recent years, numerous attacks have appeared that aim to steal secret information from their victim using the power side-channel vector, yet without direct physical access. These attacks are called Remote Power Attacks or Remote Power Analysis, utilizing resources that are natively present inside the victim environment. However, there is no unified definition about the limitations that a power attack requires to be defined as remote. This paper aims to propose a unified definition and concrete threat models to clearly differentiate remote power attacks from non-remote ones. Additionally, we collect the main remote power attacks performed so far from the literature, and the principal proposed countermeasures to avoid them. The search of such countermeasures denoted a clear gap in preventing remote power attacks at the technical level. Thus, the academic community must face an important challenge to avoid this emerging threat, given the clear room for improvement that should be addressed in terms of defense and security of devices that work with private information. acceptedVersion

SummaryMiSDEED is a command-line tool for generating synthetic longitudinal multi-omics data from simulated microbial environments. It generates relative-abundance timecourses under perturbations for an arbitrary number of samples and patients. All simulation parameters are exposed to the user to facilitate rapid power analysis and aid in study design. Users who want additional flexibility may also use MiSDEED as a Python package.Availability and implementationMiSDEED is written in Python and is freely available at https://github.com/pchlenski/misdeed.Contactpac@cs.columbia.edu

The internet of things (IoT) continues to grow quickly, with corresponding pressures to get products to market rapidly. Battery life is a key challenge, along with connectivity, coexistence, compliance, and cybersecurity. While traditional battery charge consumption measurement technologies use high speed measurements for optimal accuracy, slower measurements may actually be preferable under certain conditions. IoT devices operate in highly variable and dynamic environments that include changes to the physical environment, the electromagnetic environment, and the volumes of data measured, processed, stored, transmitted, and received. In many IoT applications there are serious consequences for the end user or device vendor if a device battery fails prematurely. This paper describes a hybrid strategy using event-based power analysis for measuring and analyzing an IoT device in highly dynamic environments. Engineers can use this hybrid approach to quickly gain the necessary insights to properly configure hardware, firmware, and software to optimize battery runtime and avoid customer frustration and the associated consequences.

Novel high performance computing systems that feature hybrid architectures require large scale code refactoring to unravel underlying exploitable parallelism. Such redesign can often be accompanied with machine-precision changes as the order of computation cannot always be maintained. For chaotic systems like climate models, these round-off level differences can grow rapidly. Systematic errors may also manifest initially as machine-precision differences. Isolating genuine round off level differences from such errors remains a challenge. Here, we apply two-sample equality of distribution tests to evaluate statistical reproducibility of the ocean model component of US Department of Energy's Energy Exascale Earth System Model (E3SM). A 2-year control simulation ensemble is compared to a modified ensemble as a test case - after a known non-bit-for-bit change in a model component is introduced - to evaluate the null hypothesis that the two ensembles are statistically indistinguishable. To quantify the false negative rates of these tests, we conduct a formal power analysis using a targeted suite of short simulation ensembles. The ensemble suite contains several perturbed ensembles, each with a progressively different climate than the baseline ensemble - obtained by perturbing the magnitude of a single model tuning parameter, the Gent and McWilliams κ, in a controlled manner. The null hypothesis is evaluated for each of perturbed ensembles using these tests. The power analysis informs on the detection limits of the tests for given ensemble size allowing model developers to evaluate the impact of an introduced non-bit-for-bit change to the model.

Side-channel attacks target system implementation statistics, such as the electricity required to run a cryptographic function. Deriving cryptographic keys, such as AES keys, has become such a simplified process that extracting sensitive information from an otherwise secure algorithm requires only a $35USD microcontroller. While cryptographic algorithms indicate the presence of sensitive data, making them a preferable target, other systems hold valuable data with significantly less protection. Due to the ubiquity and rigidity of machine learning algorithms, the ability to infer model parameters has drastic security implications. This investigation extracted information from machine learning models through the use of traditional side-channel techniques. Specifically, a side-channel power analysis was performed using a ChipWhisperer Lite to extract information from Neural Networks and Linear Regression models running on a target microcontroller. Then, time series classification tasks were performed on the resultant power traces to determine the differences between the two models and their varied hyperparameters. Three such classification tasks were tested. In the first, a neural network was differentiated from a linear regression model with 100% accuracy. In the second, two neural networks with different sized hidden layers are classified with 97.92% accuracy. In the third, two virtually identical linear regression models are compared that differ only in the initial value of one hyperparameter. These models were only classified with 67.92% accuracy. Although the accuracy decreases as the models become more alike, these results indicate that machine learning model parameters can be inferred from power-based side-channel attacks.

Logic locking techniques have been widely investigated to thwart intellectual property (IP) piracy and reverse engineering attacks on integrated circuits. Although extensive research efforts have been made to examine the resilience of logic locking techniques against Boolean satisfiability (SAT) and key sensitization attacks, there still lacks a comprehensive assessment of different locking methods’ resilience against power-analysis attacks. In this work, we evaluate the success rate of differential power analysis (DPA) and correlation power analysis (CPA) attacks that are performed on the circuits encrypted with logic locking techniques applied at gate level or transistor level. To enhance the CPA attack resilience of the existing transistor-level locking techniques, we further propose a new strategy to search for optimal key insertion locations. Our analysis and experimental results indicate that gate-level locking and transistor-level locking should use different strategies to select the optimal key insertion locations. Our case studies confirm that the proposed key insertion strategy can improve the transistor-level locking technique’s resilience against CPA attacks.

Chaos computing provides a large number of functions from a single hardware. Large-scale reconfigurability can be achieved flexibly by tuning only a few parameters from a chaos-based computing system. Implementation of reconfigurable complex functions from a single chaos circuit can alleviate area and power concerns due to decreasing technology nodes. It is possible to make a multi-input multi-output complex instruction set using the chaos-generated functionalities where operations are more uniform than conventional implementations. Lack of uniformity in implementation of instructions in traditional computing system provides opportunity for attackers to reverse engineer based on side channel power analysis. In this paper, it is proposed that chaos-based implementation of a complex instruction set is immune to classification-based reverse engineering attack. Cross obfuscation and self obfuscation schemes are proposed in this work which leverage reconfigurability of chaotic system for obfuscating the power profile of the instruction set and it has been made immune to reverse engineering attacks. The design utilizes 3-input multi-output instructions by using a single chaotic iterative map. We analyzed the immunity of this design against classification-based reverse engineering attack for six different classification algorithms with five dimensionality reduction techniques.

Dynamic occupancy models provide a flexible framework for estimating and mapping species occupancy patterns over space and time for large-scale monitoring programs (e.g., the North American Bat Monitoring Program (NABat), the Amphibian Research and Monitoring Initiative). Challenges for designing surveys using the dynamic occupancy modeling framework include defining appropriate derived trend parameters, and providing usable tools for researchers to conduct project-specific sample size investigations. We present a simulation-based power analysis framework for dynamic occupancy models that allows for the incorporation of the underlying environmental space (i.e., as covariates) within a specific study region to inform sample size estimation. We investigate two definitions of temporal trend: (1) a gradual, sustained (linear or nonlinear) change over a period of many years, and (2) an abrupt increase or decrease between two time periods. We draw upon pilot data collected following NABat protocols to inform assumed data generating values in a demonstration of our approach. Due to the complicated parameter structure of dynamic occupancy models, we emphasize the importance of visualizing simulated changes over time based on different parameter settings prior to conducting a power analysis. Our simulations revealed that the linearity of short-term trends (five years in our investigation) conferred higher power with lower sample size than longer trends where occupancy probabilities approached zero (ten years in our investigation). We provide an example of how to use our tools to conduct customized investigations using questions posed by NABat, and in doing so, we shed light on general guidelines that can be applied to programs monitoring species occupancy for other taxa. Importantly, we created an R package to execute our approach for informing program-, species-, and study-specific investigations aimed at identifying changes in species occupancy.

This paper presents an approach to compute secured modular exponentiation to mitigate power analysis attacks. Two processes have been designed based on ‘multiply-always’ binary method, whic...

With increasing expansion of the Internet of Things, embedded devices equipped with cryptographic modules become an important factor to protect sensitive data. Even though the employed algorithms in such devices are mathematically secure in theory, adversaries may still be able to compromise them by means of side-channel attacks. In power-based side-channel attacks, the instantaneous power consumption of the target is analyzed with statistical tools to draw conclusions about the secret keys that are used. There is a recent line of work that additionally makes use of techniques from the machine learning domain to attack cryptographic implementations. Since a complete review of this emerging field has not been done so far, this research aims to survey the current state of the art. We use a target-based classification to differentiate published work and drive general conclusions according to a common machine learning workflow. Furthermore, we outline the relationship between traditional power analysis techniques and machine learning-based attacks. This enables researchers to gain a better understanding of the topic in order to design new attack methods as well as potential countermeasures.

Several password and smart-card based two-factor security remote user authentication protocols for multi-server environment have been proposed for the last two decades. Due to tamper-resistant nature of smart cards, the security parameters are stored in it and it is also a secure place to perform authentication process. However, if the smart card is lost or stolen, it is possible to extract the information stored in smart card using power analysis attack. Hence, the two factor security protocols are at risk to various attacks such as password guessing attack, impersonation attack, replay attack and so on. Therefore, to enhance the level of security, researchers have focused on three-factor (Password, Smart Card, and Biometric) security authentication scheme for multi-server environment. In existing biometric based authentication protocols, keys are generated using fuzzy extractor in which keys cannot be renewed. This property of fuzzy extractor is undesirable for revocation of smart card and re-registration process when the smart card is lost or stolen. In addition, existing biometric based schemes involve public key cryptosystem for authentication process which leads to increased computation cost and communication cost. In this paper, we propose a new multi-server authentication protocol using smart card, hash function and fuzzy embedder based biometric. We use Burrows–Abadi–Needham logic to prove the correctness of the new scheme. The security features and efficiency of the proposed scheme is compared with recent schemes and comparison results show that this scheme provides strong security with a significant efficiency.

The Torque Method is an easy way for kinematic and power analysis of planetary gear trains, both simple and compound ones. Moreover it gives possibility of optimal choice of a structural scheme (and its parameters) of compound planetary gear trains.

The emergence of new devices to be used in low-power applications are expected to reach impressive performance compared to those obtained by equivalent CMOS counterparts. However, when used in lightweight security applications, these emerging paradigms are required to be reliable and safe enough during the task of protecting important and valuable data. In this work, the usage of HyperFET devices for security applications has been analyzed and new paradigms for enhancing security against Power Analysis attacks have been developed for the first time. To perform this analysis, classical dual-precharge logic primitives implemented with 14nm FinFET have been upgraded to incorporate HyperFET devices. The proposed primitives incorporating HyperFETs, as well as a 4-bit Substitution box of PRIDE algorithm as demonstrative example, have been designed and simulated using predictive models. Simulation-based Differential Power Analysis attacks demonstrate high improvements in security levels in a x25 factor at least, with negligible degradation in performance. This first approach could be easily extensible to other ciphers or crypto-circuits, where the incorporation of HyperFET devices will enhance security for most future applications. acceptedVersion

Elliptic curve cryptography is the most widely employed class of asymmetric cryptography algorithm. However, it is exposed to simple power analysis attacks due to the lack of unifiedness over point doubling and addition operations. The unified crypto systems such as Binary Edward, Hessian and Huff curves provide resistance against power analysis attacks. Furthermore, Huff curves are more secure than Edward and Hessian curves but require more computational resources. Therefore, this article has provided a low area hardware architecture for point multiplication computation of Binary Huff curves over GF(2163) and GF(2233). To achieve this, a segmented least significant digit multiplier for polynomial multiplications is proposed. In order to provide a realistic and reasonable comparison with state of the art solutions, the proposed architecture is modeled in Verilog and synthesized for different field programmable gate arrays. For Virtex-4, Virtex-5, Virtex-6, and Virtex-7 devices, the utilized hardware resources in terms of hardware slices over GF(2163) are 5302, 2412, 2982 and 3508, respectively. The corresponding achieved values over GF(2233) are 11,557, 10,065, 4370 and 4261, respectively. The reported low area values provide the acceptability of this work in area-constrained applications.

Power Analysis Attack (PAA) are a class of Side Channel Attacks (SCA) which is based on power consumption measurements whose major concern is the protection of secret data stored in cryptographic devices. This paper reports the advantages of Secure Double Rate Registers (SDRR) as a Register Transfer Level (RTL) countermeasure in order to increase the security of cryptographic devices against PAA. SDRR is exploited in AES 128 bit architecture, the random data in the entire clock cycle is evaluated by the combinational path. One of the main advantage is that our technique does not require duplication of combinational path to process the random data thereby limiting area overhead unlike previous RTL countermeasures. This work reported in this paper gives the comparative study between conventional advanced encryption standard (AES) algorithm with normal registers and AES algorithm with secure double rate registers (SDRR). This proposed system is implemented, simulated using Verilog HDL and synthesized by Xilinx tool.

Authenticated Encryption (AE) is the latest cryptographic algorithm standard introduced through CAESAR (Com-petition for Authenticated Encryption: Security, Applicability, and Robustness). AE schemes provide a process for simultaneously achieving the security goals of confidentiality and integrity assurance. The constructions of authentication encryption is secure and efficient to protect the modern electronic information systems. In this research paper, we proposed an Improved AEGIS-128 Algorithm (i-AEGIS-128) for improving the standard AEGIS-128 algorithm to enhance the performance in which quarter round-based AES (Advanced Encryption Standard) is used for the encryption and decryption process. The proposed i-AEGIS-128 is based on an AEGIS-128 AES-round permutation modification for hardware implementation. The Results of i-AEGIS-128 on Intel(R)Core(TM) i7-3700 Processor running at 3.40 GHz speed with 16GB of RAM using C/C++ and HDL (Hardware Description Language) languages and platforms to determine the encryption and decryption time, throughput processing unit memory during encryption and decryption. Finally we compared the efficiency and power analysis of the hardware. The i-AEGIS-128 algorithm relies on the use of ¼ AES-round in authentication encryption to reduce the area consumed during processing, perform fast encryption and decryption, use less power and provide the best efficiency.

Producing compelling and trustworthy results relies upon performing well-powered studies with low rates of misleading evidence. Yet, resources are limited, and maximum sample sizes required to achieve acceptable power in typical fixed N designs may be disconcerting. ‘Sequential’, ‘optional stopping’, or ‘interim’ designs – in which results may be checked at interim periods and a decision made as to whether to continue data collection or not – provide one means by which researchers may be able to achieve high power and low false positive rates with less of a resource burden. Sequential analyses have received considerable attention from both frequentist and Bayesian hypothesis testing approaches, but fewer approachable resources are available for those wishing to use Bayesian estimation. In this tutorial, we cover a general process for performing power analyses of fixed and sequential designs using Bayesian estimation – simulating data, performing regressions in parallel to reduce time requirements, choosing different stopping criteria and data collection sequences, and calculating observed power and rates of misleading evidence. We conclude with a discussion of some limitations and possible extensions of the presented approach.

Implementing countermeasure against power analysis-based attack is a critical issue in cryptographic hardware implementation. Protection schemes such as masking or Threshold Implementation (TI) have been proposed for hardware protection, but they have shortages like insufficient protection ability, or excessive hardware overhead. In this paper, we present low cost hetero S-box hardware implementation, where S-box groups for ARIA algorithm can be implemented using the coefficients with different hardware cost. Additional area reduction scheme using isomorphism sharing between S-boxes are also proposed. The proposed heterogeneous ARIS S-box has been implemented using 28nm CMOS process, and it showed 39% area saving with 30% of power saving. The proposed hardware also passed the security test, showing that it is verified as secure against power analysis-based attacks.

International audience; A key challenge HCI researchers face when designing a controlled experiment is choosing the appropriate number of participants, or sample size. A priori power analysis examines the relationships among multiple parameters, including the complexity associated with human participants, e.g., order and fatigue effects, to calculate the statistical power of a given experiment design. We created Argus, a tool that supports interactive exploration of statistical power: Researchers specify experiment design scenarios with varying confounds and effect sizes. Argus then simulates data and visualizes statistical power across these scenarios, which lets researchers interactively weigh various trade-offs and make informed decisions about sample size. We describe the design and implementation of Argus, a usage scenario designing a visualization experiment, and a think-aloud study.

To enhance the security of digital circuits, there is often a desire to dynamically generate, rather than statically store, random values used for identification and authentication purposes. Physically Unclonable Functions (PUFs) provide the means to realize this feature in an efficient and reliable way by utilizing commonly overlooked process variations that unintentionally occur during the manufacturing of integrated circuits (ICs) due to the imperfection of fabrication process. When given a challenge, PUFs produce a unique response. However, PUFs have been found to be vulnerable to modeling attacks where by using a set of collected challenge response pairs (CRPs) and training a machine learning model, the response can be predicted for unseen challenges. To combat this vulnerability, researchers have proposed techniques such as Challenge Obfuscation. However, as shown in this paper, this technique can be compromised via modeling the PUF's power side-channel. We first show the vulnerability of a state-of-the-art Challenge Obfuscated PUF (CO-PUF) against power analysis attacks by presenting our attack results on the targeted CO-PUF. Then we propose two countermeasures, as well as their hybrid version, that when applied to the CO-PUFs make them resilient against power side-channel based modeling attacks. We also provide some insights on the proper design metrics required to be taken when implementing these mitigations. Our simulation results show the high success of our attack in compromising the original Challenge Obfuscated PUFs (success rate > 98%) as well as the significant improvement on resilience of the obfuscated PUFs against power side-channel based modeling when equipped with our countermeasures.

FPGAs have been used in the cloud since several years, for workloads such as machine learning, database processes and security tasks. As for other cloud services, a highly desired feature is virtualization in which multiple tenants share a single FPGA to increase utilization and by that efficiency. By solely using standard FPGA logic in the untrusted tenant, on-chip logic sensors have recently been proposed, allowing remote power analysis side-channel and covert channel attacks on the victim tenant. However, such sensors are implemented by unusual circuit constructions, such as ring oscillators or delay lines, which might be easily detected by bitstream and/or netlist checking. In this paper we show that such structural checking methods are not universal solutions as the attacks can make use of “benign-looking” circuits. We demonstrate this by showing a successful Correlation Power Analysis attack on the Advanced Encryption Standard.

In this paper, we show that a software implementation of CCA secure Saber KEM protected by first-order masking and shuffling can be broken by deep learning-based power analysis. Using an ensemble of deep neural networks created at the profiling stage, we can recover the session key and the long-term secret key from 257 x N and 24 x 257 x N traces, respectively, where N is the number of repetitions of the same measurement. The value of N depends on the implementation, environmental factors, acquisition noise, etc.; in our experiments N = 10 is enough to succeed.The neural networks are trained on a combination of 80% of traces from the profiling device with a known shuffling order and 20% of traces from the device under attack captured for all-0 and all-1 messages. "Spicing'' the training set with traces from the device under attack helps minimize the negative effect of device variability. Part of Proceedings: 978-1-4503-8662-3QC 20230331

In recent years the popularity of procedures to collect intensive longitudinal data, such as the Experience Sampling Method, has immensely increased. The data collected using such designs allow researchers to study the dynamics of psychological functioning, and how these dynamics differ across individuals. To this end, the data are often modeled with multilevel regression models. An important question that arises when designing intensive longitudinal studies is how to determine the number of participants needed to test specific hypotheses regarding the parameters of these models with sufficient power. Power calculations for intensive longitudinal studies are challenging, because of the hierarchical data structure in which repeated observations are nested within the individuals and because of the serial dependence that is typically present in this data. We, therefore, present a user-friendly application and step-by-step tutorial to perform simulation-based power analyses for a set of models that are popular in intensive longitudinal research. Since many studies use the same sampling protocol (i.e., a fixed number of at least approximately equidistant observations) within individuals, we assume this protocol fixed and focus on the number of participants. All included models explicitly account for the temporal dependencies in the data by assuming serially correlated errors or including autoregressive effects. ispartof: Advances in Methods and Practices in Psychological Science vol:4 issue:1 pages:1-24 status: published

Recently introduced federated learning is an attractive framework for the distributed training of deep learning models with thousands of participants. However, it can potentially be used with malicious intent. For example, adversaries can use their smartphones to jointly train a classifier for extracting secret keys from the smartphones’ SIM cards without sharing their side-channel measurements with each other. With federated learning, each participant might be able to create a strong model in the absence of sufficient training data. Furthermore, they preserve their anonymity. In this paper, we investigate this new attack vector in the context of side-channel attacks. We compare the federated learning, which aggregates model updates submitted by N participants, with two other aggregating approaches: (1) training on combined side-channel data from N devices, and (2) using an ensemble of N individually trained models. Our first experiments on 8-bit Atmel ATxmega128D4 microcontroller implementation of AES show that federated learning is capable of outperforming the other approaches.

The effective feature selection and classification of power traces in side-channel attacks has been a hot topic of research in recent years. Traditional side-channel attacks, such as simple power analysis attacks and template attacks, require a large number of power traces to break the key, while machine learning algorithms require fewer power traces to successfully recover the key, thus being able to greatly improve the success rate of the attack. Among them, the MLP network proves effective in data classification. Therefore, based on the MLP network, we investigate and propose a power analysis attack method with the feature selection of two joint correlation coefficients. Via comparing the conventional attack methods, the success rate of this attack method is significantly improved.

The majority of recently demonstrated deep-learning side-channel attacks use a single neural network classifier to recover the key. The potential benefits of combining multiple classifiers with ensemble learning method have not been fully explored in the side-channel attack’s context. In this paper, we show that, by combining several CNN classifiers which use different attack points, it is possible to considerably reduce (more than 40% on average) the number of traces required to recover the key from an FPGA implementation of AES by power analysis. We also show that not all combinations of classifiers improve the attack efficiency.

This paper presents an overview of power analysis side-channel attack and experimental results of power consumption measurements charts for encryption algorithm Magma (GOST R 34.12 - 2015 (n = 64)). Magma cipher was implemented at Arduino electric board (namely Arduino Uno). Measurements were made by using a LECROY WavePro 7100A oscilloscope with a 1 GHz bandwidth and 10 GHz / 4 channel sampling frequency. Our experiments led to finding segments and getting power value of each encryption operations and marked segments of each encryption rounds.

MPC-in-the-head based protocols have recently gained much popularity and are at the brink of seeing widespread usage. With widespread use come the spectres of implementation issues and implementation attacks such as side-channel attacks. We show that implementations of protocols implementing the MPC-in-the-head paradigm are vulnerable to side-channel attacks. As a case study, we choose the ZKBoo-protocol of Giacomelli, Madsen, and Orlandi (USENIX 2016) and show that even a single leaked value is sufficient to break the security of the protocol. To show that this attack is not just a theoretical vulnerability, we apply differential power analysis to show the vulnerabilities via a simulation. In order to remedy this situation, we extend and generalize the ZKBoo-protocol by making use of the notion of strong non-interference of Barthe et al. (CCS 2016). To apply this notion to ZKBoo, we construct novel versions of strongly non-interfering gadgets that balance the randomness across the different branches evenly. Finally, we show that each circuit can be decomposed into branches using only these balanced strongly non-interfering gadgets. This allows us to construct a version of ZKBoo, called $(n+1)$-ZKBoo which is secure against side-channel attacks with limited overhead in both signature-size and running time. Furthermore, $(n+1)$-ZKBoo is scalable to the desired security against adversarial probes. We experimentally confirm that the attacks successful against ZKBoo no longer work on $(n+1)$-ZKBoo. Moreover, we present an extensive performance analysis and quantify the overhead of our scheme using a practical implementation.

Power Attacks have become a serious concern for secure FPGA-based embedded system design. However, considerable countermeasures have been introduced to improve the resistance of FPGA devices against Differential Power Analysis (DPA) and Correlation Power Analysis (CPA) attacks during recent years. In this work, we proposed a novel countermeasure which utilizes the Dynamic Partial Reconfiguration (DPR) property of the FPGA devices to obfuscate the leaked information. DPR capability allows updating a certain part of the running design on the device while other parts remain functioning without interruption. We proposed a new masking scheme using this technology in which masking function is changed dynamically at runtime to violate the assumptions needed for a successful power analysis attack. The proposed method not only overcomes to the first-order DPA attacks but also increases the resistance against the second-order DPA attacks. Our experimental results show that the proposed method has considerable security improvement against first and second order SCA attacks with negligible overheads. Moreover it can be complemented with any other desired countermeasures as well.

This paper presents a multiplier-free realization of the block finite impulse response (FIR) filter in transpose form configuration using binary constant shifts method (BCSM). The proposed architecture is synthesized using Xilinx Vivado and Cadence RTL Encounter compiler for the area and power analysis and is compared with the existing works in the literature. The comparison highlights the advantages of the proposed architecture in terms of power, hardware complexity and throughput for realizing reconfigurable high throughput block FIR filters.

Evolve and resequence (E&R) experiments, in which artificial selection is imposed on organisms in a controlled environment, are becoming an increasingly accessible tool for studying the genetic basis of adaptation. Previous work has assessed how different experimental design parameters affect the power to detect the quantitative trait loci (QTL) that underlie adaptive responses in such experiments, but so far there has been little exploration of how this power varies with the genetic architecture of the evolving traits. In this study, we use forward simulation to build a more realistic model of an E&R experiment in which a quantitative polygenic trait experiences a short, but strong, episode of truncation selection. We study the expected power for QTL detection in such an experiment and how this power is influenced by different aspects of trait architecture, including the number of QTL affecting the trait, their starting frequencies, effect sizes, clustering along a chromosome, dominance, and epistasis patterns. We show that all of these parameters can affect allele frequency dynamics at the QTL and linked loci in complex and often unintuitive ways, and thus influence our power to detect them. One consequence of this is that existing detection methods based on models of independent selective sweeps at individual QTL often have lower detection power than a simple measurement of allele frequency differences before and after selection. Our findings highlight the importance of taking trait architecture into account when designing and interpreting studies of molecular adaptation with temporal data. We provide a customizable modeling framework that will enable researchers to easily simulate E&R experiments with different trait architectures and parameters tuned to their specific study system, allowing for assessment of expected detection power and optimization of experimental design.

The method of cryptography establishes the confidentiality for digital data transmission and storage. Cryptography is used in different applications like ecommerce, health-monitoring and military for protecting information. The Data encryption standard (DES) is widely used cryptographic algorithm due to its symmetric nature and economical implementation to provide short term data security. The same key and architecture set is used for encrypting and decrypting in DES algorithm accordingly. The substitution operation is performed by S-Box by using the key to obtain information uniquely. This paper implements DES algorithm using Globally Asynchronous Locally Synchronous (GALS) methodology which uses independent clock. This improves speed due to its pipelined architecture enabling concurrent data processing. The encryption and decryption engine are implemented by VLSI architecture. This architecture is simulated in Verilog HDL and synthesized on the Xilinx 14.2 device. The logical units of architecture on Field Programmable Gate Array (FPGA) increases by 6.25% to provide improved security. Hence, the speed is improved by trading off with area. This proposed method is proved to be robust for Differential Power Analysis (DPA) which is analyzed from the statistics of the processing time through 50000 encryptions.

Cyber physical systems (CPS) is a dominant technology in today's world due to its vast variety of applications. But in recent times, the alarmingly increasing breach of privacy and security in CPS is a matter of grave concern. Security and trust of CPS has become the need of the hour. Hardware Trojans are one such a malicious attack which compromises on the security of the CPS by changing its functionality or denial of services or leaking important information. This paper proposes the detection of Hardware Trojans at the system level in AES-256 decryption algorithm implemented in Atmel XMega Controller (Target Board) using a combination of side-channel power analysis and machine learning. Power analysis is done with help of ChipWhisperer-Lite board. The power traces of the golden algorithm (Hardware Trojan free) and Hardware Trojan infected algorithms are obtained and used to train the machine learning model using the 80/20 rule. The proposed machine learning model obtained an accuracy of 97%-100% for all the Trojans inserted.