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Through Silicon Via (TSV) is considered as the near-future solution to realize low-power and high-performance 3D-Integrated Circuits (3D-ICs) and 3D-Network-on-Chips (3D-NoCs). However, the lifetime reliability issue of TSV due to its fault sensitivity and the high operating temperature of 3D-ICs, which also accelerates the fault-rate, is one of the most critical challenges. Meanwhile, most current works focus on detecting and correcting TSV defects after manufacturing without considering high-temperature nodes’ impact on lifetime reliability. Besides, the recovery for defective clusters is also challenging because of costly redundancies. In this work, we present HotCluster: a hotspot-aware self-correction platform for clustering defects in 3D-NoCs to help understand and tackle this problem. We first give a method to predict normalized fault rates and place redundant TSV groups according to each region’s fault rate. In our particular medium fault-rate (normalized to the coolest area), HotCluster reduces about 60% of the redundancies in comparison to the uniformly distributed redundancies while having a higher ratio of router working in a normal state. Furthermore, HotCluster integrates both online (weight-based) and offline (max-flow min-cut offline method) mapping algorithms to help the system correct the faulty TSV clusters. The experimental results show that both the max-flow min-cut offline method and weight-based online mode with a redundancy of 0.25 exhibits less than 1% of routers disabled under 50% defect-rates.

For most Internet-of-Things (IoT) applications, embedded processors typically execute lightweight tasks such as sensing and communication. The typical IoT program senses some information and sends them via a channel, usually a wireless channel with an RF circuit. These IoT nodes often require a system with networking capabilities and a low-power harvester implementation. This brief presents a sub- $\mu \text{W}$ 8-bit processor which is suitable for such IoT applications. The processor implements the Open8 Instruction Set Architecture (ISA) with an 8-bit datapath and 16-bit bus addressing. The chip contains the processor and a 4-KB of Static Random-Access-Memory (SRAM), and is fabricated by the 65-nm Silicon-On-Thin-Box (SOTB) process. The SOTB process is one of the Fully-Depleted Silicon-On-Insulator (FD-SOI) technology. Hence, the ability to control biasing voltages is one of its key advantages to achieve low-power. The experimental results show that the power consumption at the reverse-body bias can reach down to 50-nW with 0.5-V supply voltage and 32-KHz operating clock frequency. The completed microcontroller consists of the Open8 processor, 32-KB of Read-Only-Memory (ROM), 4-KB of SRAM, Serial Peripheral Interface (SPI), SPI programmer, debug module, General-Purpose In-Outs (GPIOs), and UART. The system was tested using an XC7A100T Xilinx Field-Programmable Gate Array (FPGA); it yielded 1.8% of the total FPGA utilization.

In order to detect and localize through-silicon-via (TSV) failures in both manufacturing and operating phases, most of the existing methods use a dedicated testing mechanism with long response time and prerequisite interruptions for online testing. This article presents an error correction code (ECC)-based method named “TSV on-communication test” (TSV-OCT) to detect and localize faults without halting the operation of TSV-based 3-D-IC systems. We first propose a statistical detector, a method to detect open and short defects in TSVs that work in parallel with data transactions. Second, we propose an isolation-and-check algorithm to enhance the localization ability of the method. Moreover, the Monte Carlo simulations show that the proposed statistical detector increases $\times 2$ the number of detected faults when compared to conventional ECC-based techniques. With the help of isolation and check, TSV-OCT localizes the number of defects up to $\times 4$ and $\times 5$ higher. In addition, the response time is kept below 65 000 cycles, which could be easily integrated into real-time applications. On the other hand, an implementation of TSV-OCT on a 3-D Network-on-Chip (NoC) router shows no performance degradation for testing while having a reasonable area overhead.

As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Network-on-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles).

Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, R redundant TSVs can fully localize and correct R defects and support the detection of R+1 defects. Moreover, by using G groups, it can localize up to GxR and detect up to G x (R + 1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50% localization). By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.

The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHOTON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26% to 51.04% in the speed performance and a reduction rate of 7.55% to 60.64% in area utilization compared to existing implementations of PHOTON hash functions.

Deep Learning (DL) has contributed to the success of many applications in recent years. The applications range from simple ones such as recognizing tiny images or simple speech patterns to ones with a high level of complexity such as playing the game of Go. However, this superior performance comes at a high computational cost, which made porting DL applications to conventional hardware platforms a challenging task. Many approaches have been investigated, and Spiking Neural Network (SNN) is one of the promising candidates. SNN is the third generation of Artificial Neural Networks (ANNs), where each neuron in the network uses discrete spikes to communicate in an event-based manner. SNNs have the potential advantage of achieving better energy efficiency than their ANN counterparts. While generally there will be a loss of accuracy on SNN models, new algorithms have helped to close the accuracy gap. For hardware implementations, SNNs have attracted much attention in the neuromorphic hardware research community. In this work, we review the basic background of SNNs, the current state and challenges of the training algorithms for SNNs and the current implementations of SNNs on various hardware platforms.

Radio Frequency Identification (RFID) tags using asymmetric cryptography are more and more proposed to solve the well-known issue of symmetric-based tags, key distribution. In the asymmetric cryptography family, the Elliptic Curve Cryptography (ECC) primitive is often used due to its advantages in security and implementation costs. However, these ECC-based tags must still be hardened against hardware fault attacks (e.g., Side-Channel Attacks and Fault attacks). Balancing between the implementation costs and the security level is challenging since when the security level is improved, the implementation cost also increases much. Finding optimal implementations against hardware attacks is a system-level problem that must be taken authentication protocol security attributes and cryptography primitive costs into account. This paper proposes a methodology to develop low-cost ECC-based tags, ensuring robustness against Side-Channel Attacks. For that, a comparison of various authentication protocols and different ECC algorithms is first given, then an experimental setup is described to allow validating the implementations and measuring the robustness of the tag.

The Internet of Things (IoT) with the advancements of many technologies opens a wide range of new applications such as smart appliances, smart cities and smart grids. Despite its popularity and usability, it also creates a new attack surface for the hackers especially on highly constrained devices which have limited memory footprints and processing power. These constrained devices often use Authenticated Encryption with Associated Data (AEAD) to secure data stored in the devices and transmitted over the network. In this work, we design a lightweight data encryption core in hardware with the support for AEAD to secure IoT applications on highly constrained devices. The design achieves a low area cost with only 23kGEs in TSMC 65nm technology and an encryption throughput of 123Mbps at 60MHz.

In this paper, a PCA and ANN-based face recognition system is proposed and implemented on a Coarse Grain Reconfigurable Computing (CGRC) platform. Our work is quite distinguished from previous ones in two aspects. First, a new hardware-software co-design method is proposed, and the whole face recognition system is divided into several parallel tasks implemented on both the Coarse-Grained Reconfigurable Architecture (CGRA) and the General-Purpose Processor (GPP). Second, we analyzed the source code of the ANN algorithm and proposed the optimization solution to explore its multi-level parallelism to improve the performance of the application on the CGRC platform. The computation tasks of ANN are dynamically mapped onto CGRA only when needed, and it's quite different from traditional Field Programmable Gate Array (FPGA) methods in which all the tasks are implemented statically. Implementation results show that our system works correctly in face recognition with a correct recognition rate of approximately 90.5%. To the best of our knowledge, this work is the first implementation of PCA and ANN-based face recognition system on a dynamically CGRC platform presented in the literature.

Thermal dissipation is one of the most critical challenges for stacking 3D-ICs, where the heat cannot easily transfer through several layers of silicon. As the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Black’s mode [1], stacking 3D-ICs also confront the reliability threat. Notably, Copper has a higher activation energy than CMOS, which makes Copper Through-Silicon-Vias vulnerable with the thermal-accelerated failure. Therefore, this paper presents a platform where we investigate the thermal distribution, predict the reliability, and propose a method for efficiently insert spare TSVs to ensure lifetime reliability. To demonstrate our platform, we apply a TSV-based 3D-NoC (3D Network-on-Chip) under the PARSEC benchmarks. We also illustrate the thermal-aware TSV redundancies insertion using grid search and genetic algorithm to balance the number of TSVs and the target MTTF.

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To enhance the reliability of TSV connections, using error correction code to detect and correct faults automatically has been demonstrated as a viable solution.This paper presents a 2D Parity Product Code (2D-PPC) for TSV fault-tolerance with the ability to correct one fault and detect, at least, two faults. In an implementation of 64-bit data and 81-bit codeword, 2D-PPC can detect over 71 faults, on average. Its encoder and decoder decrease the overall latency by 38.33% when compared to the Single Error Correction Double Error Detection code. In addition to the high detection rates, the encoder can detect 100% of its gate failures, and the decoder can detect and correct around 40% of its individual gate failures. The squared 2D-PPC could be extended using orthogonal Latin square to support extra bit correction.

As one of the most promising technologies to reduce footprint, power consumption and wire latency, Three Dimensional Integrated Circuits (3D-ICs) is considered as the near future for VLSI system. Combining with the Network-on-Chip infrastructure to obtain 3D Networks-on-Chip (3D-NoCs), the new on-chip communication paradigm brings several advantages. However, thermal dissipation is one of the most critical challenges for 3D-ICs, where the heat cannot easily transfer through several layers of silicon. Consequently, the high-temperature area also confronts the reliability threat as the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Black’s model. Apparently, 3D-NoCs and 3D ICs must tackle this fundamental problem in order to be widely used. However, the thermal analyses usually require complicated simulation and might cost an enormous execution time. As a closed-loop design flow, designers may take several times to optimize their designs which significantly increase the thermal analyzing time. Furthermore, reliability prediction also requires both completed design and thermal prediction, and designer can use the result as a feedback for their optimization. As we can observe two big gaps in the design flow, it is difficult to obtain both of them which put 3D-NoCs under thermal throttling and reliability threats. Therefore, in this work, we investigate the thermal distribution and reliability prediction of 3D-NoCs. We first present a new method to help simulate the temperature (both steady and transient) using traffic values from realistic and synthetic benchmarks and the power consumption from standard VLSI design flow. Then, based on the proposed method, we further predict the relative reliability between different parts of the network. Experimental results show that the method has an extremely fast execution time in comparison to the acceleration lifetime test. Furthermore, we compare the thermal behavior and reliability between Monolithic design and TSV-based design. We also explore the ability to implement the thermal via a mechanism to help reduce the operating temperature.

HEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC&rsquo, s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW, this is important factor for handheld applications.

LED is an ultra-lightweight block cipher targeting resource-constrained devices. The current hardware architectures of this cipher utilize large logic area, operate in low frequencies and have low throughput. To improve the trade-offs between area utilization and performance, an iterative round-based architecture of LED block cipher is implemented in this paper. LED algorithm is available in 64-bit and 128-bit key sizes. In this paper, the focus is on the 64-bit key with 64-bit block size. This algorithm is implemented on various Field Programmable Gate Array (FPGA) devices. The design is verified on several Altera and Xilinx devices using Altera Quartus II, ModelSim and Xilinx ISE simulators. Both low-cost and high-end FPGA devices were targeted. Tradeoffs between area and performance were considered, with the optimization for performance. The throughput and maximum operating frequency are benchmarked with the existing literature and better performance is achieved. The results show large improvements in maximum operating frequency and throughput as well as reduction in area utilization compared to recent designs of round-based LED block cipher.

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates, the sensitivity to thermal hotspots and stress issues due to the difference in temperature between layers are preventing TSV-based 3D-ICs from being widely and efficiently used. Due to defect clustering, 3D-ICs could have multiple defects in the same region which cannot be detected by using error correction codes while dedicated testing could take a significant number of testing cycles. This paper presents a 2D Parity Product Code (2D-PPC) with the ability to correct one fault and detect, at least, two faults. With the extension using Orthogonal Latin Square, 2D-PPC could detect multiple defects while reasonably increasing the area cost and latency.

Histogram of Oriented Gradient (HOG) in combination with Supported Vector Machine (SVM) has been used as an efficient method for object detection in general and human detection in particular. Human detection using HOG-SVM in hardware shows high classification rate at higher throughput when compared with deep learning methods. However, data dependencies and complicated arithmetic in HOG feature generation and SVM classification limit the maximum throughput of these applications. In this paper, we propose a novel high-throughput hardware architecture for human detection by co-optimizing HOG feature generation and SVM classification. The throughput is improved by using a fast, highly-parallel and low-cost HOG feature generation in combination with a modified datapath for parallel computation of SVM and HOG feature normalization. The proposed architecture has been implemented in TSMC 65nm technology with a maximum operating frequency of 500MHz and throughput of 139fps for Full-HD resolution. The hardware area cost is about 145kGEs along with 242kb SRAMs.

High-Efficiency Video Coding (HEVC), also known as H.265 and MPEG-H Part 2, is the newest video coding standard developed to address the increasing demand for higher resolutions and frame rates. In comparison to its predecessor H.264/AVC, HEVC achieved almost double of compression performance that is capable to process high quality video sequences (UHD 4K, 8K; high frame rates) in a wide range of applications. Context-Adaptive Baniray Arithmetic Coding (CABAC) is the only entropy coding method in HEVC, whose principal algorithm is inherited from its predecessor. However, several aspects of the method that exploits it in HEVC are different, thus HEVC CABAC supports better coding efficiency. Effectively, pipeline and parallelism in CABAC hardware architectures are prospective methods in the implementation of high performance CABAC designs. However, high data dependence and serial nature of bin-to-bin processing in CABAC algorithm pose many challenges for hardware designers. This paper provides an overview of CABAC hardware implementations for HEVC targeting high quality, low power video applications, addresses challenges of exploiting it in different application scenarios and then recommends several predictive research trends in the future.

Deep Neural Network (DNN) architectures have been recently considered as the big breakthrough for a variety of applications. Because of the high computing capabilities required, DNN has been unsuitable for various embedded applications. Many works have been trying to optimize the key operations, which are multiply-and-add, in hardware for a smaller area, higher throughput, and lower power consumption. One way to optimize these factors is to use the reduced bit accuracy; for examples, Google's TPU used only 8-bit integer operations for DNN inference. Based on the characteristics of different layers in DNN, further bit accuracy can be changed to preserve the hardware area, power consumption, and throughput. In this work, the thesis investigates a hardware implementation of multiply-and-add with variable bit precision which can be adjusted at the computation time. The proposed design can calculate the sum of several products with the bit precision ranging from 1 to 16 bits. The hardware implementation results on Xilinx FPGA Virtex 707 development kit show that our design occupies smaller hardware and can run at a higher frequency of 310 MHz, while the same functionality implemented with and without DSP48 blocks can only run at a frequency of 102 MHz. In addition, to demonstrate that the proposed design is applicable effectively for deep neural network architecture, the paper also integrated the new design in the MNIST network. The simulation and verification results show that the proposed system can achieve the accuracy up of to 88%.

This paper presents "On Communication Through-Silicon-Via Test" (OCTT), an ECC-based method to localize faults without halting the operation of TSV-based 3D-IC systems. OCTT consists of two major parts named Statistical Detector and Isolation and Check. While Statistical Detector could detect open and short defects in TSVs that work without interrupting data transactions, the Isolation and Check algorithm enhances the ability to localize fault position. The Monte-Carlo simulations of Statistical Detector show ×2 increment in the number of detected faults when compared to conventional ECC-based techniques. While Isolation and Check helps localize the number of defects up to ×4 and ×5 higher. In addition, the worst case execution time is below 65,000 cycles with no performance degradation for testing which could be easily integrated into real-time applications.

In this paper, we propose a high-throughput and low-latency AES architecture for wideband and real-time applications such as surveillance cameras, video conference, motion detection, IoT gateways, data store encryption… Our design uses an outer round pipeline technique to achieve high throughput. The design has been modelled in RTL VHDL and then synthesized with a 45nm CMOS technology using Synopsys Design Compiler. The implementation results show that the proposed architecture achieves a throughput of 111.3Gbps and a latency of 12.6ns at the maximum operating frequency of 870MHz. With the same 45nm CMOS technology, our design has area efficiency (2.4 times) and energy efficiency (4.7 times) higher than other related works.

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs); however, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are threating TSV-based 3D-ICs. On the other hand, real-time applications demand short response time to the new occurrence faults which make online testing become a critical challenge. In order to solve this problem, this paper presents an online method named TSV-IaS which supports detecting and correcting open and short defect TSVs by isolating and shifting the signals of TSVs then analyzing the output syndromes. Furthermore, we also present an analytical analysis on detectability and response time of the proposal. Results show that with R redundant TSVs in a group, the proposed method can fully correct R defects and detect R+1 defects while keeping a low-cost structure. Monte-Carlo simulations also demonstrate a 100% detection rate with 32-cycles based tests.

The soft error rates per single-bit due to alpha particles in sub-micron technology is expectedly reducedas the feature size is shrinking. On the other hand, the complexity and density of integrated systems are accelerating which demand ecient soft error protection mechanisms, especially for on-chip communication. Using soft error protection method has to satisfy tight requirements for the area and energy consumption, therefore a low complexity and low redundancy coding method is necessary. In this work, we propose a method to enhance Parity Product Code (PPC) and provide adaptation methods for this code. First, PPC is improved as forward error correcting using transposable retransmissions. Then, to adapt with dierent error rates, an augmented algorithm for configuring PPC is introduced. The evaluation results show that the proposed mechanism has coding rates similar to Parity check’s and outperforms the original PPC.Keywords Error Correction Code, Fault-Tolerance, Network-on-Chip. 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In image compression and video coding, quantization error helps to reduce the amount of information ofthe high frequency components. However, in temporal prediction the quantization error contributes its valueas noise in the total residual information. Therefore, the residual signal of the inter-picture prediction isgreater than the expected one and always differs zero value even input video contains only homogeneousframes. In this paper, we reveal negative effects of quantization errors in inter prediction and propose a videoencoding scheme which is able to avoid side effects of quantization errors in the stationary parts. We proposeto implement a motion detection algorithm as the first stage of video encoding to separate the video into twoparts: motion and static. The motion information allows us to force residual data of non-changed part to zeroand keep the residual signal of motion regularly. Beside, we design block-based filters which improve motionresults and filter those results fit into block encode size well. Fixed residual data of static information permitsus to pre-calculate its quantized coefficient and create a bypass encoding path for it. Experimental resultswith the JPEG compression (MJPEG-DPCM) showed that the proposed method produces lower bitrate thanthe conventional MJPEG-DPCM at the same quantization parameter and a lower computational complexity.

Recently, Artificial Neural Network (ANN) has emerged as the main driving force behind the rapid developments of many applications. Although ANN provides high computing capabilities, its prohibitive computational complexity, together with the large area footprints of ANN hardware implementations, has made it unsuitable for embedded applications with real-time constraints. Stochastic Computing (SC), an unconventional computing technique which could offer low-power and area-efficient hardware implementations, has shown promising results when applied to ANN hardware circuits. In this paper, efficient hardware implementations of ANN with conventional binary radix computation and SC technique are proposed. The system’s performance is benchmarked with a handwritten digit recognition application. Simulation results show that, on the MNIST dataset, the 10-bit binary implementation of the system only incurs an accuracy loss of 0.44% compared to the software simulations. The preliminary simulation results of the SC neuron block show that the output is comparable to the binary radix results. FPGA implementation of the SC neuron block has shown a reduction of 67% in the number of LUTs slice.

Huge bandwidth demand along with the requirement to synchronize data structures between different processing structures in multiprocessor system-on-chip (MPSoC) lead to the need to design dedicated memory access controllers. This paper presents the design of a reconfigurable multi-function memory direct memory controller (ReDMAC) for high-performance MPSoCs. The ReDMAC supports the capability of dynamic reconfiguration by enabling the hardware fabrics to be synthesized into various functions even if the system is working. The ReDMAC can support four operating modes, including direct memory access, matrix transposing, data sorting, and matrix merging. The ReDMAC has been modeled at the Register Transfer Level (RTL) using VHDL language. The controller has been simulated and evaluated on reconfigurability to work with individual functions. The controller is also synthesized with the Synopsys Design Compiler tool to compare hardware costs with the independent implementation of each individual function. Simulation and synthesis results indicate that the proposed design meets the required functionality, while the area of the controller decreases about three times compared to total area of independent function cores.

This paper presents a low energy AES encryption core targeting for hardware security implementation in IoT systems. The proposed AES core architecture employs the improved shared S-box scheme with 32-bit datapath and low switching activity shift-row operation. Consequently, the proposed AES encryption core can provide good tradeoff with the area of 4.3 kgates and the energy consumption of 4 pJ/bit in 32 nm CMOS technology library.

Soft errors are expecting to be accelerated with the shrinking of feature sizes due to low operating voltages and high circuit density. However, soft error rates per single-bit is expectedly reduced with technology scaling. With tight requirements for the area and energy consumption, using a low complexity and high coding rate error correction code (ECC) to handle soft errors in on-chip communication is necessary. In this work, we use Parity Product Code (PPC) and propose several supporting mechanisms to detect and correct soft errors. First, PPC can work as a parity check to detect single event upset (SEU) inside each flit. Then, to reduce the needed retransmission, a Razor flip-flop with parity check (RFF-w-P) is proposed to work with PPC. Since PPC can act like forward error correction (FEC), we also present a selective transmission in bit-indexes by using a transposable FIFO. Therefore, the proposed mechanism not only guarantee single error detection/correction but also provide 2+ error correction as FEC. The proposed work also reduce the area cost of FIFO in comparison to traditional coding methods and adapt too multiple error rates.

The Network-on-Chip (NoC) paradigm has been emerging as new communication solution for the Ultra Large-Scale Integration System-on-Chips (SoCs). Many real-time embedded SoCs support multi-rate applications that requires the NoC has to offer different Quality-of-Service level. This paper proposes and implements a reconfigurable hybrid router that combines the hybrid switching scheme with the priority-driven arbitration mechanism. The router supports both guaranteed-throughput (GT) service and best-effort (BE) service without reserving resources for GT service. In addition, the proposed solution not only guarantees GT-type QoS, but also enhance the average performance for BE service by using communication resources efficiently. The router has been modelled and then implemented on Xilinx Virtex-7 FPGA technology. The obtained results show that this router can guarantee reliability and enhance significantly the average performance of BE load compared with the generic router while the overheads in terms of area and power consumption are acceptable.

International audience; Connected devices are getting attention because of the lack of security mechanisms in current Internet-of-Thing (IoT) products. The security can be enhanced by using standardized and proven-secure block ciphers as advanced encryption standard (AES) for data encryption and authentication. However, these security functions take a large amount of processing power and power/energy consumption. In this paper, we present our hardware optimization strategies for AES for high-speed ultralow-power ultralow-energy IoT applications with multiple levels of security. Our design supports multiple security levels through different key sizes, power and energy optimization for both datapath and key expansion. The estimated power results show that our implementation may achieve an energy per bit comparable with the lightweight standardized algorithm PRESENT of less than 1 pJ/b at 10 MHz at 0.6 V with throughput of 28 Mb/s in ST FDSOI 28-nm technology. In terms of security evaluation, our proposed datapath, 32-b key out of 128 b cannot be revealed by correlation power analysis attack using less than 20 000 traces.

The increasing amount of digital video with supreme quality requires more efficient compression. As the complexity of video coding algorithm is rising, there are more demands for hardware accelerators and customized hardware. Context-based Adaptive Binary Arithmetic Coding (CABAC) is the only entropy coding method adopted in the latest video compression standard, High Efficiency Video Coding (HEVC). Binary Arithmetic Encoder (BAE) is an essential component in CABAC, where the compression process happens. Because of the high data dependency and sequential coding characteristic, it is challenging to parallelize BAE. In this work, we proposed a low-cost and high-throughput hardware architecture for one core of BAE in HEVC. Our 4-stage pipelined BAE architecture is capable of processing one regular bin and up to 4 bypass bins per clock cycle with 30% reduction in terms of area when compared with the designs for one-core CABAC architecture. The design can compress an average of 1.4 bins per cycle. It achieves a throughput of 1 Gbin/s at the maximum operating frequency of 810 MHz with the area of 2.2 kGEs and the power consumption of 2.0 mW in Nangate 45nm technology.

This paper presents a proposal and implementation of a multi-mode full-reconfigurable router for Network-on-Chip (NoC). First, the router supports a hybrid packet-switching architecture that is dynamically reconfigurable to exchange between wormhole and virtual cut-through switching schemes at run-time. Therefore, it reaches a higher average performance than wormhole switching, while decreasing the implementation cost in comparison with the virtual cut-through switching. Second, the router is equipped a Quality-of-Services (QoS)-driven arbiter. Therefore, the proposed solution not only guarantees the guaranteed-throughput service without reserving resources but also enhances the average performance for the best-effort service by using network resources efficiently based on the priority inheritance arbitration mechanism. Third, the router is enhanced with the dynamically deadline-aware rerouting mechanism. In contention situation, the router can configure the routing computation unit to reroute the packet to another path so as to reduce the waiting interval of the blocked packets. The router was designed at the Register Transfer Level and modeled using VHDL language and then synthesized with Xilinx Virtex-7 FPGA technology. The experimental results prove that the proposed router is reliable and can improve the average performance of different QoS loads significantly compared with the generic routers while the area and power overhead are acceptable.

Network-on-Chip (NoC) paradigm allows designers to integrate efficiently more intellectual properties (IPs) into a single chip system. However, the power consumption has become one of the most critical issues for designing such large complex systems. Low power design can be achieved by scaling the voltage and frequency of the target components. The question is how to make the voltage-frequency scaling adaptable to the required performance of the system at run-time while reducing as much as possible the power consumption. This paper presents a novel solution for NoC architectures to reduce power consumption using fuzzy-logic algorithms. As the communication traffic is not equally distributed over the network architecture, depending on the communication load, each router in the network will be applied with a corresponding voltage and frequency to minimize the power consumption while keeping necessary communication throughput.

Network-on-Chip (NoC) has been proposed as the communication paradigm for the Ultra Large-Scale Integration System-on-Chips. One of the key factors that determine the performance and the implementation cost of a NoC is the switching scheme. In this paper, we propose and implement a hybrid switching router based on the combination of wormhole and virtual cut-through switching schemes. The router is dynamically reconfigurable to exchange between switching schemes at run-time, therefore, it achieves higher average performance than wormhole switching, while reducing the implementation cost in comparison with the virtual cut-through switching. The router has been modelled at Register Transfer Level in VHDL language and then synthesized on Xilinx Virtex-7 FPGA technology. The experimental results show that this router can guarantee reliability and reduce latency about 30.2% and increase average throughput approximately 38.9% compared with the generic router. The area and power overhead compared with the generic router are acceptable.

As the rapid advancement in semiconductor technology leads to shrinking of transistor sizes and the integration scale is over one billion transistors, Reconfigurable Network-on-Chips becomes a new methodology providing adaptive infrastructure resources as well as flexible network protocols to adapt to dynamic environment. In this paper, we propose a routing-path tracking and updating mechanism for reconfigurable Network-on-Chips. The hardware architectures used to implement the proposed mechanism such as modified RNoC routers and Network Interfaces are introduced. With this routing-path tracking and updating mechanism, packet transmission delay can be reduced from 4.92% to 33.33% depending on the data structures.

In this paper, we propose a novel AES microarchitecture with 32-bit datapath optimized for low-power and low-energy consumption targeting IoT applications. The proposed design uses simple shift registers for key/data storage and permutation to minimize the area, and the power/energy consumption. These shift registers also minimize the control logics in the key expansion and the encryption path. The proposed architecture is further optimized for area and/or power/energy consumption by selecting a suitable implementation of S-boxes and applying the clock gating technique. The implementation results in TSMC 65nm technology show that our design can save 20% of area or 20% of energy per bit at the same area when compared with the current 32-bit datapath designs. Our design also occupies smaller core area with lower energy per bit and at least 4 times higher in throughput in comparison with other 8-bit designs in the same technology node.

In this paper, we present a novel router architecture for implementing a Reconfigurable Network-on-Chip (RNoC) at high-level design using SystemC. The RNoC is an adaptive NoC-based system-on-chip providing a dynamic reconfigurable communication mechanism. By adding a virtual port – named Routing Modification port – into the conventional router architecture, the network router is able to route communication data flexibly whenever the target routing path is blocked, by unwanted defects or intently by a software programme to meet the requirements of applications. The proposed architecture has been modeled in SystemC/C++, simulated and verified within a 2D mesh 5×5 network platform. In normal communication mode, the static XY routing algorithm is used while the West-First algorithm with a proposed prohibited router surrounding technique is applied in reconfiguration mode. Experimental results are also reported to compare the performance of the network architecture in different operation modes as well as with other works.

Low power design can be easily achieved by scaling the voltage and frequency of the target systems. The most concerning issue is how to make the voltage-frequency scaling adaptable to the required performance of the system at run-time. In this paper, we present the design of a voltage-frequency controller for network-on-chip routers based on fuzzy-logic processing. The communication traffic of a network router will be predicted by a fuzzy-logic algorithm. Then the voltage and frequency of the router will be scaled according to the predicted results in order to get power consumption optimal for the network router. The most important part of the proposed controller, the fuzzy-logic processor (FLP), is modeled and verified using VHDL and then implemented on FPGA devices.

Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors, or soft errors, have severe consequences on chip performance, such as deadlock, data corruption, packet loss and increased packet latency. In this paper, we propose a soft-error resilient 3D-NoC router (SER-3DR) architecture for highly-reliable many-core Systems-on-Chips. The proposed architecture is able to recover from transient errors occurring in different pipeline stages of the SER-3DR.We implemented the architecture in hardware with 45 nm CMOS technology. Evaluation results show that SER-3DR is able to achieve a high level of transient error protection with a latency increase of 18.16%, an additional area cost of 14.98% and a power overhead of 5.90% when compared to the baseline router architecture.

H.264 is the most popular video coding standard with high potent coding performance. For its efficiency, the H.264 is expected to encode real-time and/or high-definition video. However, the H.264 standard also requires highly complex and long lasting computation. To overcome these difficulties, many efforts have been deployed to increase encoding speed. Besides, with the revolution of portable devices, multimedia chips for mobile environments are more and more developed. Thus, power-oriented design for H.264 video encoders is currently a tremendous challenge. This paper discusses these trends and presents an overview of the state of the art on power features for different H.264 hardware encoding architectures. We also propose the VENGME’s design, a particular hardware architecture of H.264 encoder that enables applying low-power techniques and developing power-aware ability. This low power encoder is a four-stage architecture with memory access reduction, in which, each module has been optimized. The actual total power consumption, estimated at Register-Transfer-Level (RTL), is only 19.1 mW.

Motion JPEG simply compresses each frame in a video sequence using JPEG still image compression standard. This video codec satisfies power consumption and real-time properties of embedded systems while having very low complexity. However, the downside is its inefficiency in reducing the bit-rate because there are still redundancies between encoded frames. In this paper, we focus on reducing temporal redundancies in MJPEG using a motion detection algorithm, called Zipfian estimation. The Zipfian estimation helps MJPEG extract separately the moving blocks and the stationary blocks then removes temporal redundancies by minimizing encoded bit-stream of stationary blocks and encoding only the residuals of the moving blocks between adjacent frames. Experimental results show that the proposed method can provide twice compression ratio as much as the conventional MJPEG, and an approximate quality and bit-rate as the H.264/AVC (Intra-mode). Even the proposed method uses the Zipfian estimation, it still has smaller number of operations than the conventional MJPEG if the percentage of the static scene is equal or greater than 60%. Compared with the H.264/AVC Intra mode when turning off the rate-distortion optimization, the running time of the proposed method is still only a half.

Because of significant bit rate reduction in comparison to the previous video compression standards, the H.264/AVC has been successfully used in a wide range of applications. In hardware design for H.264/AVC video encoders, power reduction is currently a tremendous challenge. This paper presents a survey of different H.264/AVC hardware encoders focusing on power features and power reduction techniques to be applied. A new H.264/AVC hardware encoder, named VENGME, is proposed. This low power encoder is a four-stage architecture with memory access reduction, in which, each module has been optimized. The actual total power consumption, estimated at RTL level, is 19.1mW.

The integration of a variety of IP cores into a single chip to meet the high demand of new applications leads to many challenges in timing issues, especially the interface between different clock domains. Globally Asynchronous, Locally Synchronous (GALS) approach addresses these challenges by dividing a chip into several independent subsystems working with different clock signals. In multi-synchronous Network-on-Chip (NoC) based on GALS architecture, the network routers run with different frequencies, so the problem is how to transfer data safely and efficiently between them. In order to build a synchronization unit to tackle this problem, in this paper, we propose a novel efficient asynchronous First-In-First-Out architecture targeting to multi-synchronous NoCs. Token ring structure, register-based memory, and modified Asynchronous Assertion - Synchronous De-assertion techniques are applied to improve the performance of the proposed asynchronous FIFO. After simulating and verifying the design, we have implemented our asynchronous FIFO architecture with CMOS 180nm technology from AMS. Implementation results are analyzed and compared with previous works to show the strong points of our design.

In this paper, we propose a design methodology for the inter-prediction in H.264/AVC codecs by addressing the relationship between its main processes. The target of this methodology is to optimize the design in order to get better performance while keeping a reasonable design cost. An efficient hardware architecture for the inter-prediction in H.264/AVC codecs is then proposed with three key techniques: a modified full search algorithm with bandwidth efficiency, pipelining technique, and data reuse strategy. With this approach, the inter-prediction has been successfully designed and implemented with a CMOS 180nm technology which provides low cost in terms of latency, hardware overhead and memory bandwidth. The design is initially targeted to CIF video format; however, it is obviously suitable for real-time HD 1080p video format.

This paper presents the design of a System on Programmable Chip (SoPC) based on Field Programmable Gate Array (FPGA) for speech recognition in which Mel-Frequency Cepstral Coefficients (MFCC) for speech feature extraction and Vector Quantization (VQ) for recognition are used. The execution speed of the blocks in the speech recognition system is surveyed by calculating the number of clock cycles while executing each block.

The Network-on-Chip (NoC) paradigm has been recently known as a competitive on-chip communication solution for large complex systems such as multi-core and/or many-core systems thanks to its advantages. However, one of the main challenging issues for NoC designers is that the network performance should be rapidly and early pre-proved for target applications. In this paper, we present a NoC simulation and evaluation platform allowing designers to simulate and evaluate the NoC performance with different network configuration parameters. The proposed platform has been implemented in SystemC to be easily modified in order to adapt different simulation strategies and save the simulation time. With this platform, designers can deal with: (i) configuring the network topology, flow control mechanism and routing algorithm; (ii) configuring various regular and application specific traffic patterns; and (iii) simulating and analyzing the network performance with the assigned traffic patterns in terms of latency and throughput. Obtained results with a 4 × 4 2D-mesh NoC architecture will be presented and discussed in this paper to demonstrate the proposed platform.