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A continuous‐time offset cancelation and gain calibration strategy is proposed for open‐loop residue amplifiers of pipeline ADC's. Utilizing a reliable technique for detecting gain and offset error, also saving digital amounts of the signals that are resulted from the calibration loop, data conversion proceeds without any interruption. In addition, due to sharing this structure between the several RA stages in ADC, power consumption and area occupation are decreased. Also, this strategy does not require extra circuits, like replica residue amplifier or wide‐bits digital processor for offset and gain‐error correction. Using digital circuits results in multiplexing clock frequency; also, utilizing a unit gain and offset calibration structure for the whole RA in the main ADC results in a significant power consumption reduction. The simulations show that the input‐referred offset is reduced to around 30 μV. Also, the gain calibration loop provides a gain of 8 with an error deviation less than 0.001. Post‐layout simulation results are presented at all process corners and various temperatures, using HSPICE software and 0.18 μm standard CMOS technology in 14‐bit 200 MS/s Pipeline ADC with 23 dB improvement in SNR and 3.9 bit in ENOB. [ABSTRACT FROM AUTHOR]

This paper presents an improved bottom-plate sampling sample-and-hold (S/H) architecture for high speed and high linearity analog to digital converters (ADCs). The proposed circuit reduces the charge injection employing a switch at the S/H's output. The S/H circuit has been laid out in 0.35 um CMOS technology and simulated using standard level 49 SPICE parameters. The simulation result shows that the spurious free dynamic range (SFDR) of 80 dB is achieved up to the sampling frequency of 250 MS/s at nyquist input frequency with 1.6 $$(V_{P-P})$$ differential output swing which is able to realize an ADC of 14-bits resolution. [ABSTRACT FROM AUTHOR]

In this paper a new operational amplifier is presented based on the conventional folded cascode Op-Amp structure. A new method of positive feedback is used to increase DC-gain. Contrary to conventional designs this method does not decrease the speed of the folded cascode Op-Amp in the closed loop configuration. Simplicity is the other advantage of the proposed Op-Amp in comparison with the conventional structures. In this method, DC-gain improves by adding only two devices to the folded cascode structure. The additional devices neither decrease the bandwidth nor increase the power consumption, to a great extent. Proposed structure has been simulated by HSPICE software using level 49 parameters ( BSIM3v3) in a typical 0.35 μm CMOS technology. HSPICE simulation confirms the theoretical estimated improvements. [ABSTRACT FROM AUTHOR]

This paper proposes the method to implement a general form of membership functions for fuzzy systems in CMOS technology. These membership functions are a general form of triangular types and those functions which are used in linguistic hedge fuzzy logic, hence can offer better performance in almost all applications. The comparison between the proposed method and previously reported works shows better performance in all parameters. Designed circuits to implement these types of membership functions are simulated using HSPICE by level 49 parameters (BSIM3v3) in 0.35 μm standard CMOS technology. Current mode realization of the circuits leads to simple and intuitive configurations. The Rational Power Generator Module (RPGM) generates powers with the resolution of 0.03125 and using seven programming bits. The simulation results of RPGM demonstrate a RMS error of 1.42% and a maximum power consumption of 1.05 mW. [ABSTRACT FROM AUTHOR]

Abstract: A new open-loop high-speed CMOS sample-and-hold is presented. Based on new method for further reduction of voltage-dependent charge injection, a new CMOS sample-and-hold was designed. Simulation results confirm the effectiveness of this method. Over 10dB improvement in signal-to-noise ratio, compared to the signal-to-noise ratio of conventional bottom plate sampling S/Hs was achieved with this method. A comparison between newly designed S/H and the bottom-plate sampling S/H is presented. [Copyright &y& Elsevier]

Abstract: A new high-speed successive approximation analog-to-digital converter (ADC) architecture is presented. Two-bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two digital-to-analog converter (DACs), is another novelty of the new architecture. The proposed DAC structure allows a substantial reduction in overall control logic complexity. A 10-bit 40Ms/S successive approximation ADC was designed based on the proposed architecture in CMOS technology. The simulation results show that the proposed architecture introduces 7% reduction in power consumption over conventional architecture. Furthermore, chip area for the new ADC is 40% less than what otherwise would be needed by an ADC using conventional architecture. [Copyright &y& Elsevier]