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This article studies the sharing control scheme for a hybrid 48 V/375 V/400Vac ac/dc microgrid, based on classical droop control and a novel approach for secondary control. In this article, both the dc and ac grids are controlled by a $P/V$ droop strategy. At the ac grid, this assumes a main resistive component in the distribution line impedance. The droop control voltage error in steady state is compensated by a novel and simple secondary control approach. The proposed control strategy is based on the calculation of the optimum power flow in each operating point and the real-time modification of the droop characteristics of the converters involved in the power flow calculation. The proposed control is also capable of eliminating the induced voltage drop when using virtual impedance and incorporating any power sharing criteria for the converters contributing to the power production, being this flexibility one of its more important characteristics. [ABSTRACT FROM AUTHOR]

This letter presents a periodically refreshed capacitive floating level shifter (CFLS) for applications that require a conditional switching signal. The proposed structure can generate a floating signal without additional bias voltage, and all coupling capacitors (CCs) can be simultaneously refreshed. Digital low-dropout (DLDOs) regulators are integrated to show how the leakage current from a CC affects the DLDOs that are driven by conventional and proposed CFLSs. Results are measured according to the temperature and supply voltage. With a 28-nm CMOS process, the proposed CFLS achieves a delay of 8.9 ns including the I/O buffer delay and an energy consumption of 788 fJ per cycle at VDD = 0.9 V. [ABSTRACT FROM AUTHOR]

This paper presents a design-oriented analysis on the voltage stability and the transient fault current limitation of voltage-controlled modular multilevel converter (MMC) with L-filters. First, a dual-loop voltage control based on the L-filter plant is systematically designed, where the upper limits of controller parameters to ensure the small-signal stability are identified. Then, considering the transient current limitation during faults, the lower boundaries of inner current controller parameters are derived. Within the region of allowed controller parameters, the optimization is further made to minimize the closed-loop output impedance of MMC, which enhances the output voltage stiffness against the load current disturbance. Lastly, time-domain simulations corroborate the theoretical analysis. [ABSTRACT FROM AUTHOR]

This article describes the development of an 18 kV, 30 kW power supply for a pulsed current load with the maximum current of 20 A and a di/dt equal to 100 A/μs. The achieved output ripple is less than 0.01%. In such a high level of precision, the most important issues are considerable difference between the instantaneous and average output powers, as well as insufficient reaction speed of the converter to the fast load change. Very low level of the voltage feedback and its sensitivity to the noise. The first issue necessitates a notable overdesign of the converter switches if the output voltage precision is dedicated to the converter. The second issue raises the problems relevant to observing the voltage ripple and providing it for the control loop. This article proposes, a fast and high current linear regulator developed based on the load current feedforwarding. Using this approach, the fast regulator compensates the voltage change caused by a high level of instantaneous power. The main converter maintains the average power. Thus, there is no need for converter overdesigning. Furthermore, the problems relevant to the high voltage feedback and providing it for the control loop are removed. The voltage feedback is solely served to correct the current loop probable error. Hence, the sensitivity of the control loop against the existing noise is minimized. Despite existing a 600 nF capacitor as the output capacitor, the output voltage drop is less than 0.01% in a wide range of the output current pulse up to 250 μs. The power supply is constructed and experimental results are provided to verify the mentioned specifications. [ABSTRACT FROM AUTHOR]

An array of proportional-resonant regulators is often used in shunt active power filters to control the grid currents and reduce the harmonic distortion caused by a distorting load. The voltage that is necessary to compensate for the current harmonics must be consistent with the available dc-link voltage. In this article, three adaptive algorithms for the exploitation of the dc-link voltage are developed and compared. These algorithms adaptively change the voltage saturation of each regulator to preserve the control capability of the fundamental component of the current when the available voltage is not enough to control the filter current. Simultaneously, they try to improve the quality of the grid current because the dc-link voltage of the active power filter is allocated to the regulators to compensate only the most significant harmonics. Some experimental results are shown to demonstrate the feasibility of the three algorithms. [ABSTRACT FROM AUTHOR]

On-chip digital low-dropout (LDO) regulators enable fast dynamic voltage scaling, reducing power consumption. Integrating these regulators into a highly resistive environment has complicated the design of power delivery systems. With the increasing sensitivity of complex integrated systems to power noise, effective approaches to distribute on-chip LDOs are needed due to the limited metal resources. In this article, a methodology is proposed to distribute the pass gates of a system of on-chip digital LDOs. The distribution of the pass gates considers the location of the load currents to reduce voltage variations across the power grid. The proposed pass gate distribution topology reduces the maximum voltage variations across the grid, on average, by two to three times under nonuniform load distributions. [ABSTRACT FROM AUTHOR]

Flux-weakening (F-W) based on feedback voltage regulation is commonly adopted in interior permanent magnet synchronous motor drives. Voltage space vector magnitude is controlled in a closed loop, modifying the current reference, following a value related to the inverter limitations. A stable and fast voltage control allows to operate with lower voltage margin, leading to higher torque versus speed capability. Theoretical analysis and gain adaptation of the F-W regulation loop was reported by Bolognani et al. partially overcoming the difficulties due to the strong nonlinearity of the plant. An approximated closed-form design method was proposed and refined by Bedetti et al. This allowed the application of the algorithm to drives where autotuning is needed, ensuring stability and dynamical performances. A fundamental enhancement is introduced in this article, namely the use of a speed regulator with explicit torque reference output. An advantage of this technique is that the speed loop becomes linear in the whole operating range and an accurate control of machine torque is possible. Thanks to a novel gain adaptation for the voltage regulator, the F-W behavior is decoupled from the speed control response at speed steady-state (at constant or slowly changing torque), improving performance of the overall drive control. Adoption of this novel method allows smooth operation with invariant dynamical behavior of both the speed and F-W control loops. Extensive simulations and experimental tests are reported to prove the validity of the proposal. A sensorless operation of the drive system has also been considered in the tests to further validate the proposed solution. [ABSTRACT FROM AUTHOR]

The flipped-voltage-follower-based low-dropout regulator (LDO) has drawn attention for its fast response and reduced complexity, while super source follower can be combined to push the pole at the gate of the pass device to high frequency. But the maximum load current and minimum load capacitance of this topology are limited, especially when the poles and zero from the SSF are omitted in previous designs. This paper proposes a solution to extend the ranges of the load current and load capacitance, by implementing a small feed-forward capacitor ($C_{F}$) and a damping factor control circuitry. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot. The proposed LDO is verified in a 65-nm CMOS process with 0.008 mm2 active area. The measured voltage undershoot is 80 mV with a load steps from 100 μA to 50 mA with 2-ns edge times, with no external capacitor. And the maximum load capacitance can be extended to 2 nF. A figure-of-merit of 0.8 mV is achieved. [ABSTRACT FROM AUTHOR]

This work is based on the vision that the ultimate power integrity and efficiency may be best achieved via a heterogeneous chain of voltage processing starting from onboard switching voltage regulators (VRs), to on-chip switching VRs, and finally to networks of distributed on-chip linear VRs. As such, we propose a heterogeneous voltage regulation (HVR) architecture encompassing regulators with complimentary characteristics in response time, size, and efficiency. By exploring the rich heterogeneity and tunability in HVR, we develop systematic workload-aware power management policies to adapt heterogeneous VRs with respect to workload change at multiple temporal scales to significantly improve system power efficiency while providing a guarantee for power integrity. The proposed techniques are further supported by hardware-accelerated machine learning (ML) prediction of nonuniform spatial workload distributions for more accurate HVR adaptation at fine time granularity. Our evaluations based on the PARSEC benchmark suite show that the proposed adaptive three-stage HVR reduces the total system energy dissipation by up to 23.9% and 15.7% on average compared with the conventional static two-stage voltage regulation using off-chip and on-chip switching VRs. Compared with the three-stage static HVR, our runtime control reduces system energy by up to 17.9% and 12.2% on average. Furthermore, the proposed ML prediction offers up to 4.1% reduction of system energy. [ABSTRACT FROM AUTHOR]

One promising solution for future large wind turbine power conversion is to use medium-voltage power conversion systems for high efficiency and high power-density, e.g., by using a cascaded structure presented in this paper. However, a medium-frequency (MF) oscillation issue was observed while testing the experimental prototype of the above system. Given the complex multivariable coupling models of the multiwinding transformer and multiple inverters, conventional single-variable theories are not suitable. Therefore, this paper presents a new decoupling analysis method. Using a proposed linear transformation matrix, the output currents of multiple inverters can be transformed to a summation (grid) current and difference currents, where the former is the summation of inverter currents and the latter are the differences between currents of any two inverters. This transformation has enabled the use of single-variable theories, e.g., Bode diagram to analyze the summation current and difference current separately. It was found that the MF oscillation issue is caused by the equivalent impedance of the summation current being much larger than that of the difference current. Specifically, using small controller parameters cannot ensure the grid current quality and using large parameters may cause oscillation in the difference current. The proposed method can provide guidelines to design the parameters of current regulators and filters in multiple-inverter systems. Experimental results of a downscaled wind energy conversion system are presented to verify the proposed method. [ABSTRACT FROM AUTHOR]

The offset voltage variation of current sensors is mainly due to the thermal drift, and it causes torque ripples in current vector-controlled surface permanent magnet synchronous motor (SPMSM) drives. This paper proposes a current offset error compensator for the current vector-controlled SPMSM drives used in robotic applications, wherein dynamic movements frequently occur. The current offset error compensator for this kind of applications should provide a stable performance in estimating current offset errors during dynamic movements. Especially, the current offset error compensator should be able to suppress interferences from outer-loop controllers. In this paper, analysis on a synchronous frame current regulator is performed to see the relation between current commands and measured currents under the current offset error existing condition. The analysis shows that pure current offset error components can be obtained by subtracting low-pass filtered current commands from measured currents in a synchronous reference frame. It means that the interference from current commands in correcting current offset errors can be easily decoupled by the simple subtraction process, and the dynamic control capability of a current offset error compensator could be significantly improved. The dynamic performance of the proposed current offset error compensator is proved through simulations and experiments. [ABSTRACT FROM AUTHOR]

Distributed on-chip voltage regulation is promising for addressing many IC power delivery challenges. However, complex interactions between active regulators and the surrounding parasitic passive RLC network cause stability concern. The recently developed hybrid stability technique provides a unique opportunity for coping with stability of distributed on-chip regulation and enabling efficient localized system design. However, the inherent conservativeness of the hybrid stability theorem (HST) leads to large pessimism in stability evaluation and hence causes overdesign. In this paper, the above challenge is addressed by extending the HST with an optimal frequency-dependent system partitioning technique which can significantly reduce the amount of pessimism in stability analysis. To put the proposed approach on a firm theoretical footing, we prove that the partitioning technique removes the conservativeness without altering the physical system and key theoretical properties of the partitioned blocks are maintained under certain constraints. Upon this, an efficient stability-ensuring power delivery design methodology using an automated design flow is developed to significantly improve power delivery performance. Within a large design space, the proposed approach ensures stability and improves system performance by up to 53%, measured by a figure of merit (FOM), when compared to the classical phase margin design approach, which provides no guarantee of stability. Furthermore, on average our approach boosts the FOM by 113% while consuming 11% less power compared to a reference hybrid stability approach. [ABSTRACT FROM AUTHOR]

In this paper, a pW-power relaxation oscillator for sensor node applications is presented. The proposed oscillator operates over a wide supply voltage range from nominal down to deep sub-threshold and requires only a sub-pF capacitor for Hz-range output frequency. A true pW-power operation is enabled thanks to the adoption of an architecture leveraging transistor operation in super-cutoff, the elimination of voltage regulation, and current reference. Indeed, the oscillator can be powered directly from highly variable voltage sources (e.g., harvesters and batteries over their whole charge/discharge cycle). This is achieved thanks to the wide supply voltage range, the low voltage sensitivity of the output frequency and the current drawn from the supply. A test chip of the proposed oscillator in 180 nm exhibits a nominal frequency of approximately 4 Hz, a supply voltage range from 1.8 V down to 0.3 V with 10%/V supply sensitivity, 8–18-pA current absorption, and 4%/°C thermal drift from -20 °C to 40 °C at an area of $1600~\mu \mathrm {m}^{2}$. To the best of the authors’ knowledge, the proposed oscillator is the only one able to operate from sub-threshold to nominal voltage. [ABSTRACT FROM AUTHOR]

A class of novel tunable light-emission-diode (LED)-compatible current regulator, including the reverse blocking and the reverse conducting device, is proposed by integrating the p-GaN cap with a voltage nanosensor on the AlGaN/GaN platform. Verified by the experimentally calibrated simulation, it is the feedback of the voltage sensor that stabilizes the depletion region of the reverse biased p-GaN /AlGaN/2-DEG junction, which contributes to clamping the voltage effectively. Compared with the proposed regulator, the devices only with the p-GaN cap or the sensor cannot perform the current regulation. Moreover, investigated by varying the p-type concentration of the p-GaN, the length of the sensor as well as the temperature, the proposed device featuring a ripple wave below 4 mA/mm and a temperature coefficient of 4.5 mA $\cdot $ mm $^{-\textsf {1}}\text{K}^{-\textsf {1}}$ exhibits its potential in LED industry and other related applications. [ABSTRACT FROM AUTHOR]

This paper presents a new topology based on a modified class-E resonant inverter used as an LED series current regulator. The proposed topology behaves as a controllable nondissipative impedance that adjusts the current flowing through the lamp. In this circuit, the LED is placed at the dc side of the class-E inverter, in series with the input filter inductance. The power handled by the ac side is sent back to the input by means of two diodes. Despite the addition of these two diodes, the converter maintains all the advantages of the class-E inverter: low component count, simple control, and extremely low switching losses. The LED current can be controlled with a small variation of the operating frequency. This way, the low-frequency current ripple of the lamp can be strongly reduced even when there is a considerably high input voltage excursion, such as the one expected in electrolyticless high-power-factor LED ballast. This paper proposes a simplified methodology based on the fundamental approach aiming to design and build a laboratory prototype. The prototype is designed in order to minimize the effect of LED voltage in the output current. This way, the input voltage ripple can be canceled using a simple feedforward control. [ABSTRACT FROM AUTHOR]

The distorted back electromotive force (EMF) waveforms of dc-biased vernier reluctance machines result in stator current distortion, torque ripple, and efficiency reduction. For the purpose of eliminating the harmonic currents and optimizing the phase current, a new optimal current control strategy is proposed by utilization of accurate fundamental and harmonic voltage equations. Each harmonic component is decoupled in the multilevel synchronous rotating coordinate. The interactions between the multiple harmonic currents are avoided, and it assures a strong robustness. The harmonic currents can be suppressed significantly both in steady-state and dynamic operation, and it has a positive effect on the efficiency and torque ripple. Furthermore, a modified maximum torque per ampere curve considering inductance nonlinearity is achieved by adjusting the dc–ac current ratio under different phase currents, aiming to maximize the output capacity. Finally, the effectiveness of the proposed optimal current control strategy is validated experimentally for a prototype machine. [ABSTRACT FROM AUTHOR]

Inductive power transfer systems deployed in material handling have traditionally used parallel-tuned (current-sourced) boost regulators to independently control and regulate the load on each secondary. This paper evaluates the current doubler as an alternative parallel-tuned secondary controller within this application to better match the current and voltage requirements in the secondary resonant tuning network in high-power applications. This enables designs that enable the secondary magnetic pickup to achieve a smaller profile and fit within typical space constraints of material-handling vehicles. This paper presents the design approach needed for this regulator and compares its operation and performance against a traditional boost controller using both the simulation and the measurement of two built 5-kW secondary regulators. The current doubler naturally achieves a lower output ripple due to its interleaved switching and is found to have a comparable efficiency to the boost controller but requires slightly more components. [ABSTRACT FROM AUTHOR]

Recent works have shown that the state-feedback decoupling of capacitor voltage allows for drastic bandwidth enlarging of current controllers for grid-forming converters in islanded microgrids. Furthermore, Smith predictor and lead compensation have been also proved as very effective implementations for compensating the controller delays. These features are key to fulfill demanding requirements in terms of voltage regulation in islanded applications. This work deepens in the discrete-time domain modeling and implementation issues of the above-mentioned techniques. A full discrete-time and sensitivity analyses reveal phenomena not properly modeled in previous works, which limits the performance: the presence of high-frequency oscillations due to discrete poles with negative real part. Subsequently, proper design countermeasures (i.e., limit bandwidth) are proposed. Discrete implementation of the voltage controller is also addressed, and design guidelines are provided. Experimental tests in accordance with the high demanding standards for uninterruptible power supply systems verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents a new concept and approach for topology control and switching in distribution systems by extending the traditional circuit switching to laterals and single-phase loads. Voltage unbalance and other key performance indicators including voltage magnitudes, line loading, and energy losses are used to characterize and demonstrate the technical value of optimizing system topology on a per-phase basis in response to feeder conditions. The near-optimal per-phase topology control is defined as a series of hierarchical optimization problems. The proposed approach is applied to IEEE 13-bus and 123-bus test systems for demonstration, which included the impact of integrating electric vehicles (EVs) in the test circuit. It is concluded that the proposed approach can be effectively leveraged to improve voltage profiles with electric vehicles, the extent of which depends on the performance of the base case without EVs. [ABSTRACT FROM AUTHOR]

In this brief, we propose a supply noise-insensitive charge-pump phase-locked loop (PLL) using a source-follower (SF) regulator and noise cancellation. In order to minimize the voltage drop of the SF regulator while improving supply rejection, a gate-voltage-boosting technique and the body-controlled noise cancellation are proposed. To suppress the phase noise from the ring oscillator, a reference multiplier is employed to maximize the PLL loop bandwidth. Implemented in 65-nm CMOS, a prototype PLL at 3.2 GHz achieves supply noise spur of less than −33 dBc for a 50- $\text{m}V_{\mathrm{ pp}}$ supply noise around the loop bandwidth while consuming 3.12 mW from a 1-V supply. [ABSTRACT FROM AUTHOR]

This paper presents a single-phase ac–dc–ac converter with high-frequency isolation, which employs the interleaved technique. The proposed converter is suitable for power quality applications, such as dynamic voltage restorers, uninterruptable power supplies, and voltage regulators. The modeling of power flow is presented, focusing on the minimization of the transformer current. This analysis is improved by the introduction of the actuators type concept, which ensures reduced current through the transformer. Moreover, the effective longitudinal inductance of the series association of the boost inductor and two interphase transformers is determined. The soft-switching regions are also obtained as well as their dependency on the phase-shift angle. The proposed converter is compared with one indirect ac–dc–ac topology, which uses the dual active bridge converter as the isolation stage. Experimental results are obtained to show that the proposed converter is able to provide power factor correction, mitigate voltage sags, and regulate the output voltage. [ABSTRACT FROM AUTHOR]

An LED driver consisting of dimmable current balancing circuits (CBCs) and a boost converter with drain voltage balance (DVB) and phase-shifted pulsewidth modulation (PSPWM) control schemes is presented. To reduce the power loss on conventional linear current regulators, CBCs are employed. The DVB control scheme is proposed to maintain a desired constant voltage across the CBCs, so as to increase current balance and achieve high efficiency of the CBCs. Thus, the bus voltage of the boost converter is adaptively regulated based on the DVB control. The PSPWM control scheme can alleviate the variation of the bus current provided by the boost converter. As a result, the transient ripple of the bus voltage can be reduced when the light-emitting diode (LED) strings are turned on and off. Furthermore, the utilization of DVB control is increased when the PWM dimming duty cycle becomes lower. The experimental results demonstrate that the minimum voltage among the CBCs is always kept at the lowest constant level while maintaining the required current passing through the LED strings. The efficiency of the CBCs is kept almost the same for different LED currents and is over 95%. Thus, a high-efficient parallel-string dimmable LED driver with simple circuitry can be achieved. [ABSTRACT FROM PUBLISHER]

One of the most critical attributes of low dropout regulators (LDOs) in increasingly complex systems on chip (SoCs) is high-power supply rejection ratio (PSRR), not only over a wide frequency range but also over a large load current range. This paper presents an LDO, realized in 65-nm CMOS, featuring >60-dB PSRR over a 10-MHz frequency range and a 100-mA large load current range. The high PSRR is achieved by an adaptive feed forward ripple cancellation (FFRC) technique embodying an adaptive load current tracking scheme. By means of embodying an NMOS-based power stage, the LDO also achieves very low dropout voltage of 80 mV and features very small overshoot and undershoot of 2 and 4 mV, respectively. [ABSTRACT FROM AUTHOR]

Supply regulation using low quiescent current linear regulators helps in extending the battery life of power aware applications with very long standby time. A 1.24 $\mu \text{A}$ quiescent current NMOS low dropout (LDO) that uses a hybrid bias current generator (HBCG) which boosts the bias current dynamically and adaptively to improve the transient response is presented in this paper. A bias-current scalable error amplifier with an on-demand pull-up/pull-down buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. A novel switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA with a low-ESR 1 $\mu \text{F}$ output capacitor. Designed in a 0.25 $\mu \text{m}$ CMOS process, the LDO has an output voltage range of 1–3 V, a dropout voltage of 240 mV, and a core area of 0.11 mm2. [ABSTRACT FROM AUTHOR]

Tap changers are commonly used to maintain the limits in medium-voltage lines. Initially based on electromechanical switches, efforts have been made since the 1990's to reduce maintenance expenses with thyristor-based versions. Among the methods to limit the short-circuiting current in commutating taps, the multiwinding coil has demonstrated, during decades of use in the low-voltage field, to be reliable and cheap. Two previous papers showed that multiwinding changers can be applied to medium-voltage lines up to 34.5 kV, 15 MVA with no parallel or series thyristor association. This paper proposes a new topology, based on a double array of tap switches per phase, allowing for step-up the power from 15 to 36 MVA and insertion in any point of the line with no connection to the head transformer. A comparative cost analysis gives technical and economical results for a typical 10 MVA, 34.5 kV stabilizer demonstrating the advantages of the proposed circuit over the electronic single array topology and the classic mechanical solutions. [ABSTRACT FROM PUBLISHER]

With the rapid development of photovoltaic (PV) technology, more utility-scale PV systems are being integrated into rural areas where abundant and low-cost land is available. In these areas, step-voltage regulators (SVRs) with an open-delta configuration are widely used for voltage regulation. However, since SVRs were initially designed for tackling slow and smooth load variations, frequent PV output fluctuations can cause excessive tap changes. Moreover, rural communication facilities are normally expensive and underdeveloped, so only limited parameters are recorded with low resolution and reliability. Thus, much needed tap information cannot be properly monitored in a cost-effective way. In contrast, a downstream load center or utility-scale PV site is commonly well equipped with modern sensors and data acquisition systems, which provide the possibility for tap evaluation. Therefore, this paper proposes a new remote tap position estimation approach to accurately assess the upstream tap positions of open-delta SVRs from downstream measurements. Furthermore, the proposed approach is firmly validated through field testing under the support of the local utility and PV plant owner. This novel method not only enables reliable tap position monitoring with high precision for utilities to research PV–SVR interaction, but also provides valuable information to PV owners for correctly analyzing downstream voltage performance. [ABSTRACT FROM AUTHOR]

The field-weakening scheme is generally adopted for traction motors to achieve a wider speed range where the common proportional and integration compensator is needed to regulate the flux-producing current. However, the regulator performance deteriorates due to dc-link voltage disturbances and motor parameter nonlinearities in the different speed regions. To solve this issue, a model predictive control (MPC) based field-weakening algorithm is proposed for a traction electric vehicle using a low-voltage induction motor. The augmented prediction state relationship between stator voltage and flux-producing current is established for motor current control. The steady-state error can be eliminated with an integrator embedded within the augmented equation. The overall closed-loop control is presented where the system eigenvalues are adjusted in real time for various speed regions, and accordingly, the controller performance can be evaluated with the amplitude of the eigenvalues. Moreover, the weight coefficient in the cost function can be adjusted corresponding to speed variation for guaranteed motor control performance. The simulation and experimental results are provided to verify the proposed MPC-based field-weakening algorithm. [ABSTRACT FROM PUBLISHER]

Low-voltage (LV) feeder voltage magnitude and unbalance are often the constraining factors on a feeder's capacity to absorb rooftop photovoltaic (PV) generation. This paper presents a new probabilistic method for voltage management in distribution networks through the placement of distribution static compensators (dSTATCOMs) and on-load tap changers (OLTCs) considering the reactive capability of PV inverters in multiple LV and medium-voltage distribution networks. The method uses a modified particle swarm optimization. In this paper, several scenarios for the placements of multiple dSTATCOMs with and without embedded energy storage systems using both reactive and real power compensation are investigated in combination with an OLTC equipped with independent per-phase tap-changing control. The voltage constraints in the proposed method are statistically defined using three duration curves. These are the voltage unbalance, maximum voltage, and minimum voltage duration curves. The method is comprehensively tested for varying load and PV generation based on data from a real Australian distribution network with considerable unbalance and distributed PV generation. The results show that PV hosting capacity increases where the proposed approach is applied. [ABSTRACT FROM PUBLISHER]

In this paper, a fully integrated digitally assisted low-dropout regulator (LDO) for a NAND flash memory system is proposed and verified using 500 nm I/O CMOS transistors. By combining an amplifier (AMP)-based LDO with a comparator (CMP)-based LDO, the proposed LDO achieves both fast load response in the transient state and accurate regulation in the steady state, which are advantages of the CMP-based LDO and AMP-based LDO, respectively. Moreover, loop frequency stability is satisfied in a wide range of load currents between 0 and 150 mA by using the simple structure of the gm-boost cell to insert an auxiliary path. For an input voltage range of 2.3–3 V and an output voltage of 2.1 V, the measured output droop is 225 mV for a 150 mA load step in the load transition time of 20 ns with the total bias current of 81\,\mu \rmA. The fabricated prototype chip occupies 160\,\times \,610\,\mu \rmm^2 with an on-chip output capacitor of 2 nF. [ABSTRACT FROM AUTHOR]

A performance-aware 3-D power delivery network (PDN) using a novel common-centroid regulator placement and computational intelligence is presented. An evolutionary algorithm has been employed to evaluate the optimal performance tradeoffs such as power, latency, and signal integrity and to find the best performance placement of regulators in intertier PDN. To analyze main benefits of the proposed on-chip 3-D PDN, the regulator, most important block, is presented in the PDN. Through-silicon via and I/O links are also integrated into the 3-D PDN to analyze the power noise accurately. The proposed 3-D PDN using evolutionary process can significantly improve the energy efficiency, supply noises, and power/signal quality of a heterogeneous 3-D PDN. It is designed and fabricated in a 65-nm CMOS technology at 1 V. The measurement results show that the supply voltage fluctuation is 10.2 mV and the total power consumption of the proposed 3-D PDN is 4.22 mW while the 3-D I/O transceiver operates with a data rate of 1.9 Gb/s. [ABSTRACT FROM PUBLISHER]

A low-power ac–dc light-emitting diode (LED) driver with adaptive driving bus voltage (ADBV) and energy recycling (ER) control schemes is proposed to drive red, green, and blue LEDs in series to achieve high efficiency. The bus voltage of the power factor correction flyback converter with the ADBV control is always adjusted, so as to reduce power loss on current regulators. However, since the small bandwidth of the flyback converter and large bus capacitor limit the transient response of the flyback converter, it is difficult to maintain the voltage across current regulators at the minimum value. The ER control is proposed to accelerate the transient response of the bus voltage, making the voltage across current regulators as close to the minimum voltage as possible. Furthermore, extra energy is stored and restored on the recycling capacitor when the bus voltage is switched between different supplying levels without consuming much power due to the ER control. The experimental waveforms of the laboratory prototype are shown to confirm the validity of the proposed schemes. [ABSTRACT FROM PUBLISHER]

This part of the paper illustrates the use of the expression derived in Part I for predicting subharmonic oscillation in switching regulators. Six case studies with different control schemes from the recent literature are used to validate the novel approach and the new derived expression, which is benchmarked for these case studies against results obtained using the discrete-time modeling approach or Floquet theory combined with Filippov method. Numerical simulations from the circuit-level switched models, implemented in PSIM software, are used to demonstrate the correctness of the derived closed-form condition. A procedure is presented to apply the approach of the paper to power converters with nonlinear sources, such as photovoltaic (PV) arrays or fuel cells. Experimental measurements from a boost converter prototype for PV applications are also provided to validate the theoretical predictions and the numerical simulations showing a remarkable agreement. [ABSTRACT FROM AUTHOR]

This paper proposes an output current-differential (OCD) control scheme that has a master–slave structure. It can be applied in dc/dc converters to connect the input in series and the output in parallel. All of the control and sample circuits in the proposed control scheme are on the output side, which means that there is no further isolation in the control loops. The proposed control scheme, consisting of one output voltage regulator loop and individual load-current-sharing loops, will enable low-voltage converters to be used for high-voltage specifications. The master module regulates the output voltage through a common output voltage loop and provides current references to slave modules. The individual current-sharing loops residing in the slave modules regulate the current in each module equally. According to the power balance, input-voltage sharing is realized simultaneously. To prevent a situation in which system failure is caused by master module failure, a fault-tolerant automatic master–slave output current-differential (FOCD) control scheme is developed. The performance of the OCD and FOCD control schemes is validated on a 450-W prototype input-series–output-parallel system comprising three forward converters. [ABSTRACT FROM AUTHOR]

This part of the paper takes a new look at the stability of the fundamental periodic behavior and the associated subharmonic oscillation boundary in dc–dc switching regulators with fixed-frequency pulse width modulation. After revisiting different approaches applied to a unified reduced-order model of switching regulators, the work presents a novel way of obtaining such a boundary without any simplification nor order reduction. A new simple closed-form condition is then obtained using the new approach, which is valid for different strategies with both trailing edge and leading edge modulation schemes. The critical condition is obtained from the steady-state response using an asymptotic approach without resorting to frequency-domain Fourier analysis or using the monodromy or the Jacobian matrix of the discrete-time model. Unlike the method based on the Fourier series expansion, the proposed method does not require the use of any transform and, most importantly, can be applied to bilinear switching regulators. As a byproduct of the proposed method, a singularity problem that is encountered in steady state, when the system involves integrators in the feedback loop, is addressed and a solution is developed to achieve a closed-form expression in the presence of such integrating feedback loops. [ABSTRACT FROM AUTHOR]

The two-stage 48 V-12 V-1.8 V voltage regulator module (VRM) structure is gaining more and more attention in high-end server applications. The LLC converter is the preferred choice for the first conversion stage because it provides the isolated 12-V output efficiently, which is then converted to 1.8 V by the multiphase Buck converter. Since the CPU works in sleep-mode most of the time, the light-load efficiency is very important for energy saving. This paper proposes to change the primary side of the LLC converter from the full-bridge (FB) configuration into the half-bridge (HB) configuration dynamically in the light-load condition, so that the output of the LLC dc transformer (DCX) can be changed from 12 to 6 V. This will increase the overall light-load efficiency significantly due to the reduced core loss of the LLC DCX and the reduced switching loss of the multiphase Buck converter. To achieve a fast transition of the bus voltage between 12 and 6 V, the capacitance for the intermediate bus is properly selected and the optimal trajectory control for transition between the FB configuration and HB configuration is proposed. A high-efficiency high-density 48–12 /6 V LLC DCX is designed, and experiments on the two-stage VRM demonstrate that there is a fast transient response and a more than 10% light-load efficiency improvement. [ABSTRACT FROM AUTHOR]

This paper presents a digitally controlled 2-/3-phase 6-ratio switched-capacitor (SC) dc-dc converter with low output voltage ripple and high efficiency. To achieve wide input and output voltage ranges, six voltage conversion ratios are generated with only two discrete flying capacitors by using both 2- and 3-phase operations. An adaptive ripple reduction scheme is proposed to achieve up to four times reduction in the output voltage ripple. The complexity of controller design is reduced by using digital synthesis, and the technique is scalable with process. Fast loop response is achieved by using synchronized hysteretic control. The SC converter was fabricated in a 0.13- \mu \textm CMOS process. It can deliver a maximum power of 250 mW to an output of 0.5–3 V with a wide input voltage range of 1.6–3.3 V. Compared to an SC converter with only 2-phase operation, the maximum efficiency improvement is 20%. The converter achieves a peak efficiency of 91%. [ABSTRACT FROM AUTHOR]

A dual-mode controlled dc–dc controller with power over Ethernet (PoE) interface for power device (PD) is presented that is designed to support drawing power either from an Ethernet cable or from an external auxiliary supply support (ASS). PoE interface supports all the functions that comply with the IEEE802.3af/at standard. Based on bandgap reference structure, a detection comparator is provided to detect input voltage without extra voltage reference. Using a low offset voltage amplifier, a low-loss current-limiting technique is proposed to achieve a high-precision current-limit point. Based on a high-speed comparator and two timing capacitors, an oscillator (OSC) is implemented for better accuracy, and provides the maximum duty cycle ( D\mathrm {max} ) and external frequency synchronization. The chip is fabricated in a 0.5- \mu \textm 65 V BCD process and occupies a die size (with pads) of $1.79 \times 2.76$ mm2. The experimental results are measured for an active clamp forward converter with a wide range of dc input voltages from 33 to 57 V, an output voltage of 12 V, and an output power of 30 W. The chip achieves peak power efficiency of 90% and 90.63% on DC and ASS, respectively. The load regulation at different input voltages can be measured to be within ±0.11%. Measurements further show that the peak-to-peak ripple voltage of the chip is 161 mV and the recovery time is less than 1.2 ms for the 2-A load step. [ABSTRACT FROM PUBLISHER]

A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to $V_{{\mathrm{DD}}}$ , while its 4-kB ROM and the 16-kB SRAM are powered from $V_{{\mathrm{DD}}}$ to 2 $V_{{\mathrm{DD}}}$ . Since the memory and logic will, in general, draw different supply currents, the midrail $V_{{\mathrm{DD}}}$ is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and $V_{{\mathrm{DD}}}$ . Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 $\times $ . Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV. [ABSTRACT FROM AUTHOR]

This paper presents a 16-core voltage-stacked system with adaptive frequency clocking (AFClk) and a fully integrated voltage regulator that demonstrates efficient on-chip power delivery for multicore systems. Voltage stacking alleviates power delivery inefficiencies due to off-chip parasitics but adds complexity to combat internal voltage noise. To address the corresponding issue of internal voltage noise, the system utilizes an AFClk scheme with an efficient switched-capacitor dc–dc converter to mitigate noise on the stack layers and to improve system performance and efficiency. Experimental results demonstrate robust voltage noise mitigation as well as the potential of voltage stacking as a highly efficient power delivery scheme. This paper also illustrates that augmenting the hardware techniques with intelligent workload allocation that exploits the inherent properties of voltage stacking can preemptively reduce the interlayer activity mismatch and improve system efficiency. [ABSTRACT FROM PUBLISHER]

The design of power delivery system plays a crucial role in guaranteeing the proper functionality of many-core processor systems. The power loss suffered on power delivery has become a salient part of total power consumption, and the energy efficiency of a highly dynamic system has been significantly challenged. Being able to achieve a fast response time and multiple voltage domain control, on-chip voltage regulators (VRs) have become popular choices to enable fine-grain power management, which also enlarge the design space of power delivery systems. This paper analytically studies different power delivery system paradigms and power management schemes in terms of energy efficiency, area overhead, and power pin occupation. The analysis shows that compared to the conventional paradigm with off-chip VRs, hybrid paradigms with both on-chip and off-chip VRs are able to maintain high efficiency in a larger range of workloads, though they suffer from low efficiency at light workload. Employed with the quantized power management scheme, the hybrid paradigm can improve the system energy efficiency at light workload by a maximum of 136% compared to the traditional load balanced scheme. Besides this, the in-package (iP) hybrid paradigm further shows its advantage in reducing the physical overheads. The results reveal that at 120 W workload, it occupies only a 10.94% total footprint area or 39.07% power pins of that of the off-chip paradigm. We conclude that the iP hybrid paradigm achieves the best tradeoffs between efficiency, physical overhead, and realization of fine-grain power management. [ABSTRACT FROM AUTHOR]

This paper presents a model that incorporates the impact of islanding dynamics in reliability evaluation of active distribution networks. In order to do that, the effects of the islanding process in terms of voltage and frequency variations, as well as the impact of component failures, are taken into consideration in the reliability assessment. The proposed model is based on a combination of probabilistic reliability evaluation with the dynamic simulation of the islanding process. The reliability evaluation is performed by Non-Sequential Monte Carlo simulation, while the islanding process is evaluated by a transient stability simulation with complete models of synchronous machine and its voltage and speed regulators. Results are obtained for a MV distribution test system, where the influence of dynamics in the survivability rate of islanding is incorporated into the calculation of traditional reliability indices, leading to more realistic results. [ABSTRACT FROM AUTHOR]

This paper highlights the importance of chronology on voltage protection and control apparatuses in studies of voltage security in active distribution networks with high generation capacity. This paper presents simulation results of a real-life example of a long rural distribution feeder having three voltage regulators in cascade, and a customer whose demand accounts for a large percentage of the total feeder load. The customer is also an independent power producer and its location at the far end of the feeder yields an intricate voltage protection coordination when the customer ramps up and down its own generation at the peak-demand period. [ABSTRACT FROM AUTHOR]

An envelope modulator (EM) is presented to increase the efficiency of an RF power amplifier. In order to supply an output voltage higher than the input voltage while providing low-frequency power in the EM, a single-inductor dual-output (SIDO) converter is introduced. By employing the SIDO converter, the EM does not require an additional boost converter. In addition, a high-frequency converter (HFC) with a wide-bandwidth capability is also proposed. These two converters, the SIDO converter and the HFC, are combined in parallel without an ac coupling capacitor by employing a low-frequency current-balancing technique. The chip is implemented in a 0.18-μm CMOS process and achieves 86.5% peak efficiency while tracking a 10-MHz long-term evolution envelope signal. [ABSTRACT FROM AUTHOR]

Over the past few years, both the integration of small-scale embedded generators and the electric power consumption have been increased rapidly in the low-voltage (LV) distribution networks. These two trends are likely to result in a number of power quality issues such as voltage rise/drop and voltage unbalance. Regarding the mitigation of the voltage rise/drop effects, several utilities have already implemented the application of on-load tap changer (OLTC) in secondary distribution transformers. However, the voltage control via OLTC transformers might be infeasible in the case of radial feeders with both large number of branches and long distribution lines. This paper evaluates the performance of active in-line voltage regulators (IVRs) in LV grids. The study also investigates the optimal placement and sizing of active IVRs in Flemish LV networks. Concerning the OLTC control of the IVRs, an algorithm from a previous work is used. Finally, the influence on various power quality metrics is tested, when IVRs are incorporated into the system. [ABSTRACT FROM AUTHOR]

Power flow analysis is one of the tools that is required in most of the distribution system studies. An important characteristic of distribution systems is the load unbalance in the phases and a three-phase power flow analysis is needed. In this paper, a three-phase linear power flow (3LPF) formulation is derived based on the fact that in a typical distribution system, voltage angles and magnitudes vary within relatively narrow boundaries. The accuracy of the proposed 3LPF is verified using several test cases. Potential applications of the proposed method are in distribution systems state estimation and volt-VAR optimization. [ABSTRACT FROM PUBLISHER]

This work presents a fully integrated 4-to-1 DC-DC symmetric ladder switched-capacitor converter (SLSCC) for voltage stacking applications. The SLSCC absorbs inter-layer load power mismatch to provide minimum voltage guarantees for the internal rails of a multicore system that implements four-way voltage stacking. A new hybrid feedback control scheme reduces the voltage ripple across stacked voltage layers for high levels of current mismatch, a condition that exacerbates voltage noise in conventional SC converters. Furthermore, the proposed SLSCC dynamically allocates valuable flying capacitor resources according to different load conditions, which improves conversion efficiency and supports more power mismatch between the layers. Implemented in TSMC’s 40G process, the SLSCC converts a 3.6 V input voltage down to four stacked output voltage layers, each nominally at 900 mV. [ABSTRACT FROM AUTHOR]