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This article presents a hysteretic-current-controlled buck converter with constant-frequency-controlled and active-current-sensing (ACS) techniques. This converter used phase–frequency-locked techniques to achieve constant switching frequency. Even if the input voltage or output load current changes, the switching frequency will be as stable as possible at 1 MHz. The proposed ACS circuit will not generate sparks, so the current feedback loop does not need a sample-and-hold circuit, and that will reduce the transient response time. The proposed buck converter has been fabricated with TSMC 0.35 μ m CMOS 2P4M technology; the total area of the chip is 1.5 mm × 1.5 mm. The measurement results of this buck converter show that the maximum power efficiency is 90% when the output voltage is 2.5 V and the load current is 300 mA. The output voltage range is 2.5–1 V, and the maximum load current is 600 mA. When the load current varies between 100 and 500 mA, the load transient response is 2.6 μ s/2.2 μ s and undershoot/overshoot is 20 mV/30 mV. The switching frequency of this buck converter is locked at 1 MHz and the voltage error is within 1%. more...

This paper proposes a new and improved fast-transient-response low-transient-voltage boost converter with pseudo-current hysteresis-controlled techniques (PCHC). The converter uses the rail-to-rail current-sensing circuit to provide a hysteresis-controlled signal, helping to speed up the transient response and improve the overall efficiency. The proposed boost converter has been fabricated with TSMC $0.18~\mu \text{m}$ CMOS 1P6M technology, and the chip area is $1.18\times 1.18$ mm2 (include PADs). The measured results show that the input voltage range is from 0.5 V to 1 V, the output voltage is set as 1.8 V, and the output load current range is from 10 mA to 100 mA. When the output load current changes from 10 mA to 100mA and 100 mA to 10 mA, the transient responses are both 2 $\mu \text{s}$ , and peak power efficiency is 88.5% at the output load current of 75 mA. more...

This paper presents a dead-beat-controlled (DBC) fast-transient-response buck converter with active pseudo-current-sensing techniques. The dynamic-slope control can compensate for the ramp slope to reduce subharmonic oscillation issue of the current-mode converter when the duty cycle is greater than 50%. The proposed active pseudo-current sensor can shorten the time of transient response, because it does not need a sample-and-hold circuit to eliminate spikes, and it can obtain inductor current information precisely. Thus, the DBC circuit including the dynamic slope generator and the proposed active pseudo-current sensor can compensate for the inductor current slope to stabilize the converter in one duty cycle when the output voltage is changed and can accelerate the transient response to achieve a better performance. The proposed converter has been implemented with TSMC 0.35- $\mu \text{m}$ CMOS 2P4M technology, and the chip area is 1.5 mm $\times \,\, 1.5$ mm (including PADs). The operating frequency is 1 MHz, the maximum output current is 600 mA, and the peak power efficiency is 89% under 200-mA load current. The output voltage range is from 0.8 to 2.5 V, and the fast transient responses are $2~\mu \text{s}$ from light load to heavy load and from heavy load to light load. This buck converter also has the characteristic of low output ripple. more...

This paper presents a high-efficient low-noise buck converter with continuous-time delta-sigma-modulation and burst-mode techniques. The proposed buck converter uses the techniques of over-sampling, noise shaping, burst mode, and continuous-time second-order delta-sigma modulator to achieve low output noise, low overshoot and undershoot voltage, and improve the recovery time. First, the second-order DSM can lower the switching frequency noise, overshoot, and undershoot of the converter. Second, the noise shaping technique can move the noise to high frequency and filter out the noise within bandwidth. Third, the burst-mode technique can accelerate the transient response. The proposed chip is fabricated with a 0.35 μ m Taiwan Semiconductor Manufacturing Company (TSMC) CMOS process and the chip area is 1.5 × 1.5 mm. The transient recovery time is 6 and 16 μ s, when the load current changes from 600 to 50 mA and from 50 to 600 mA, respectively. The output noise spectrum is –67.5 dbm, when output voltage is 2 V. The maximum efficiency is 91.6%, when the output voltage is 2 V. The supply voltage is 3.3 V. The output voltage range of the proposed converter is 1–2.5 V. more...

A new fast-response current-mode buck converter with improved $I^{2}$ -controlled techniques is presented in this paper. First, the proposed converter uses the improved $I^{2}$ -controlled techniques to design a new current-mode buck converter. The current-sensing circuit can fully sense the inductor current. The sensing current is divided into two paths; one is flown through the dynamic-acceleration circuit, and the other is transferred to hysteretic comparator to compare with dynamic-acceleration output. The $I^{2}$ -controlled techniques increase the bandwidth of the converter’s closed-loop gain that will speed up the converter’s transient response. Second, the converter uses the phase–frequency-controlled techniques to lock the switching frequency of the adaptive on-time generator of the proposed converter and reduce the difficulty of the output filter. Third, the circuit does not need slope compensation, so that it is very simple to implement. Fourth, the proposed buck converter was implemented with TSMC 0.35- $\mu \text{m}$ CMOS 2P4M processes, which is a low-cost process. The experimental results show that the maximum load current can be up to 600 mA, the input voltage range is 2.6–4 V, the output voltage is regulated at 1.8 V, the maximum power efficiency is up to 90%, and the transient response times are 2.5 and $2.8~\mu \text{s}$ at rising and falling edges, respectively. more...

A new hysteresis-current-controlled buck converter with alternating current (AC) sensing techniques is presented in this Letter. The proposed AC sensing technique senses the inductor current ripple by sensing the voltage at two terminals of the inductor. Accompanying with hysteresis-current-controlled technique and a type-III compensator, the transient response can be accelerated. The simulation result shows the response time is 0.7 µs when the load current switch from 150 to 600 mA and the maximum efficiency is 94.6%. more...

A sub-1-μs ultrafast-response buck converter utilizing improved analog-voltage-dynamic-estimation (AVDE) techniques is proposed in this letter to improve previous works. First, the improved AVDE controller uses a new pseudocurrent circuit and a new ramp generator to get low gain, wide bandwidth, wide dynamic range, and low equivalent series resistor $(R_{{\text{ESR}}})$ . Second, the proposed converter has high performance, fast transient response, and low output voltage ripple. Third, the circuit does not need slope compensation so that it is very simple to implement. The switching frequency of the proposed buck converter is 1 MHz for nominal 3.3-V input and 0.8–2.5-V output range application. The experimental results prove that the proposed scheme improves the transient response within 1.2 μs and its maximum power efficiency can be up to 91.9%. The fastest transient time of the proposed converter is only 0.8 μs as the switching frequency is equal to 1 MHz. The settling time of the proposed converter is only within 0.8 cycle of the switching frequency. The maximum load current is 300 mA. The proposed buck converter has been fabricated with a commercial 0.35-μm CMOS 2P4M process, and the total chip area is about ${1.46 \;\text{mm}\times 1.5}$ mm, including PADs. more...

A new step-up (boost) converter with fast-response and efficiency-enhancement techniques suitable for cluster-based wireless sensor networks is presented in this paper. First, the modified nonoverlapping clock generator can produce four proper switching clocks to prevent four power transistors to be turned on simultaneously. Second, the size of the power transistor is adaptively changed by the width controller according to the different load current. Third, the zero-current detector is used to prevent the reverse inductor current at light load. Fourth, the converter efficiency can be raised by efficiency enhancement techniques. On top of that, this converter retains fast transient response at any load variation. The proposed boost converter has been implemented with a TSMC 0.35- $\mu \text{m}$ 2P4M CMOS 3.3/5 V process. The experimental results show that the proposed boost converter’s transient responses are $2~\mu \text {s}/4~\mu \text{s}$ for raising/falling time and the high efficiency is 93.8%. more...

This paper presents a 10- $\mu \text{s}$ transient recovery time and a low electromagnetic interference dc–dc buck converter with a second-order delta–sigma ( $\Delta $ – $\Sigma )$ modulator. The proposed buck converter employs the techniques of oversampling, noise shaping, fast-transient path, mode selector, and second-order $\Delta $ – $\Sigma $ modulator to achieve spur reduction and to improve transient recovery time. As a result, the noise tones of the output voltage are less than the other conventional pulsewidth modulation converters. In addition, the fast-transient path could correct output voltage immediately, and the mode selector controls the duty cycle of the converter to limit overshoot voltage and undershoot voltage. The chip was implemented using a 0.35- $\mu \text{m}$ Taiwan Semiconductor Manufacturing Company CMOS process. The measured results show that the transient recovery time is 10 $\mu \text{s}$ from heavy load to light load and from light load to heavy load, and the noise power spectrum demonstrates a −64-dBm peak noise when the output voltage is 2 V and the output current is 300 mA. A maximum efficiency of 89% is measured at 3 V output voltage and at 3.6 V supply voltage. more...

This paper presents a fast-transient boost converter with noise-reduction techniques for wireless sensor networks. The modulator can be directly inputted by 0.8–1.2 V for 1.8 V output. The proposed low electromagnetic interference (EMI) boost converter is based on a fast delta–sigma controller. This paper proposes a fast delta–sigma modulator for a boost converter to solve the EMI problem. The proposed converter complies with Federal Communication Commission class B conducted emission limits, in which the harmonic level must be lower than −48 dB $\mu \text{V}$ for frequency from 0.45 to 30 MHz. The measured results show that the maximum efficiency of the proposed converter is 90%, and the recovery time is 4 $\mu \text{s}$ from heavy to light load and 8 $\mu \text{s}$ from light to heavy load. The chip was fabricated in Taiwan Semiconductor Manufacturing Co., Ltd. 1P6M 0.18- $\mu \text{m}$ complementary metal–oxide–semiconductor process, and the chip area is $\sim 0.85$ mm2. It is designed to operate from 1 to 2 MHz with a 3.3- $\mu \text{H}$ inductor and a 10- $\mu \text{F}$ output capacitor. The proposed converter output spectrum is lower than −70 dBm or −40 dB $\mu \text{V}$ . more...

This paper presents a low electromagnetic interference buck converter for wireless sensor networks with the spur-reduction techniques. The proposed buck converter uses the third-order delta–sigma modulator (DSM) with its noise-shaping characteristic to achieve low output noise. The DSM is designed with the chopper-stabilization techniques, which further reduces the impacts of low-frequency noises, such as flicker noise and offset voltage. The proposed buck converter also adopts fast transient path in order to get a fast transient response. The proposed buck converter has been fabricated with a TSMC 0.35- $\mu \text{m}$ CMOS 2P4M process. The area of the whole chip is 2.18 mm2. Compared with previous works, the noise floor of the proposed converter’s output is below −76 dBm, which is lower than others. The settling time of the proposed converter’s output is $\sim 20~\mu \text{s}$ with the load current skipping between 50 and 500 mA, that is faster than previous works, too. Moreover, the peak efficiency of the proposed converter is better and equals to 90%. more...

This paper proposes a new common-mode feedback (CMFB) scheme for a fully differential operational transconductance amplifier (OTA) with enhanced linearity and large voltage swing. The main feature is that the common-mode feedback circuit output with push-pull scheme, which is parallel to the high-side PMOS and low-side NMOS of the output stage, to stabilize the common-mode state quickly and to maximize the output voltage swing. In addition, the third-order Butterworth low-pass transconductance–capacitance filter based on linear transformation techniques is also implemented in the TSMC 0.18 µm 1P6M CMOS process. The power dissipation of the designed transconductance cell is only 161 μW and the average power consumption of this chip is 1.4 mW under 1.2 V supply voltage. The filter core occupies a silicon area of 0.044 mm2. more...

The omnipotent Li–ion battery charger with multimode control and polarity reversible techniques is presented in this article. The proposed chip is fabricated with TSMC 0.35μm 2P4M complementary metal-oxide- semiconductor processes, and the chip area including pads is 1.5 × 1.5 mm2. The structure of the omnipotent charger combines three charging modes and polarity reversible techniques, which adapt to any Li–ion batteries. The three reversible Li–ion battery charging modes, including trickle-current charging, large-current charging and constant-voltage charging, can charge in matching polarities or opposite polarities. The proposed circuit has a maximum charging current of 300 mA and the input voltage of the proposed circuit is set to 4.5 V. The maximum efficiency of the proposed charger is about 91% and its average efficiency is 74.8%. The omnipotent charger can precisely provide the charging current to the battery. more...

A fast transient response flying-capacitor buck-boost converter is proposed to improve the efficiency of conventional switched-capacitor converters. The voltage boost ratio of the proposed converter is 2 D , where D is the duty cycle of the switching signal waveform. Furthermore, the proposed structure utilizes pseudocurrent dynamic acceleration techniques to achieve fast transient response when load changes between heavy load and light load. The switching frequency of the proposed converter is 1 MHz for 3.3-V input and 1.0–4.5-V output range application. Experiment results show that the proposed scheme improves the transient response to within 2 $\mu $ s and the total power conversion efficiency can be as high as 89.66%. The proposed converter has been realized by a 2P4M CMOS chip by 0.35- $\mu $ m fabrication process with total chip size of about 1.5 mm $\times $ 1.5 mm, PADs included. more...

The new efficiency-improvement low-ripple charge-pump boost converter using adaptive slope generator with hysteresis voltage comparison techniques is proposed in this paper. This proposed converter can reduce output voltage ripple, because its inductor is connected to the output. This proposed converter adopts a new controlled architecture, self-adaptive slope generator with hysteresis comparison technology, to shorten the transient response. The proposed boost converter has been fabricated with TSMC 0.35- $\mu $ m CMOS 2P4M processes, and a total chip area of $1.49~{\rm mm}\times 1.49$ mm. Its maximum output current is 260 mA when the output voltage is 3.6 V. When the supply voltage is 3.3 V, the output voltage can be 3.6–5.1 V. The maximum efficiency is 90.99% and the minimum output ripple is 10.8 mV. Finally, the theoretical analysis is verified to be correct by the experimental results. more...

A low-voltage and low-control-loss RF-dc rectifier with high power conversion efficiency (PCE) at 13.56 MHz band is presented in this paper. This is achieved by utilizing novel reducing reverse loss (RRL) techniques to reduce the reverse leakage current loss. Higher output voltage can also be generated by the multistage stacking method with RRL technology. A boost-type front-end converter composed of an RF-dc rectifier with the RRL technique and a boost converter operating in a discontinuous-conduction mode are also proposed. The single-stage, three-stage pump-type RF-dc rectifier and the boost-type front-end rectifier have been implemented in TSMC 0.18 μm 1P6M technology. Experimental results show that the maximum PCE of the single-stage and three-stage pump-type RF-dc active rectifiers are 68.6% and 67.9% with input powers of 4.9 and 12.8 dB·m, respectively. The maximum PCE of the boost-type front-end converter is 41.3% with 1.2 dB·m input power. more...

A switched capacitor (SC)-based converter with an integrated switch is proposed to improve the efficiency of the traditional SC converter. The proposed converter has the properties of fast transient responses and nonpulsating output current, which can reduce both the output voltage ripple and current stress requirement of the output capacitor. The proposed converter has been implemented using the Taiwan Semiconductor Manufacturing Company Technology Corporation 0.35-μm 3.3/5 V 2P4M CMOS process. The switching frequency is 1 MHz with a 150-mA maximum load current for 3.3-V input and 1.0-4.5-V output range application. The experimental results prove that the power efficiency of the proposed scheme can be up to 90%. more...

A primary-side controlled method is commonly used in flyback LED driver to regulate output current by employing an auxiliary winding. However, owing to intrinsic propagation delay in real-world circuits, a primary-side controlled flyback converter experiences a worse line regulation. This paper proposes a smart output current estimation scheme to improve line regulation for constant on-time control, and it can be compatible with the current flyback topology. A 9.5-W prototype of the proposed flyback LED driver has been fabricated in Nuvoton Technology Corporation 0.6-μm 5-V/40-V CMOS process. The maximum switching frequency is set to around 100 kHz with universal-line input, single-stage power factor correction for LED lighting applications. Experimental results prove that the proposed scheme can improve the line regulation within 1.5% and the power efficiency can be up to 89.7%. more...

This paper presents a high-efficiency positive buck- boost converter with mode-select circuits and feed-forward techniques. Four power transistors produce more conduction and more switching losses when the positive buck-boost converter operates in buck-boost mode. Utilizing the mode-select circuit, the proposed converter can decrease the loss of switches and let the positive buck-boost converter operate in buck, buck-boost, or boost mode. By adding feed-forward techniques, the proposed converter can improve transient response when the supply voltages are changed. The proposed converter has been fabricated with TSMC 0.35-μm CMOS 2P4M processes. The total chip area is 2.59 × 2.74 mm2 (with PADs), the output voltage is 3.3 V, and the regulated supply voltage range is from 2.5-5 V. Its switching frequency is 500 kHz and the maximum power efficiency is 91.6% as the load current equals 150 mA. more...

Two integrated stereo fully differential filterless class-D amplifiers are presented in this paper. The object is to develop a modulation of a class-D audio amplifier with high power efficiency in this paper. The traditional H-bridge class-D audio amplifier has a shortcoming of large signal distortion which is worse than realized. However, the proposed circuit improves the drawback and provides high power efficiency at the same time. The circuit implements a modified scheme of pulse-width modulation. In this paper, we presented two class-D amplifiers, compared their differences and explained why the efficiency and distortion performance can be modified. The increase in total harmonic distortion (THD) is due to non-linearity in the triangle wave. To overcome this problem, a negative feedback from the output of the switching power stage is adopted to reduce the THD. When a 0.7-VPP and 1 kHz sine wave is used as an input signal, the minimum THD is 0.029 % and the maximum power efficiency is 83 %. The fully differential class-D audio amplifier is implemented with a TSMC 0.35-μm 2P4M CMOS process, and the chip area is 2.57 × 2.57 mm2 (with PADs). more...

This paper proposes a new phase-locked-loop (PLL)-based inductive coupled contactless energy transfer (CET) analog frequency-shift keying (FSK) demodulator using a high-efficiency RF-to-dc rectifier for biomedical implanted devices. The analog FSK demodulator is composed of a modified CMOS three-stage rectifier, a voltage regulator, an FSK signal generator, and a PLL. The proposed modified single-stage rectifier with both positive and negative output voltages using a PMOS and an NMOS pass transistor, an inverter, and two capacitors has a small active area and can enhance the power conversion efficiency. The proposed RF-to-dc rectifier achieves an efficiency of 64% at 8.4 dBm. The power consumption of the demodulator is as low as 0.76 mW, and the active area is 0.084 mm2. The analog FSK demodulator supports a data rate of 100 kb/s to 1 Mb/s. The chip was implemented in a Taiwan Semiconductor Manufacturing Company (TSMC) 0.35- μm double-poly quadruple-metal CMOS technology to verify the proposed CET circuit. Two figures of merit are provided to illustrate the advantages of the proposed architecture. more...

The proposed high-efficient WLED driver using light-balanced-controlled techniques with current-locked loops is presented in this paper. This LED driver has 500:1 current sensing ratio and 1 kHz PWM dimming frequency. The maximum output current of the buck converter is 100 mA and the output voltage range is from 3.5 to 4.8 V with a 20 and 18 μH off-chip capacitor and inductor, respectively. The maximum efficiency of the proposed LED driver is 87.8 % and the current difference between each LED string is 1.33 %. And it is fabricated with TSMC 0.35 μm 2P4 M CMOS processes. The chip area is 1.52 mm × 1.36 mm. more...

SUMMARY A new fast-response buck converter using accelerated pulse-width-modulation techniques is proposed in this article. The benefits of the accelerated pulse-width-modulation technique is fast-transient response, simple-compensation design, and no requirement for slope compensation; furthermore, some power management problems are minimized, such as EMI (Electro Magnetic Interference), size, design complexity, and cost. The traditional voltage-mode speed is slower with the transient response, so an accelerated pulse-width-modulation technique is used to solve the problem of slowed transient response in this article. The proposed buck converter has excellent conversion efficiency with a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 µm CMOS 2P4M processes, and the total chip area is 1.32 × 1.22 mm2. Maximum output current is 300 mA when the output voltage equals 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 1–2.6 V. Maximum transient response is less than 5 µs. The simulation and experimental results are presented in this article. Copyright © 2011 John Wiley & Sons, Ltd. more...

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35@mm 2P4M CMOS technology. The chip area without pads is only 0.87mmx0.65mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8V power supply voltage (V"D"D=1.8V) can be pumped up to 8.2V. The proposed charge pump circuit achieves efficiency of 60% at 80@mA. more...

In this paper, a new CMOS wideband low noise amplifier (LNA) is proposed that is operated within a range of 470MHz-3GHz with current reuse, mirror bias and a source inductive degeneration technique. A two-stage topology is adopted to implement the LNA based on the TSMC 0.18-@mm RF CMOS process. Traditional wideband LNAs suffer from a fundamental trade-off in noise figure (NF), gain and source impedance matching. Therefore, we propose a new LNA which obtains good NF and gain flatness performance by integrating two kinds of wideband matching techniques and a two-stage topology. The new LNA can also achieve a tunable gain at different power consumption conditions. The measurement results at the maximum power consumption mode show that the gain is between 11.3 and 13.6dB, the NF is less than 2.5dB, and the third-order intercept point (IIP3) is about -3.5dBm. The LNA consumes maximum power at about 27mW with a 1.8V power supply. The core area is 0.55x0.95mm^2. more...

In this paper, we propose an inductorless CMOS wideband low noise amplifier (LNA), operated in the range from 100 to 900 MHz, with current reuse, mirror bias, gain control and input matching device using noise-cancellation technologies. The traditional wideband LNAs have different input reflection coefficient parameters (S11) at different gain control modes, and they always implement with inductors for wideband matching. Therefore, the proposed LNA which can save power consumption at low gain mode, and implement without inductor on its design. Moreover, its S11 parameter has smaller variation at different gain control modes. The wideband CMOS LNA for digital video broadcasting-handheld (DVB-H), terrestrial-digital multimedia broadcasting (T-DMB), and digital video broadcasting-cable (DVB-C) tuner application is designed using TSMC 0.18 - μ m RF CMOS process. The post-simulation results at high gain mode show that the gain is 13 – 15.8 dB , the noise figure (NF) is less than 2.75 dB. The LNA consumes power between 7.25 mW (low gain mode) and 17.8 mW (high gain mode) at 1.8 V power supply. The core area is 0.435 × 0.67 mm 2 . more...

In this paper, a differential multi-band CMOS low noise amplifier (LNA), operated in a wide range from 1350 to 2900 MHz , with input matching device, noise cancellation and interference rejection technology, is proposed. Traditional wideband LNAs have poor performances on interference rejection or image rejection. In this design, a multi-band CMOS LNA with matching device noise cancelling, matching device current reuse and source inductance device reuse technologies is proposed, it can improve noise figure, wideband match and interference rejection. There exists a switch-mode notch filter to enhance the interference rejection performance and it does not need additional inductors. A prototype of proposed multi-band CMOS LNA was designed to work at 1450 – 1490 MHz , 1680 – 1685 MHz and 2635 HMz – 2660 MHz . The simulation results show that the gain is between 18 and 19 dB at L-band application (1450–1685MHz) and between 25.8 and 26.1 dB at CMMB Satellite application ( 2635 HMz – 2660 MHz ) , the noise figure is 3.1–3.3 dB, and the third-order intercept point (IIP3) is − 7 dBm . It consumes 27.35 mW under 1.8 V supply voltage in TSMC 0.18- μ m RF CMOS process. more...

The demand for current-mode fast-transient-response shunt regulator is increasing for the growth of portable electronics, such as cellular phones, PDA, laptops, etc. A new current-mode fast-transient-response shunt regulator is presented in this paper. The proposed shunt regulator used a single Miller compensation capacitor to increase stability. The current-mode shunt regulator helps the transient response to be faster than the voltage-mode low-dropout regulator (LDO) and the power noise (bounce noise) is smaller than one. The proposed current-mode shunt regulator has been fabricated with TSMC 0.35 μm 2P4M CMOS technology. The experimental results show the transient-response time is only 400 ns within 0.5% error and the maximum output voltage dip is only 70 mV for full loading current variation. Moreover, the line and load regulations are 26 μV/mA and 8 ppm/mA, respectively. The dropout current is 1.0741 mA for loading current 150 mA. The active chip area is 226 μm × 310 μm. more...

A low-sensitivity, low-bounce, high-linearity current-controlled oscillator (CCO) suitable for a single-supply mixed-mode instrumentation system is designed and proposed in this paper. The designed CCO can be operated at low voltage (2 V). The power bounce and ground bounce generated by this CCO is less than 7 mVpp when the power-line parasitic inductance is increased to 100 nH to demonstrate the effect of power bounce and ground bounce. The power supply noise caused by the proposed CCO is less than 0.35% in reference to the 2 V supply voltage. The average conversion ratio KCCO is equal to 123.5 GHz/A. The linearity of conversion ratio is high and its tolerance is within plusmn1.2%. The sensitivity of the proposed CCO is nearly independent of the power supply voltage, which is less than a conventional current-starved oscillator. The performance of the proposed CCO has been compared with the current-starved oscillator. It is shown that the proposed CCO is suitable for single-supply mixed-mode instrumentation systems. more...

A new building block called the multiplication-mode current conveyor (MMCC) is proposed here. The structure consists of a differential voltage current conveyor (DVCC) and a folded Gilbert cell without any other auxiliary circuits. Based on the MMCC, a four-quadrant analogue multiplier is designed in TSMC 0.35 mum CMOS 2P4M processes with power supply plusmn 1.65 V. HSPICE post-layout simulation results show that the maximum DC operating range is plusmn 200 mV, the loading range is from 1 to 10 kOmega, the bandwidth is about 90 MHz, the total harmonic distortion (THD) is 0.85 , the power consumption is 1.08 mW and the chip area without pads is 0.48 times 0.36 mm 2 . The new square summer and analogue divider applications employing MMCCs are also presented. more...

An integrated class-D amplifier with active current sensing suitable for AC switches is presented in this paper. The proposed current-sensing technique is used to sense and control the inductor current at the output stage and allows the current-sensing element to be integrated into class-D amplifiers. To verify the performance of the proposed circuits, a class-D amplifier was designed and fabricated with 3.3-V 0.35- mum double-polyquadruple-metal CMOS technology on a chip area of 1.79 times 1.45 mm. The maximum power efficiency of the class-D amplifier can be up to 94% for an 8-Omega load. These active current-sensing circuits can be applied to other power converters with AC switches. more...

A new monolithic fast-response buck converter using spike-reduction current-sensing circuits is proposed in this paper. The proposed converters are designed and implemented with TSMC 0.35-mum DPQM CMOS processes. The operation frequency can be up to 1.887 MHz. The response time is only 2 mus and compared with other references. The maximum output current is 750 mA, and the maximum power efficiency can be up to 89.1% at 2.442-W output power. The chip area is only 2.157 mm2. more...

A monolithic CMOS voltage-mode, buck DC-DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC-DC converter is 1.2V. The proposed buck DC-DC converter with a chip area of 0.82mm^2 is fabricated with a standard 0.35-@mm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2V, with an input voltage of 1.5V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300mW. more...

This paper presents a new compact CMOS Li-Ion battery charger for portable applications that uses a charge-pump technique. The proposed charger features a small chip size and a simple circuit structure. Additionally, it provides basic functions with voltage/current detection, end-of-charge detection, and charging speed control. The charger operates in dual-mode and is supported in the trickle/large constant-current mode to constant-voltage mode with different charging rates. This charger is implemented using a TSMC 0.35-mum CMOS process with a 5-V power supply. The output voltage is almost 4.2 V, and the maximum charging current reaches 700 mA. It has 67.89% power efficiency, 837-mW chip power dissipation, and only 1.455times1.348 mm2 in chip area including pads more...

This paper presents the design and experimental results of a concurrent dual-band 2.4/5.2GHz low-noise amplifier. To achieve the concurrent gain and impedance matching at the both bands, input and output matching using two poles matching and LC resonant network are implementation, respectively. In low-noise amplifier using gain enhanced technique in order to improve gain since LC resonant matching network limit gain. The LNA is has been fabricated in a 0.18-um CMOS process and employs a supply voltage of 1 V. The measured power gain and noise figure for 2.4GHz (5.2GHz) is 12.9dB (8.9dB) and 3.7dB (3.7dB), respectively. The linearity parameters of IP1dB and IIP3 are −14dBm and −4dBm at 2.4GHz, and −11dBm and −1dBm at 5.2GHz, respectively. The power consumption is 7.6mW. more...

A wide-range high-linearity current-controlled pulse-width/ delay circuit suitable for current-mode controlled techniques is presented in this paper. The proposed circuit has been fabricated with 0.35µm CMOS 2P4M processes. The chip area is only 0.33mm × 0.12mm. The experimental results show the variation of the output frequency within ±0.2%, the tolerance of duty cycle is less than 0.2%. The current-controlled pulse-width/delay circuit is supply independent and can be operated at 2.5V. The linear range of input current is from 4µA to 277µA, and corresponding duty cycle of pulse-width output is from 1.59% to 97.2%. The experimental results agreed with the theoretical analysis are presented in this paper. more...

A high-efficiency fast-transient-response V 2-controlled boost converter with a small equivalent series resistance (ESR) capacitor is presented. The proposed boost converter can achieve a fast and stable load transient response without relying on the ESR of the output capacitor. The switching frequency of the proposed boost converter is 500 kHz for a nominal 2.5–4.2 V input and a 3.3–5 V output application. Experimental results show that the transient recovery time inheriting the advantage of V 2 control is shorter than 6.4 µs with the load step from 250 to 20 mA and the highest efficiency can be up to 95.4%. The proposed boost converter has been fabricated with a 0.35 µm 2P4M CMOS process, the total chip area is about 1.5 × 1.5 mm2, including the PADs. more...

The proposed driver circuit provides a new driver scheme for supply noise rejection and uniformity enhancement of AMOLED displays. We propose a new gamma circuit scheme for supply noise rejection improvement and provide a driver circuit with offset voltage zero-crossing detection (OZCD) technology to enhance the uniformity of larger displays. The simulation results show the supply noise rejection can improve more than 40dB, and the driver voltage output uniformity can be reduced to less than +/-1mV. more...

An ultra-low input flyback converter is proposed in this paper. Instead of the conventional flyback topology, the improved topology is able to reduce more power consumption to achieve high efficiency by replacing the output diode with a power transistor. This design can achieve wide conversion ratio and high conversion efficiency by utilizing transformer and digitally controlled zero-current switching techniques operates from input voltage 20 mV to 250 mV while supplying an output 1.8V, delivers maximum 18 mW of output power and 92.63% efficiency for a 250 mV input. The proposed circuit has been designed with TSMC 0.18μm CMOS 1P6M processes. The total chip area is 1.19 × 1.18mm2 with PADs. more...

The omnipotent Li-Ion battery charger with multimode controlled techniques is presented in this paper. The proposed chip can create a reversible three-stage linear Li-Ion battery charger and is designed with TSMC 0.35μm DPQM CMOS processes. The three-stage charger functions include trickle-current charging, large-current charging and constant-voltage charging. This technique can reduce the damage of Li-Ion battery. The design of structure, which creates an omnipotent charger, combines with the reversible three-stage charger; that is adapts to any Li-Ion batteries. The proposed circuit can adjust the maximum charge current of 350mA, the constant voltage is set to 4.2V. Input voltage of the proposed circuit is from 4.4V to 4.8V. The average efficiency of the proposed charger is about 79%. The omnipotent charger can precisely provide VOUT where range is from 2.2V to 4.2V. The chip area is 1.5×1.5mm2. more...

A low-voltage positive buck-boost converter using average-current-controlled techniques is proposed in this paper. The benefit of the average-current-controlled circuit is that it does not need to use slope compensation, furthermore, it can reduce some power management problems such as cost, design complexity, size, and EMI. The advantages of the low-voltage operational amplifier are that it has lower power dynamic consumption and also can operate at low supply voltage. The proposed low-voltage positive buck-boost converter using the active-current-sensing circuit and average-current-controlled circuit techniques can work stably without slope compensation even when the duty cycle is higher than 50%. The proposed design circuit has been fabricated with TSMC 0.35µm CMOS 2P4M processes, the total chip area is 2.46 × 2.47mm2. When the supply voltage is 1.5V, the output voltage range is between 0.8V∼3.3V. more...

Four new CMOS inverter-based voltage multipliers consisted of PMOS/NMOS pass transistors, inverter circuits, and capacitors are proposed in the paper. The proposed voltage multipliers which combine the functions of rectifiers and charge-pumps improve the power conversion efficiency and reduce the number of passive components therefore they are suitable for the integration. The voltage multiplier with positive output voltage is implemented with TSMC 0.35µm CMOS 2P4M processes, and the experimental results have showed good agreement with the theoretical analysis. The chip area without pads is only 1.75×1.32 mm2 for five-stage positive output voltage of voltage multiplier more...

The communication speed between components is far from satisfactory. To achieve high speed, simple control system configuration, and low cost, a new on-chip all-digital three-phase dc/ac power inverter using feedforward and frequency control techniques is proposed. The controller of the proposed power inverter, called the shift register, consists of six-stage D-latch flip-flops with a goal of achieving low-power consumption and area efficiency. Variable frequency is achieved by controlling the clocks of the shift register. One advantage regarding the data signal (D) and the common clock (CK) is that, regardless of the phase difference between the two, all of the D-latch flip-flops are capable of delaying data by one CK period. To ensure stability, the frequency of CK must be six times higher than that of D. The operation frequency of the proposed power inverter ranges from 10 Hz to 2 MHz, and the maximum output loading current is 0.8 A. The prototype of the proposed circuit has been fabricated with TSMC 0.35 μm 2P4M CMOS processes. The total chip area is 2.333 × 1.698 mm2. The three-phase dc/ac power inverter is applicable in uninterrupted power supplies, cold cathode fluorescent lamps, and motors, because of its ability to convert the dc supply voltage into the three-phase ac power sources. more...

A new single-inductor triple-output (SITO) buck converter using CMOS technology is presented in this paper. A new time multiplexing scheme is also proposed for control. This SITO DC-DC buck converter uses only one inductor to provide three independent output voltages. The output voltages of 2.5V, 1.65V, and 0.8V are designed from a 3.6V power supply. A maximum efficiency of 77.4% is achieved at a total output power of 460mW, with a switching frequency of 1MHz. The proposed SITO buck converter circuit has been fabricated with TSMC 0.35μm 2P4M CMOS technology, and the active chip area including I/O pad is 1.53mm × 1.79mm. more...

An unexpected POR (Power-on Reset) may lead to system unstable or hanging-up during the booting. This paper proposed a new reset IC structure to monitor system power during power ramp-up. For system design, this chip contains hysteresis input voltage, power delay control, output enable, power good signal, and LVRC (Low Voltage Reset Circuit). Finally, the proposed IC is designed with TSMC 0.35µm 2P4M process. The chip specifications are listed below: 3.3V +/− 10% as input power, 1.5∼5V as analog input signal, 15∼30mV as hysteresis input voltage, 2.7∼2.8V as startup voltage of LVRC, and 40mW as chip power consumption. It can be applied to most current mobile device. more...

A CMOS sub-1 V capacitor-free low-power-consumption low-dropout voltage regulator (LDO) with digital controlled loop is presented in this paper. This technique can make power consumption lower than other LDOs with traditional controlled Loop. Especially, the performance of power consumption of proposed LDO without off-chip capacitors is excellent. The LDO can also be stable even without the output capacitor. With 0.9 V power supply voltage, the output voltage is designed as 0.6 V. The maximum output current of the LDO is 120 mA at an output of 0.6 V. The prototype of the LDO is fabricated with TSMC 0.35-mum CMOS processes. The chip area (including I/O pad) is only 927 mum times 969 mum. more...

In this paper, we have proposed a new high precision ramp waveform generator for low cost ADC test. With proposed test method combined with histogram analysis, an ADC can be easily tested on general digital testers. In our approach, we combine a traditional ramp generator with proper gain of operational amplifier (OPA) for ADC test. This new ramp generator structure can reduce the effect of output resistance (Ro) and then get the smaller integral nonlinearity (INL) error. Eventually, we have designed a ramp generator chip using TSMC CMOS 0.35 ?m 2P4M technology. The core area without I/O pad is 144 ?m × 277 ?m, operation voltage is 3.3 V. Experimental results show that the chip has a ramp signal of 2 V full range with duration of 100 ?S and measured a maximum INL of 20 ?V only. The linearity of the ramp waveform equals to 16 bits resolution. Such linearity allows the test of ADC up to 14 bits. more...

A hysteresis-current-controlled (HCC) buck converter with active current-sensing and phase-frequencylocked techniques is presented in this paper. The proposed active current-sensing technique can not only consume less power than previous techniques, but also fully sense the inductor current. Although the buck converter is HCC, the switching frequency can be constant due to the devised phase-frequency-locked technique. The proposed converter has been designed and implemented with TSMC 0.35 microm DPQM CMOS processes. It is shown in the experimental results that the HCC buck converter features the following characteristics: 1) up to 800 mA of load current, 2) wide input and output voltage range, 3) high power efficiency, and 4) constant-frequency operation. more...

A new hysteresis-current-controlled (HCC) buck converter suitable for Li-ion battery charger is presented in this paper. The technique adopted in this charger is constant current/constant voltage dual mode, which is decided by the value of internal resistance of Li-ion battery. This technique will degrade the damage of Li-ion battery and improve the power efficiency of charger. The Li-ion battery charger is designed with 0.35 - mum CMOS DPQM processes. The simulation results show that the charger works well and confirms with theoretical analysis. The power efficiency of charger can be up to 82% under the average power of 825 mW. The chip area is only 1.71times 1.52 mm 2. more...