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In this paper, a low-cost and low-leakage gate-first high-k metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO 2 coupled with Al 2 O 3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 μA/μm can be obtained for an OFF-state current of 10 -10 A/μm, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.

Channel hot-carrier (CHC) reliability in p-FinFET devices is studied related to the postdeposition anneal (PDA) process. Clearly reduced CHC degradation is observed with N2-PDA at the VG = VD stress condition. The interface defect density degradation calculated from the subthreshold slope is similar in the reference and PDA devices. However, the pre-existing high- k bulk defect is lower in the PDA-treated device as observed by the low-frequency-noise measurement. This leads to less hot/cold-carrier injection into the bulk defects at the high field under the VG = VD condition, where a higher charge trapping component is expected than under the classical VG ~ VD/2 condition. The responsible bulk defect is pre-existing, not generated during the CHC stress as proven by the stress-induced leakage current analysis.

In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (E v ) lowers the E ox and reduces the NBTI degradation at fixed overdrive. We demonstrate that trap engineering can be exploited to meet aggressive reliability requirements. Furthermore, it is predicted that there are no reliability issues in the SiGe pMOSFETs comparing with the Si counterparts.

The time-dependent variability of nanoscaled Si0.45 Ge0.55 pFETs with varying thicknesses of the Si passivation layer is studied. Single charge/discharge events of gate oxide defects are detected by measuring negative bias-temperature instability (NBTI)-like threshold voltage (Vth) shift relaxation transients. The impact of such individually charged defect on device Vth is observed to be exponentially distributed. SiGe channel devices with a reduced thickness of their Si passivation layer show a reduced average number of active defects and a reduced average impact per charged defect on device Vth. Our model for the superior reliability of the SiGe channel technology previously proposed in Part I, which is based on the energy decoupling between channel holes and dielectric defects, is shown to also explain these experimental observations. Other reliability mechanisms, such as 1/f noise, body biasing during NBTI, channel hot carriers, and time-dependent dielectric breakdown, are also investigated. None of these mechanisms are observed to constitute a showstopper for the reliability of this promising novel technology.

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.

In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition HfO2 high-k and TiN metal electrode. For the 0.8-nm EOT FinFETs, it is found that TDDB lifetime is consistent with results of planar devices for areas around , implying that the FinFET architecture does not seem to introduce new failure mechanisms. However, for devices with smaller area, the extrapolated voltage at a ten-year lifetime for soft breakdown (SBD) does not meet the specifications, and as a consequence, the SBD path wear-out will have to be included in the final extrapolation. Furthermore, it is shown that for EOTs smaller than 0.8 nm, the TDDB reliability on n-type FinFETs is challenged by the high leakage currents.

In this work we examine the positive bias temperature instability (PBTI) and stress induced leakage current (SILC) reliability of nFET devices with thin (2.5 nm) ZrO2 gate dielectric layers. nFET devices show anomalous PBTI behavior in the form of a negative threshold voltage (Vt) shift during positive bias stress with little temperature dependence and it is not ‘frozen out’ at lower temperatures, indicating a single non-diffusion based mechanism. Correlations between the PBTI and the stress induced leakage current (SILC) suggest that the PBTI effect originates from trapping into empty defects which are initially detected as SILC and located just below the silicon conduction band. These defects also appear to be linked to the time dependent dielectric breakdown behavior.

In ultrascaled complimentary metal-oxide-semiconductor technologies, the lucky-electron model does not describe correctly Channel Hot-Carrier (CHC) degradation for typical transistor test conditions independently of the gate dielectric (SiO2 or high- k). A new model to describe the CHC degradation behavior in n-channel metal-oxide field-effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented. This new model can be applicable to long- and short-channel transistors with high- k or SiO2 as a dielectric.

The temperature dependence of channel hot-carrier (CHC) degradation in n-MOS transistors with high-k dielectrics has been studied. The analysis starts from the most damaging CHC stress conditions at room temperature (V G = V D/2 for long channels and V G = V D for short channels). We find that, for long-channel transistors, the CHC degradation decreases at high temperature, while for short-channel transistors, an increase is observed. In this paper, a new picture to explain the observed increment of CHC damage with temperature for short-channel transistors with high-k dielectric is presented. We demonstrate that the total CHC degradation consists of two components: the classical CHC damage located at the drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered a positive bias temperature instability (PBTI) effect. Particularly for short transistors stressed at high temperatures, this PBTI component dominates the total CHC degradation.

Channel hot-carrier (CHC) degradation in nMOS transistors is studied for different SiO2/HfSiON dielectric stacks and compared to SiO2. We show that, independent of the gate dielectric, in short-channel transistors, the substrate current peak (used as a measure for the highest degradation) is at VG = VD, whereas for longer channels, the maximum peak is near VG = VD/2. We demonstrate that this shift in the most damaging CHC condition is not caused by the presence of the high- k layer but by short-channel effects. Furthermore, the CHC lifetime of short-channel transistors was evaluated at the most damaging condition VG = VD, revealing sufficient reliability and even larger operating voltages for the high-k stacks than for the SiO2 reference.

This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (eWF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: (a) deposition of a Dy 2 O 3 capping layer on the host dielectric (SiON or HfSiON), or (b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: (1) both cases result in dielectric modification with gate leakage (J G ) reduction; (2) adding a cap has no significant impact on T inv (

In order to reduce the gate leakage current, high-k gate dielectrics are expected to replace SiO2 in future CMOS generations. Many of these novel dielectrics are stacks of a thin SiO2 and a high-k layer. We present a theoretical study that aims at identifying the combination of the stack architecture and high-k material with the lowest leakage current. In the first part of this work the leakage current through high-k double stacks with various thicknesses, materials and gate electrodes is calculated assuming tunneling only. We discuss the difference between gate and substrate injection and show quantitatively the impact of interfacial layer thickness, barrier height, k-value and the work function of the gate material on the tunneling current. In the second part the material properties are no longer considered to be independent and with the universal relation between k-value and barrier height introduced, we are able to identify what material suits best all requirements. The leakage current is calculated for different EOTs and we demonstrate that if all dielectrics follow this universal relation, for a fixed thickness there exists one material, which gives a minimum gate leakage current. It is concluded that even for sub 1 nm EOT devices the k-value has not to exceed ∼25 and ZrO2 or HfO2 come closest to the ideal high-k if only leakage current issues are considered.

Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45° rotated devices compared with the 0° rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45° rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv-exhibited when transitioning from planar to FinFET architecture at 45° rotation-plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45° rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho et al.

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.

We propose the bipolar-mode operation of resistive random access memory devices in a purely oxygen-vacancy (V0)-controlled regime, which is achieved by very low compliance capping for forming/set transitions. This regime enables us to achieve a very low reset current of 10-100 nA, in which the governing mechanism for switching only involves the reversible drift of oxygen ions to and from oxygen soluble gate electrodes. The physical analysis of a gate stack in this V0 regime confirms the absence of metallic nanofilaments. These findings pave the way for the realization of ultralow switching power RRAM devices.

We propose the use of high-oxygen-solubility metalgate electrodes as a material of choice for high- gate stacks in order to prolong the time-dependent-dielectric-breakdown (BD) reliability. Our findings on n-channel metal-oxide-semiconductor devices with these gate electrodes reveal that the application of low negative bias stress after a soft-BD (SBD) event helps to restore the oxygen ions and passivate the oxygen vacancy traps that comprise the percolation path. This can be a simple yet effective designfor-reliability tool to initiate the self-repair of the percolation path and operate the circuit for a prolonged period after repair. The only requirement for achieving this SBD reversibility is to choose gate electrodes that can serve as good oxygen reservoirs.

In this letter, submelt laser anneal used to achieve ultrashallow junctions (USJs) in capped high- devices with TaN/TiN metal gate electrode is investigated. The submelt laser anneal results in USJ and sharp junction on both n- and pMOSFET devices. However, this process induces interface and bulk defects and reduces negative-bias temperature instability (NBTI) reliability additionally. It is shown that if the laser anneal is followed by a rapid thermal anneal, the laser-related damage decreases, and the NBTI robustness improves without altering the obtained junction sharpness.

This letter reports a novel approach to achieve low threshold voltage (Vt) Ni-fully-silicide (FUSI) nMOSFETs with SiON dielectrics. By using a dysprosium-oxide (Dy2O3) cap layer with a thickness of 5 Aring on top of the SiON host dielectrics, Vt,lin of 0.18 V for long-channel devices (Lg = 1 mum) using NiSi-FUSI electrode is obtained, satisfying the high-performance device requirements. The Vt modulation due to the Dy2O3 cap layer is also maintained in the short-channel devices (with an Lg,min of 90 nm as demonstrated in this letter). In particular, approximately 150times reduction in gate leakage current is seen while preserving the dielectric capacitance equivalent thickness after adding the Dy2O3 cap layer on SiON dielectrics, likely due to a high-k layer (DySiON) formation during device source/drain activation process. We also report that the Dy2O3 layer does not vitally degrade the device reliability, such as positive-bias temperature instability and time-dependant dielectrics breakdown.

In downscaled poly-Si gate MOSFET devices reliability margin is gained by progressive wearout. When the poly-Si gate is replaced with a metal gate, the slow wearout phase observed in ultrathin SiON and HfSiON dielectrics with poly-Si gate disappears, and with it, the reliability margin. We demonstrate for several combinations of dielectric and gate materials that the large abrupt current increase (/spl Delta/I) as compared to poly-Si is not likely due to process issues, but is an intrinsic property of the dielectric/metal gate stack. The occurrence of large /spl Delta/I is a potential limitation for the reliability of metal gate devices.

The impact of the Al 2 O 3 position with respect to HfO' 2 in the process flow, is investigated. It is shown that Al 2 O 3 incorporation in order to increase the pMOS threshold voltage, slightly degrades the mobility, slightly increases NBTI and increases the EOT with respect to the reference without Al 2 O 3 Moreover, the trap density profiles depend on the Al 2 O 3 position: higher in the interfacial layer when Al 2 O 3 is below and higher in the HfO 2 when Al 2 O 3 is above HfO 2 • Furthermore, Al 2 O 3 below HfO 2 shows higher gate leakage, reduced LF noise but marginal NBTI difference compared to AL 2 O 3 above HfO 2 .

From the 32nm CMOS node on, trench shaped local interconnects are introduced to connect the individual transistors on a chip. Aggressive pitch scaling and overlay errors however challenge the integrity of the SiN dielectric between the gate and the local interconnects. In this work we study the reliability of this dielectric. It is found that the current between gate and the contacts is polarity independent and the breakdown voltage shows a strong polarity dependence. While within die good uniformity is observed, due to overlay errors the spacing between the gate and the contact varies across the wafer. This results in large VBD and tBD variability and for an intrinsic TDDB lifetime extrapolation correction for this non-uniformity required.

Higher κ-value HfO 2 (κ∼30) was evaluated in replacement metal gate pMOS devices. The higher-κ was achieved by doping and anneal of the HfO 2 causing crystallization into the cubic phase. The resulting gate-stack has up to 103 × lower gate-leakage current compared to a reference HfO 2 : JG at −1 V ∼ 2 µA/cm2 at EOT∼9.7 A. The better J G - EOT-scaling, result in performance and reliability improvements when normalized to the J G .

This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si 45 Ge 55 /Si cap deposition and the workfunction metal, high performance devices with balanced V t,sat (+0.12V, −0.16V) at scaled T inv ∼1nm and gate length L g ∼30nm are reported, leading to 17ps ring oscillators at 1µW/stage at Vdd=0.7V. Compatibility with gate last processing is also demonstrated.

In high-κ (HfSiON and HfLaO) metal gate stacks, the traps leading to gate current I g random telegraph noise (RTN) are found to be effectively passivated by bipolar switching from negative gate bias, where RTN and threshold voltage variation (ΔV T ) are reduced significantly or even disappear. The reduction of RTN, ΔV T and I g in degraded gate dielectrics is modeled by oxygen ion drift from the oxygen gettering metal gate electrode to re-passivate the traps upon negative gate bias. A performance boosting technique for transistors during operation is proposed. In this technique, the gate is swept by a small negative voltage to induce a bipolar switching and thus boost up performance after long duration of operation.

6A EOT Si 0.45 Ge 0.55 pFETs with 10 year lifetime at operating conditions (V DD =1V) are demonstrated. Ultra-thin EOT is achieved by interfacial layer (IL) scavenging. Negative Bias Temperature Instability (NBTI) is alleviated using a high Ge fraction, a thick SiGe quantum well (QW) and a thin Si cap. Hot Carrier Injection (HCI) and Time Dependent Dielectric Breakdown (TDDB) are shown also to not constitute a showstopper for optimized SiGe devices.

In this work we present the time dependent dielectric breakdown (TDDB) characteristics of LaO capped HfO 2 layers with an equivalent oxide thickness of 8A. The layers show maximum operating voltages in excess of 1V. Such high reliability can be attributed to very high Weibull slopes. We examine the origin of the high slopes by a detailed study of the evolution of the stress induced leakage current with time, temperature and stress voltage.

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO 2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ∼5 A and ∼8 A respectively for both n and pMOS devices. The drive currents at I off =100 nA/µm with V DD =1 V is 1.4 mA/µm and 0.6 mA/µm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V T of 0.3/-0.4V, good V T -uniformity, and V T -matching and very high cutoff frequencies at ∼290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.

At low energy range, the Lucky Electron Model does not describe correctly the Channel Hot-Carrier (CHC) degradation for transistors with both SiO 2 and high-k dielectric. A new picture to explain the CHC degradation behavior in nMOSFETs based on the dominant role of the gate voltage into the total CHC stress is presented.

This paper overviews integration challenges of low-V T gate-first CMOS featuring one metal gate electrode and one host dielectric with Al 2 O 3 and La 2 O 3 cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low V T enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the art SMDD device results are reported.

PBTI and NBTI reliability is investigated on La 2 O 3 and Al 2 O 3 capped n and pMOSFETs, respectively. Low V th devices are achieved using the capping layers without degrading BTI reliability. For the Al 2 O 3 capped pMOSFETs no additional defects related to the capping are observed. The La 2 O 3 capping layer for nMOSFETs induces shallow traps, which however are not critical at operating conditions.

This paper reviews some of the recent learning at IMEC in reliability research on high-k gate stacks. We show how measurement, characterization techniques and physical degradation models can be transferred from SiO2 (or SiON) single layers to SiO2(SiON)/high-k stacks. In a first part, negative bias temperature instability (NBTI) is discussed. We show how interface states created at the SiO2 (or SiON)/substrate interface determine to a large extend the NBTI. Nitridation has a strong negative impact on NBTI, while thickness or composition of the high-k layer have nearly no influence. In a second part, we discuss the effect of bulk traps in the high-k layer. These traps cause fast Vt-instability and hysteresis, as well as significant positive bias temperature instability (PBTI). Additional bulk traps are created under electrical stress and form percolating paths of two or more traps causing soft breakdown (SBD). At low voltage and with metal gates, the SBD-leakage path develops into a hard breakdown (HBD) after some further wear-out time. We summarize the methodology to come to a complete reliability prediction that includes multiple SBDs and HBD. In high-k stacks, the leakage current increase due to multiple SBDs can be a reliability threat for some applications.

We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.

Channel hot-carrier (CHC) degradation in short channel transistors with a high-k gate stack processed in CMOS technology has been analysed. For short channel transistors (L < 0.15mum), the most damaging stress condition has been found to be VG = VD instead of the "classical" VG = VD/2 for long channel transistors. In this work, we have demonstrated that this shift is not caused by the presence of the high-k layer but due to short channel effects. Furthermore, the CHC degradation lifetime has been evaluated, revealing larger operating voltages for high-k than for SiO2 transistors.

In this work, we investigate the possibility of achieving low VT nMOS FinFETs with single metal gate by using a dysprosium oxide (Dy2O3) cap layer inserted between gate dielectric and metal. We determine an optimum ratio between Dy2O3 and SiO2 gate dielectric thicknesses for low nMOS VT with good process margin and no loss in performance and reliability.

This paper reports a novel approach to implement low Vt Ni-FUSI bulk CMOS by using a dysprosium oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5 Aring) can lower the NiSi FUSI nFET Vt by 300 mV/500 mV on HfSiON/SiON (resulting in a Vt,lin of 0.25 V/0.18 V respectively), w/o compromising the Tinv (

This work reports the first comprehensive evaluation of FUSI gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance (high-VT applications) have been achieved (17ps at VDD=1.1V and 20pA/?m Ioff), meeting the ITRS 45nm node requirement for low power CMOS.

Some recent insights in reliability issues of high k/metal gate stacks for the 45 nm CMOS node and beyond are discussed. The problem of transient charging effects leading to threshold voltage instability is illustrated. It is shown that nitridation of Hf-silicate layers leads to severe degradation of the Negative-Bias-Instability (NBTI) lifetime. Some insights in the mechanisms of Time-dependent-Dielectric breakdown (TDDB) are discussed and illustrated.

In this work, we report an extensive characterisation of fully silicided gate (FUSI) devices with oxynitride (SiON) and Hf-silicate gate dielectrics. Enhanced drive current is obtained, in comparison with poly gate devices, together with an increase in electron/hole mobility and reduction in CET values. We show that the work function (WF) can be engineered by doping of the poly gates prior to FUSI for SiON devices but not for Hf-silicate devices. With reference to the poly gate, Hf-silicate/FUSI devices exhibit improved TDDB reliability behavior, having higher acceleration factor (/spl gamma/) values. NBTI gives a maximum operating voltage above 1.2 V for /spl Delta/V/sub T/ = 10% or 30 mV, as extrapolated for a 10 years-lifetime.

In this paper, the electrical performance of high-k dielectrics for future technology generations is discussed. Despite major achievements in the development of high-k dielectrics, such as the gate leakage reduction - which is the main motivation why high-k dielectrics are being introduced - and the successful integration in small MOSFET devices, some major problems remain to be solved. These problems are threshold voltage control and stability, mobility and drive current performance and reliability problems. Significant progress in the performance of these layers was made by the use of engineered interfaces and optimized high-k stacks.

The electrical stability of CMOS devices with conventional gate dielectrics is commonly studied using static (DC) measurement techniques. By applying the same methods to MOS devices with alternative gate dielectrics, it has been shown that alternative gate stacks suffer from severe charge trapping and that the trapped charge is not stable, leading to fast transient charging components. In this paper, time-resolved measurement techniques down to the /spl mu/s time range are applied to capture the fast transient component of the charge trapping observed in SiO/sub 2//HfO/sub 2/ dual layer gate stacks. Furthermore, its impact on the device performance and reliability of n-channel FETs is discussed.