Search

Current filament (CF)-related double-hysteresis ${I}$ – ${V}$ behavior and holding current, ${I} _{\text {HOLD}}$ , are analyzed using experiments and 3-D technology computer-aided design (TCAD) simulation in silicon-controlled rectifiers (SCR) for system-level electrostatic discharge (ESD) protection. Our 3-D TCAD methodology uses up and down quasi-dc current sweeps to reveal a memory effect in the current density distribution along the device width. ${I} _{\text {HOLD}}$ is related to the smallest possible CF where the self-sustaining SCR action takes place during down current sweep. ${I} _{\text {HOLD}}$ exhibits a nontrivial dependence on device width, depending on whether a CF is created or not. Analyzing devices of different layouts shows that ${I} _{\text {HOLD}}$ values determined from experiments and 3-D TCAD are almost layout-independent and substantially lower than those evaluated from 2-D TCAD. ${I} _{\text {HOLD}}$ calculated by 3-D TCAD in edge-terminated devices is higher than that in 3-D structures obtained from simple width-extended 2-D doping profiles. The use of latter devices, thus, simplifies the 3-D TCAD ${I}$ – ${V}$ analysis and provides a safe margin for ${I} _{\text {HOLD}}$ prediction. The work is relevant for designing the latch-up immunity of ESD protection devices, and it also shows that conventional 2-D TCAD can provide unwanted overestimation of ${I} _{\text {HOLD}}$ .

Multi-finger floating-base silicon controlled rectifiers (SCRs) of discrete technologies are investigated by transmission line pulses (TLP) with short (300ps) and long (10ns) pulse rise times (RT). Transient interferometric mapping (TIM) is applied to study the finger triggering dynamics. The measurements are correlated with TCAD simulation. It is found that for short RT the fingers trigger simultaneously which is due to the positive influence of a voltage overshoot related to delayed conductivity modulation. For long RT the fingers trigger sequentially which is accompanied by the voltage drops near the holding voltage. The time delay between the triggering of neighboring fingers is in the 3–150ns range and depends on the actual current density in fingers. The sequential finger triggering is due to lateral carrier diffusion-limited processes and the coupling via substrate currents.

During triggering of an on-board ESD protection, e.g., an SCR, its voltage may temporarily rise to a large value. This work identifies and distinguishes the two major factors that contribute to this voltage overshoot: (1) the conductivity modulation in the silicon and (2) the inductance of the metal traces. The overshoot is shown to have a major impact on the residual current into the IC during a system level discharge (ESD gun test), in particular in high-speed interfaces, such as USB3. This work presents a physics-based behavioral model which accurately describes both contributions to the voltage overshoot. The conductivity modulation model is based on the premise that the doping concentration of a region in the SCR is insufficient to conduct the trigger current. It follows that a minimum charge must be injected into the low-doped region to enable conduction of the trigger current. SCR triggering is delayed until this minimum charge has been injected. During the delay time, the SCR voltage is determined by the high ( $\sim 1~\text{k}\Omega $ ) off-resistance of the device. After triggering, the voltage is determined by the low-impedance ( $\sim 0.25~\Omega $ ) on-resistance. The net effect is a voltage overshoot. This first overshoot is followed by a second inductive voltage overshoot at the time when L.dI/dt is maximum. The paper demonstrates how the resulting model can be used to improve system level robustness for a typical USB3 interface.

We investigated the Phase Change Memory (PCM) capabilities of In-doped Sb nanowires (NWs) with diameters of (20-40) nm, which were self-assembled by Metalorganic Chemical Vapor Deposition (MOCVD) via the vapor-liquid-solid (VLS) mechanism. The PCM behavior of the NWs was proved, and it was shown to have relatively low reset power consumption (~ 400 μW) and fast switching capabilities with respect to standard Ge-Sb-Te based devices. In particular, reversible set and reset switches by voltage pulses as short as 25 ns were demonstrated. The obtained results are useful for understanding the effects of downscaling in PCM devices and for the exploration of innovative PCM architectures and materials. Keywords: Phase change memories, Nanowires, MOCVD, In-Sb, TEM, XRD

Capacitance transient spectroscopy and dc current–voltage ( I–V ) characterization are employed to analyze charging/discharging effects and transport in 200-nm-thin carbon-doped GaN layers (GaN:C) with a low ( ${N}_{\textsf {C}} = \textsf {10}^{\textsf {18}}$ cm $^{-\textsf {3}}$ ) and high ( ${N}_{\textsf {C}} = \textsf {10}^{\textsf {19}}$ or ${N}_{\textsf {C}}= \textsf {7}\times \textsf {10}^{\textsf {19}}$ cm $^{-\textsf {3}}$ ) carbon concentration ${N}_{\textsf {C}}$ . The discharging and charging events are found to be governed by transport properties of GaN:C for whole ${N}_{\textsf {C}}$ range. However, distinct temperature behavior has been found as a function of ${N}_{\textsf {C}}$ . In the samples with low ${N}_{\textsf {C}}$ , an Arrhenius-like behavior with an activation energy of 0.8 eV indicates that the hole transport in valence band (VB) is the limiting process and the carrier exchange occurs between VB and the defect level. In contrast, in samples with high ${N}_{\textsf {C}}$ , a non-Arrhenius charging/discharging behavior with exp( aT )-dependence ( ${a}$ being a constant) in a wide temperature range (150–560 K) indicates that the transport is governed by defect bands (DBs) where the carrier exchange occurs between DBs and the carbon defect level. For samples with ${N}_{\textsf {C}} \ge \textsf {10}^{\textsf {19}}$ cm $^{-\textsf {3}}$ , the large charge accumulation in GaN:C produces a large energy barrier to prevent electron injection from n-GaN to GaN:C, thus making GaN:C blocking. This is in contrast to samples with ${N}_{\textsf {C}} = \textsf {10}^{\textsf {18}}$ cm $^{-\textsf {3}}$ where the barrier is low, rendering thus the bilayer leaky. Detailed physical models for carrier capture and emission processes and carrier transport are provided for both cases. The developed knowledge is important for understanding the role of growth parameters such as ${N}_{\textsf {C}}$ and dislocation densities, as well as for reliability testing and defect analysis.

The operation of stacked MOSFET circuit for RF switch application under electrostatic discharge (ESD) conditions is studied by transmission line pulse (TLP) and transient interferometric mapping (TIM) techniques combined with circuit simulation. TLP pulses with 100–840 ns durations were applied to the device composed of 16 stacked multifinger MOSFET blocks with gate and drain resistors, fabricated in a bulk technology. ESD discharge paths related to MOSFET channel and to open-base breakdown have been identified to have dominant role in explaining the complex voltage and current waveforms. The overall circuit behavior during TLP pulses is analyzed taking into account calibrated breakdown measurements on test structures. In order to explain the heat dissipation in MOSFET blocks measured by TIM, additional discharge paths related to block-to-block coupling due to parasitic bipolar action have been modeled and discussed. Besides the analysis of the device behavior, we have also investigated peculiar optical TIM signal related to anisotropic reflectivity and phase response due to dense multifinger block structure.

Two particular defects are commonly discussed at the III-N interface: the required donor states, known to exist from the formation of the two-dimensional electron gas (2DEG) below a hetero-barrier, and defect states at the interface or within the dielectric layer. It appears that the latter ones are responsible for the ongoing challenge to find a low-defect gate dielectric to reduce positive bias temperature instabilities (PBTI). This raises the question, why the natively given donor states behave almost like fixed charges. We review the known and verified characteristics for both defect types and the link between them. Moreover, we define a lifetime criterion for power switching applications to compare PBTI effects related to III-N interfaces.

Transient interferometric mapping (TIM) and backside light emission microscopy (EMMI) are applied to study the trigger behavior and on-state spreading in discrete-technology electrostatic discharge (ESD) protection silicon controlled rectifier (SCR) test-structures without and with trigger taps. The trigger taps or device corners are clearly identified as regions where the avalanche breakdown and SCR action are initiated. The regions relevant to the holding current can be identified by EMMI. In SCR mode the injection regions from the npn and pnp emitters have been localized by TIM. The on-state spreading (OSS) speed of 1–4 μm/ns obtained from TIM is consistent with the results of 3D TCAD simulations. The driving force of the OSS is discussed on the basis of TCAD results.

This paper reports an analysis of the degradation mechanisms of GaN-based normally-off transistors submitted to off-state stress, forward-gate operation and electrostatic discharges. The analysis was carried out on transistors with p-type gate, rated for 600 V operation, developed within the European Project HIPOSWITCH. DC measurements, thermal analysis by transient interferometric mapping (TIM), and transmission line pulse (TLP) were used in combination to achieve a complete description of the degradation and failure processes. The results of this investigation indicate that: (i) the analyzed devices have a breakdown voltage (measured at 1 mA/mm) higher than 600 V; in off-state, drain current originates from gate–drain leakage for drain voltages (VDS) smaller than 500 V, and from vertical leakage through the conductive substrate for higher drain bias. (ii) step-stress experiments carried out in off-state conditions may induce instabilities in both drain–source conduction and gate leakage. Failure consists in the shortening of the gate junction, and occurs at VDS higher than 600 V. (iii) in forward bias, the p-type gate is stable up to 7 V; for higher gate voltages, a time-dependent degradation is detected, due to the high electric field across the AlGaN barrier; (iv) TIM analysis performed under short-circuited load conditions revealed hot spots at the drain side of the channel in the access region, thus indicating that these regions may behave as weak spots under high bias operation. Cumulative device degradation under such repeating pulses has also been revealed. (v) TLP tests were carried out to evaluate the voltage limits of the devices under off-state and on-state conditions. The results described within this paper provide relevant information on the reliability issues of state-of-the-art normally-off HEMTs with p-type gate.

In this work, current multiplication at high electric field in epitaxial boron-doped diamond with high acceptor concentration is analyzed, including self-heating effect and impurity impact ionization. Quasi-static current-voltage (I-V) characteristics were measured using a transmission-line pulse setup with 100 ns pulse duration on samples with two Ohmic titanium/gold electrodes. Unambiguous exponential and super-exponential behaviors are observed in the I-V curves along with, in some cases, negative differential resistance. The self-heating effect is analyzed using transient interferometric mapping of the thermal energy distribution between electrodes with an ns time scale. Measured I-V characteristics are modelled by finite element method and by considering boron acceptor ionization due to self-heating effect and impurity impact ionization. Simulated I-V characteristics, in particular the appearance of the negative differential resistance region attributed to self-heating, are in good agreement with experimental data.

We analyse high temperature effects (up to 420 °C) in the performances of p-GaN gate normally-off AlGaN/GaN HEMTs on Si and SiC substrates for power applications. With increasing temperature, IDMAX (R ON ) decreases (increases) and the threshold voltage slightly decreases independently of the substrate and doping. The room temperature (RT) DC IV characteristics of the devices after 90 min at temperatures above 300 °C are not affected. Step stress experiments at 420 °C show more than twofold decrease of the blocking capabilities compared to RT. Finally, thermal activation of the vertical leakage current has been analysed up to 180 °C.

The ESD robustness of multi-finger nMOSFET transistors in an advanced RF CMOS technology has been analysed by both TLP and, for the first time, by transient interferometric mapping (TIM) technique. Failure current It2 has been studied for different source, gate and bulk contact grounding configurations, for TLP pulse duration between 25 ns and 550 ns and TLP rise time of 1 ns and 10 ns. The lateral distribution of dissipated thermal energy during a TLP pulse has been measured by TIM. The ESD failures for selected pad configurations are investigated by DC-IV and physical failure analysis. The highest (lowest) It2 has been revealed for floating (grounded) gate and bulk pads, and attributed to the pn junction (gate oxide) damage.

DC and transient self-heating effects are investigated in normally off AlGaN/GaN transistors designed for a high-power operation. Electrical and optical methods are combined with thermal simulations; 2-μs-long voltage pulses dissipating about 4.5 W/mm are applied on four different transistor structures combining GaN or AlGaN buffer on an n-type SiC substrate with or without Ar implantation. Transistors with only 5% Al mass fraction in the buffer show almost a threefold increase in the transient self-heating if compared with devices on the GaN buffer. On the other hand, 2-μs-long pulses were found not to be long enough for the Ar-implanted SiC substrate to influence the device self-heating unless AlGaN composition changes. In the dc mode, however, both the buffer composition and Ar implantation significantly influence the self-heating effect with the highest temperature rise for the transistor having the AlGaN buffer grown on the Ar-implanted SiC. We point on possible tradeoffs between the transistor high-power design and the device thermal resistance.

The transient recovery characteristics of the threshold voltage drift (ΔVth) of GaN-based HEMTs with a SiO2 gate dielectric induced by forward gate bias stress are systematically and comprehensively investigated for stress times from 100 ns to 10 ks, recovery times from 4 μs to 10 ks, and stress biases from 1 to 7 V. The measured recovery data are analyzed using the concept of capture emission time maps. It is shown that the observed data cannot be explained by simple first-order defect kinetics. It is revealed that the recovery curves for constant stress times scale with the stress bias. Furthermore, the shape of the recovery curves changes from concave to convex with increasing stress time, independent of the stress bias. For short stress times and low stress bias, a dominant rate limiting effect of the III/N barrier layer is proposed. Defect-related physical processes with a broad distribution of characteristic time constants are discussed to explain the logarithmic time dependency of ΔVth stress and recovery, at which the role of the Coulomb feedback effect, complex defects, and spatially distributed defects are considered.

Electrostatic discharge behavior of integrated SiGe heterojunction bipolar transistors is investigated by transmission line pulse (TLP) and transient interferometric mapping techniques. When stressing collector - base junction in reverse direction, two distinct non-thermal failure modes, depending on TLP pulse rise time (RT), have been found: For RT ≥ 10 ns the observed failure at a critical voltage is attributed to base corner breakdown as supported by failure analysis. For RT ≤ 5 ns the failure occurs due to parasitic capacitance coupling which virtually short-circuits the base-emitter junction at the pulse beginning and thus induces a parasitic bipolar action.

Stress and recovery dynamics of the drain current are analysed in normally-off GaN Hybrid-Drain - embedded Gate Injection Transistors (HD-GITs) submitted to a semi-ON state stress. Under this condition moderate drain current and high drain voltage (350-650 V) are applied simultaneously. During the stress phase the drain current shows a remarkable decrease due to hot carrier trapping and is dependent on the applied drain voltage, stress current and temperature (30–190 °C). This degradation is fully recoverable, either thermally in the temperature range 150–190 °C or by hole injection from the gate. We provide a model for the detrapping time constant taking into account both the thermally-driven process dominating for gate biases VGS 3 V.

The impact of surface treatment of 5 nm in situ SiN passivation on the performance of InAlGaN/GaN high electron mobility transistors is analyzed. After operation at 600 °C, no device degradation is observed, confirming the thermal stability of the passivation layer. The in situ SiN, grown by metalorganic chemical vapor deposition, is treated by first Ar ion sputter cleaning, intentional oxidation in water and second cleaning. The results of current collapse characterization show that the SiN surface contains a humidity related trap density of about 1.04 × 10 12 cm −2 , which can be reduced to 0.21 × 10 12 cm −2 by Ar sputter cleaning. The surface cleaning allows for deposition of further layers without degradation of the device properties. In this study, 25 nm SiN is deposited subsequently by conventional plasma enhanced chemical vapor deposition, resulting in the same device performance as the devices processed with 30 nm in situ SiN.

The thermal properties of sub-μm nanocrystalline diamond films in the range of 0.37–1.1 μm grown by hot filament CVD, initiated by bias enhanced nucleation on a nm-thin Si-nucleation layer on various substrates, have been characterized by scanning thermal microscopy. After coalescence, the films have been outgrown with a columnar grain structure. The results indicate that even in the sub-μm range, the average thermal conductivity of these NCD films approaches 400 W m− 1 K− 1. By patterning the films into membranes and step-like mesas, the lateral component and the vertical component of the thermal conductivity, klateral and kvertical, have been isolated showing an anisotropy between vertical conduction along the columns, with kvertical ≈ 1000 W m− 1 K− 1, and a weaker lateral conduction across the columns, with klateral ≈ 300 W m− 1 K− 1.

We investigate the effect of elevated ambient temperature on thermal breakdown (TB) modes in linear-geometry electrostatic discharge (ESD) protection n-p-n transistors of smart power technology subjected to 0.5-1- μs-long ESD pulses. The current transport in these devices has a form of traveling current filaments (CFs) where TB at room temperature occurs at one of the device ends. An increase in ambient temperature gives rise additionally to another failure mode, inside the device. For the failure mode at the device end, the increase of ambient temperature in the range up to 100°C causes shortening of the averaged time to TB 〈tTB〉 by a duration that the CF needs for one round trip over the device width. At ambient temperatures up to 180°C, the TB may occur even at initial triggering CF position inside the device, before the CF starts to move. The ambient temperature at which the transition between CF modes with different 〈tTB〉 occurs is investigated as a function of stress current. Furthermore, inspecting the failure current of devices with different widths shows that there is an equivalence between the effect of increased ambient temperature and the effect of the preheating at the device end by a previous CF passage. The experiments are supported by 3-D thermal simulation of temperature in moving and standing CFs.

We analyze the degradation of InAlN/GaN HEMTs using a secondary gate electrode placed on top of the SiN passivation layer in between the Schottky gate and drain contact. Although the actual transistor showed only minor degradation during the stress test under off-state bias for more than 60 h, a linear increase of trapped charges in the SiN layer has been detected starting at about 13 h of stress. The charge increase is correlated with the increased leakage current and dielectric breakdown at the secondary gate.

Intrinsic device temperature is one of the most important limits of the safe operating area and of the reliability of power double-diffused metal-oxide-semiconductor (DMOS) transistors. Therefore, precise knowledge of the temperatures throughout the device, up to the onset of thermal runaway is required. However, standard methods that measure the surface temperature, such as infrared thermography, usually cannot be applied to most advanced power technologies. Therefore, we propose to embed very small temperature sensors within the active DMOS cell array itself. These sensors are located very close to the heat-generating regions, having a tight thermal coupling, thus giving an accurate measurement of the intrinsic device temperature. Moreover, due to their small size, many sensors can be integrated into a power DMOS for a good spatial resolution. The sensors have been implemented in a smart power production technology. Calibration and verification up to 600 °C, as well as further validation up to 400 °C, by comparison to transient interferometric mapping measurements are discussed. The usefulness of the sensors is demonstrated by characterization of the thermal runaway, by measurements with a high spatial resolution achieved by 60 sensors in conjunction with an on-chip multiplexer, and by an assessment of the peak temperature reduction that can be obtained by using thick power metal layers for increased heat capacitance.

A linear correlation between 100 ns TLP and the second HMM peak current was found for several common types of protection devices. A detailed thermal analysis offers a straightforward explanation of the correlation factor in terms of pulse duration. It is found that the thermal effect of the first HMM peak can be ignored. The impact of non-thermal failure mechanisms, e.g. gate oxide breakdown due to an over-voltage, which may limit the validity of the correlation are explored for a complete system, which includes additional components. The results from this investigation are essential for proper application of the System-efficient ESD Design (SEED) methodology.

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al2O3 gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al2O3 growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ∼0.6 A/mm (VGS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al2O3 dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.

This paper focuses on optimization of bond wire positions as a method to improve thermal management of power semiconductors. For this purpose, robustness of a new low-voltage MOSFET generation with an optimized multiple bond wire arrangement and device shape is compared to an older device design with lower number of bond wires. 2D electrical simulation is used to evaluate the lateral distribution of power dissipation due to the gate voltage de-biasing effect. 3D thermal finite element simulation and infrared thermography measurements are employed to analyze the corresponding surface temperature distribution. Finally, tests under extreme single pulse short-circuit conditions demonstrate the effectiveness of thermal management for improving robustness in automotive applications.

Transient Interferometric Mapping (TIM) tools are reviewed from a perspective of their particular application area and comparison to other transient optical analysis techniques. TIM studies on trigger behavior, current filamentation and failure modes in BCD DMOS and ESD protection devices under TLP and system-level-ESD – like pulses are overviewed. TIM analysis of CMOS ESD protection devices, in particular study of on-state spreading effect in 90 nm SCRs is also presented. Furthermore TIM investigations of substrate currents and parasitic SCR paths during transient latch-up events in 90 nm CMOS and BCD technology test structures and products are reviewed. Finally TIM studies of ESD and short-time self-heating phenomena in GaN HEMTs and lasers are also briefly mentioned.

Due to the negative-differential-resistance-related instability, the current-density distribution in sufficiently wide devices exhibiting S-shaped I-V characteristics becomes inherently inhomogeneous along the device width. High-current-density on-state (i.e., a current filament) and low-current-density off-state regions are spontaneously formed, leading to the formation of a vertical branch in the I-V curve at a so-called coexistence voltage uCO. In electrostatic discharge (ESD) protection devices (PDs), this vertical I- branch usually determines the lowest voltage point that can be accessed by a conventional transmission line pulser (TLP). However, the real holding point of device VH, which is related to an I-V part with a homogeneous current distribution, lies below uCO, i.e., VH

The influence of the source/body layout on the electrical safe operating area (SOA) of both vertical and lateral double-diffused metal-oxide-semiconductor transistors is experimentally investigated using a transmission line pulse system. Tradeoff between RDSon ·Area and SOA is discussed. Stripe geometries with and without (i.e., conventional design) body contact extension and cell designs with circular and oval geometries are considered. It is shown that a circular design of the source/body cell is superior with respect to SOA, compared with the conventional stripe design. The oval design is used to improve RDSon ·Area without compromising SOA performance, compared with the circular design.

Electrostatic discharge (ESD) protection diodes with a breakdown (BD) voltage above 50 V might exhibit a BD delay in the order of microseconds. The phenomenon is related to the low generation of seed carriers that can start an avalanche BD event by impact ionization. However, emission of carriers from deep traps, or the onset of tunneling generation, can shorten the delay to only fractions of a nanosecond. Emission from deep traps has been found strong enough to make this kind of device effective for protection under standard ESD conditions. However, the application of a bias voltage prior to a stress pulse empties the trap states and thus leads to increasing BD delay. This paper investigates the BD delay in an ESD protection diode under various bias and pulse conditions. A model for the BD delay is proposed, taking into account the different seed carrier generation mechanisms. The activation energy of the dominating deep trap can be calculated to 0.18 eV by measuring the time to BD at different temperatures.

Electro-thermal destruction of n- and p-channel lateral double-diffused MOS in smart power ICs is investigated by electrical pulse experiments, simulations and failure analysis. It was observed experimentally and by TCAD simulation that the location of the hot spot plays very important role for single pulse energy capability. Damage both in silicon and copper metallization was observed. The n-DMOS exhibits better energy capability compared to p-DMOS due to better cooling efficiency of silicon area by the copper metallization. Effect of drift region length, doping profile and of copper metal thickness on energy capability is also analyzed.

Temperature distribution in diced and packaged DMOS devices subjected to repetitive stress is analyzed using transient interferometric mapping (TIM) technique combined with measurements on diode built-in temperature sensors. The effect of DMOS device position on dice, duty cycle and chip ambient temperature on thermal distribution is studied. The TIM experiments and transient temperature measurements are in good agreement with numerical 3D thermal simulations. Failure analysis data after long term pulse stress testing indicate electromigration degradation of the top metal.

Substrate current distribution as trigger for external latch-up (LU) and transient latch-up (TLU) is analyzed by optical transient interferometric mapping (TIM) technique. The transient free carrier (plasma) concentration related to substrate current flow is studied for various guard-ring configurations and injection carrier type on special test structures and real I/O cells. TIM uncovers proximity effects in I/O cells causing substrate current crowding which are important for the definition of effective LU protection concepts.

Electrostatic-discharge (ESD) tests with IEC 61000-4-2 generators are often performed at component level but are known to suffer from poor reproducibility. In this paper, it is shown that IEC 61000-4-2 generators can charge the tested device to several tens of volts before the actual ESD pulse is applied. This pre-pulse voltage (PPV) can lead to delayed avalanche breakdown (BD) initiation in silicon junctions. The origin of the BD delay is the emptying of deep trap states within the space-charge region, which lowers the contribution to the generation current due to carrier emission from the deep states. The BD delay is critical for ESD protection devices and can also lead to a dramatic reduction of the snapback trigger current in DMOS transistors. However, transient gate turn-on of the DMOS transistor eliminates the BD delay and can thus increase the ESD robustness. It is shown that the PPV varies strongly between commercial IEC generators, and it is proposed that this could be one of the main reasons for the poor reproducibility of IEC tests. A newly proposed method to deliver an IEC 61000-4-2-shaped pulse through a 50-? transmission line is investigated with respect to the correlation with real IEC generators. It is shown that PPV-related issues are not addressed by this method, unless an additional bias voltage is applied during the test. It is also demonstrated that PPV is existent in real-world IEC discharges and must not be neglected for component qualification.

A calibrated system for power metal reliability analysis in smart power technology chips is presented. This system is mainly designed for temperature evaluation during temperature-cycling experiments. Infrared camera measurements under single shot high energy pulses are correlated with electro-thermal finite element simulation and failure analysis. A special test structure, containing poly-silicon heaters, is used to produce thermal stress. The location of a hot spot agrees well with the position of degraded power metal.

The thermal distribution in large DMOS output transistors of a half-bridge driver IC fabricated in smart-power SOI technology is investigated by the backside transient interferometric mapping (TIM) technique during its thermal shutdown process. The TIM measurements uncovers four hot spots, where the temperature exceeds the limit of the built in temperature sensor. This explains the specific failure mode which was identified during accelerated reliability tests. The TIM results are complemented by temperature measurements with the build-in temperature sensors.

We present the technology and performance of InAlN/AlN/GaN MOS HEMTs with gate insulation and surface passivation using Zr or Hf . About 10-nm-thick high- dielectrics were deposited by MOCVD before the ohmic contact processing. Plasma pretreatment allowed the reduction of the temperature of the ohmic contact annealing at 600degC. The insulation and passivation of 2-m gate-length MOS HEMTs lead to a gate leakage current reduction by four orders of magnitude and a 2.5 increase of the pulsed drain-current if compared with a Schottky barrier (SB) HEMT. A dc characterization shows 110 mS mm transconductance and 0.9 A mm drain--currents that represent improvements in comparison to the similar SB HEMT and that is explained by a mobility-dependent carrier depletion effect.

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm–14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

Triggering uniformity and current sharing under TLP stress is investigated in low voltage multi-finger gg-NMOS and NPN ESD protection devices fabricated in smart-power SOI technology. Inhomogeneous current distribution over the fingers and within a single finger is detected by the backside transient interferometric mapping (TIM) technique. 2D TCAD device simulations of the multi-finger devices are used to explain the experimental TIM results. Changes in differential resistance in the pulsed IV characteristics of the NPN ESD protection devices are also explained by TIM experiments.

Transient interferometric mapping (TIM) setup for ns-time ESD testing is adapted for post-stress failure analysis. Probing from the chip backside using the thermo-optical effect is used for localization of heating place related to failure. Two variants of 2D holographic interferometers, a Michelson and a “Wollaston” one, are used for a rough identification of a failure site. An adapted scanning heterodyne interferometer is used for accurate position determination with a 2 μm space resolution. The methods are applied to identify ESD damage and metal shorts. Sensitivity and space resolution are analyzed, supported by a 3D-thermal simulation of repetitive heating signal. A power sensitivity of 50 μW for a single point heat source is demonstrated.

We investigate electrical properties of Ni/Al2O3/GaN metal–oxide–semiconductor (MOS) structures having different pre-treatment of GaN surface by O2, Ar and NH3, combined with various temperature of annealing. MOS and reference Ni/GaN Schottky contact are characterized using current–voltage and capacitance–voltage methods. MOS structures compared with the Schottky contact ones show leakage current reduction for all types of processing, from 3 to 5 orders of magnitude in reverse direct. We observed substantial influence of the pre-treatment on electrical parameters of MOS structures.

Current flow uniformity during ESD induced latch-up event is investigated in multi-finger LDMOS clamps and SCR ESD protection devices fabricated in a 0.6 μm high voltage CMOS process. Current flow, excess free carrier and hot spot distribution are analyzed by transient interferometric mapping technique combined with a latch-up pulse system consisting of a solid state pulser and a clear pulse unit. During latch-up, the current in the LDMOS clamps flows just in a single spot and the failure position is random and independent on device type. The position of the failure site correlates with the trigger position of the device. The SCRs exhibit pulse-to-pulse instabilities in the current flow.

An automated setup for investigation of degradation mechanisms in semiconductor devices under electrostatic discharge (ESD) stress is presented. Vertical-DMOS transistors of a Smart Power technology operating in bipolar snapback mode are studied by combined techniques. The current filamentary behavior imaged by a two-instants transient interferometric mapping (TIM) method and the variation of device DC characteristics are studied as a function of stress current. During repeated stress, a progressive degradation of the DC leakage current at the failure level and a slight gradual change of transfer characteristics are observed. The failure location, resolved in three dimensions by backside infrared microscopy, agrees with the position obtained from the TIM analysis and expected from device physics.

On-wafer transmission line pulsing (TLP) measurements and transient interferometric mapping experiments on vertically integrated DMOS transistors reveal the presence of hot filament hopping between the two parasitic bipolars. The activity of both intrinsic bipolar transistors is dependent on the TLP current. In addition, a traveling filament along the device width is observed, the traveling speed being estimated to be between 370 and 480 m/s.

Dynamics of localized current filaments is analyzed in electrostatic discharge protection devices of a smart power technology during microsecond long constant current pulses. Experiments performed by backside transient interferometric mapping technique and transmission line pulser stressing are correlated with 3D device simulation. Motion of the filament along the device width and its reflection at the device ends are observed. This behavior is related to the time evolution of the voltage waveform and is explained by the simulation. The filament motion is driven by the temperature gradient in the filament due to the negative temperature dependence of the impact ionization rates. A simplified analytical expression for the filament speed as a function of stress conditions and thermal characteristics is given.

The very fast dynamics of threshold voltage drift (ΔVth) of GaN-based metal-insulator-semiconductor-HEMTs induced by forward gate bias stress is investigated with a simple oscilloscope based setup. We show that the logarithmic recovery time dependence of ΔVth, previously found for recovery times ranging from 10 ms up to 1 ms, extend even to the μs regime. Further, we observed an accumulation of ΔVth because of repetitive stress pulses of 100 ns. Consequences for device operation and reliability are discussed.

We investigate the properties of high-k dielectric insulators on GaN. 22 nm thick ZrO2 is deposited on N- or Ga-polarity GaN. Al/ZrO2/GaN metal–oxide–semiconductor and reference Au/Ni/GaN Schottky contact structures are characterized using current–voltage and capacitance–voltage methods. If compared with Schottky contacts, metal–oxide–semiconductor structures show leakage current substantially reduced for the N-polarity GaN while comparable values were obtained for the Ga-polarity GaN. The oxide relative permittivity is found to be in the range of 20–30. Light-assisted capacitance–voltage method shows density of interface states Dit ~ 1 × 1012 cm−2 eV−1 for Ga-polarity and ~2 × 1012 cm−2 eV−1 for N-polarity GaN/ZrO2. Finally, we prepared AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistor proving minimal transconductance deterioration and small threshold voltage shift. It is suggested that ZrO2 deposition optimization may further reduce the leakage current.

Integrated vertical DMOS transistors of a 90-V smart power technology are studied under short-duration current pulses. Movement of current filaments and multiple hot spots observed by transient interferometric mapping under nondestructive snap-back conditions are reported. Device simulations show that the base push-out region associated with the filament can move from cell to cell along the drain buried layer due to the decrease of the avalanche generation rates by increasing temperature. The influence of the termination layout of the source field on the hot-spot dynamics is studied. Conditions for filament motion are discussed. The described mechanisms help homogenizing the time averaged current-density distribution and enhance the device robustness against electrostatic discharges.

We study degradation mechanisms in 50 μm gate width/0.45 μm length AlGaN/GaN HEMTs after electrical overstresses. One hundred nanosecond long rectangular current pulses are applied on the drain contact keeping either both of the source and gate grounded or the source grounded and gate floating. Source–drain pulsed I–V characteristics show similar shape for both connections. After the HEMT undergoes the source–drain breakdown, a negative differential resistance region transits into a low voltage/high current region. Changes in the Schottky contact dc I–V characteristics and in the source and drain ohmic contacts are investigated as a function of the current stress level and are related to the HEMT dc performance. Catastrophic HEMT degradation was observed after Istress=1.65 A in case of the ‘gate floating’ connection due to ohmic contacts burnout. In case of the ‘gate grounded’ connection, Istress=0.45 A was sufficient for the gate failure showing a high gate susceptibility to overstress. Backside transient interferometric mapping technique experiment reveals a current filament formation under both HEMT stress connections. Infrared camera observations lead to conclusion that the filament formation together with a consequent high-density electron flow is responsible for a dark spot formation and gradual ohmic contact degradation.

Switching dynamics and current flow homogeneity under very-fast TLP (vf-TLP) stress is investigated in smart power and CMOS technology ESD protection devices by means of optical transient interferometric mapping (TIM) techniques with sub-nanosecond time resolution. Comparison between the device behavior under vf- and conventional TLP stress is discussed. The sub-ns time resolution enables a detailed insight into the triggering behavior of protection elements.