28 results on '"Chan, Mansun"'
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2. Development of single-transistor-control LDO based on flipped voltage follower for SoC
3. Generic carrier-based core model for undoped four-terminal double-gate MOSFETs valid for symmetric, asymmetric, and independent-gate-operation modes
4. A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement
5. An integrated CMOS current-sensing circuit for low-voltage current-mode buck regulator
6. A high-density conduction-based micro-DNA identification array fabricated with a CMOS compatible process
7. Modeling of grain growth mechanism by nickel silicide reactive grain boundary effect in metal-induced-lateral-crystallization
8. A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film
9. Equivalent junction method to predict 3-D effect of curved-abrupt p-n junctions
10. A simple method for optimization of 6H-SiC punch-through junctions used in both unipolar and bipolar power devices
11. Design methodology of the high performance large-grain polysilicon MOSFET
12. Implementation and characterization of self-aligned double-gate TFT with thin channel and thick source/drain
13. Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization
14. A high gain N-well/gate tied PMOSFET image sensor fabricated from a standard CMOS process
15. Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method
16. The behavior of narrow-width SOI MOSFET's with MESA isolation
17. Fully depleted CMOS/SOI device design guidelines for low-power applications
18. On the power dissipation in dynamic threshold silicon-on-isolator CMOS inverter
19. Impact of scaling silicon film thickness and channel width on SOI MOSFET with reoxidized MESA isolation
20. A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation
21. A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation
22. A physically based compact device model for fully depleted and nearly fully depleted SOI MOSFET
23. Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFET's for high performance analog and mixed signal circuits
24. Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's
25. ESD reliability and protection schemes in SOI CMOS output buffers
26. A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application
27. High frequency performance of large-grain polysilicon-on-insulator MOSFETs
28. Performance of the floating gate/body tied NMOSFET photodetector on SOI substrate
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