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An analytic channel-potential-based non-charge-sheet model for long-channel symmetric double-gate (DG) MOSFETs with smooth transition between partially and full depleted (PD and FD) operation modes is described. The model has helped in understanding the DG MOSFET device physics, which has provided a physics-based DG MOSFET compact modeling framework for circuit simulation.

The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35-[micro]m CMOS technology. It is proven experimentally that the LDO provides stable voltage regulation at a variety of output-capacitor/ESR conditions and is also stable in no output capacitor condition. The preset output voltage, minimum unregulated input voltage, maximum output current at a dropout voltage of 200 mV, ground current and active chip area are 1 V, 1.2 V, 50 mA, 95 [micro]A, and 140 [micro]m x 320 [micro]m, respectively. The full-load transient response in the no output capacitor case is faster than a micro second and is about 300 ns. Index Terms--Flipped voltage follower (FVF), low drop out (LDO), loop gain and power management.

A generic carrier-based core model for undoped four-terminal double-gate (DG) MOSFETs, which is valid for symmetric, asymmetric and independent-gate-operation modes, is developed. This carrier-based model has provided solid foundation of developing a unified compact DG MOSFET model for circuit simulation.

A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current ([I.sub.Q] ~ 1 [micro]A) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small [I.sub.Q] and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage ([V.sub.DO]) with large-size pass transistor and ultra-low [I.sub.Q] can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18-[micro]m standard CMOS process and occupies 0.09 [mm.sup.2]. The LDO regulator can deliver 50-mA load current at 1-V input and ~ 100-mV [V.sub.DO]. It only consumes 1.2 [micro]A [I.sub.Q] and is able to recover within ~ 4 [micro]s even under the worst case scenario. Index Terms--High slew rate, low-dropout (LDO) regulator, low-quiescent current, tail current.

An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with [V.sub.TH] = 0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum output current of 120 mA and power-conversion efficiency higher than 89% are achieved. Index Terms--Closed-loop stability, current-mode buck regulator, dc-dc converter, low-voltage current-sensing circuit, on-chip current-sensing circuit, switched-mode power converter.

A high-density CMOS-compatible deoxyribonucleic acid (DNA) array, fabricated with a modified metallization process, is described and discussed.

The growth mechanism of metal induced lateral crystallization (MILC) is examined and modeled.

A thin-film transistor (TFT) model for grain-enhanced poly-Si TFT is described and discussed.

The breakdown characteristics of the 3-D abrupt p-n junctions are modeled by an equivalent junction method. The work provided by the analytical model and its advantages are mentioned.

An analytical solution for a breakdown of the 6H-SiC parallel-plane junctions is presented. It is then used to optimize base width and based doping of punch-through junctions used in both unipolar and bipolar high voltage power devices.

The effects of various design parameters such as the nickel strip locations, source/drain positions and transistor orientations on the performance of large-grain polysilicon-on-insulator (LPSOI) metal-oxide field effect transistors (MOSFETs) are investigated. It is shown that excellent device performance can be obtained from short and narrow devices.

An optimization of double-gate thin-film transistor (TFT) structure is studied and experimentally proved. It is found that self-alignment between top-gate, bottom-gate, thin channel region, and thick source/drain are all essential to give the desirable thin-film transistor (TFT) performance.

Research into the fabrication of a three dimensional complementary metal oxide semiconductor circuit is presented. The paper describes the use of metal-induced lateral crystallization, to build a high performance 3-D circuit.

The performance of a high gain photo-detector fabricated from a standard CMOS process is described.

High performance thin-film-transistors with differing channel widths and lengths, were formed by a novel grain enhancement technique.

A theoretical and experimental study of narrow-width effects in thin-film silicon-in-insulator MOSFETs is presented, incorporating MESA isolation technology.

Guidelines for the fully depleted (FD) complementary metal oxide semiconductors/silicon-on-isolator (CMOS/SOI) device for low-power applications were described. Device design guidelines using devices with L = 0.1 micrometer for FDSOI low-power applications were presented using an empirical drain saturation current model fitted to experimental data. Optimum buried oxide thickness was found to be between 300 and 400 nm for low-power applications. Optimum transistor size is when the driver device capacitance is 0.3 times the total load capacitance.

The power dissipation of dynamic threshold voltage MOSFET (DTMOS) has been measured. The value obtained is compared with the power dissipation and propagation delay of an inverter circuit made up of silicon-on-isolator (SOI) DTMOS and conventional floating-body SOI devices. Results of the comparison show that the DTMOS inverter uses more power than the conventional floating-body SOI CMOS inverter. It also has a smaller power-delay product when the power supply is below 0.7 V.

Research was conducted to study the properties of reoxidized MESA isolation for silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFET) in relation to the dependence of device performance on silicon film thickness and channel width scaling. Reoxidation process was optimized to accommodate performance degradation resulting from subthreshold leakage and narrow width behavior in ultra-thin devices and equipment.

A robust physical non-quasi-static (NQS) metal oxide semiconductor field effect transistor model that can be used for small-signal ac and large-signal transient analysis is formulated. This model, which can be applied to existing simulators, utilizes a physical relaxation time approach. This model requires less time in predicting NQS behavior compared with common SPICE models and the PISCES numerical device simulator.

The physical and continuous Berkeley Short-Channel IGFET I-V model in BSIM3v3, enhances the convergence property of circuit simulators. The dependencies of geometry and biases of parasitic series resistances, narrow width, bulk charge, and DIBL effects increase the accuracy of the model. The model has built-in dependencies of important dimensional and processing factors, permitting users to describe MOSFET characteristics accurately over a range of channel lengths and widths. It can be used for statistic modelling and has been implemented in various circuit simulators.

A physically based compact submicrometer Fully Depleted Silicon-On-Insulator (FDSOI) and Nearly FDSOI MOSFET all-region model is able to simulate both digital and analog circuits. It incorporates short channel effects and SOI specific mechanisms such as front and back coupling, parasite source/drain resistance effect, Drain Induced Conductivity Enhancement effect, floating body effect, and self-heating. The model uses a single parameter set for different channel lengths and widths. Its computational efficiency is confirmed with the help of experimental data using NMOS FDSOI devices.

The body-grounded non fully depleted (NFD) SOI MOSFET's with low-barrier body-contact technology have large output resistance and very low flicker noise compared to that of fully depleted (FD) SOI MOSFET's. The subthreshold characteristics and the variation of minimal threshold voltage of NFD SOI MOSFET are also better compared to that of FD SOI MOSFET. The performance of the NFD SOI MOSFET in the analog and mixed signal circuits is high compared to the performance of FD SOI MOSFET.

A quasi-two-dimensional model is used to study threshold voltage of a deep-submicrometer range effective channel length fully depleted silicon-on-insulator (FDSOI) MOSFET. Changes in the shift in threshold voltage is similar to that in the bulk but the roll-off in threshold voltage of FDSOI is less compared to bulk for the same effective channel length. The model gives accurate results as it does not assume charge partitioning and constant surface potential. The threshold voltage varies with the silicon film thickness.

The fabrication of electrostatic discharge (ESD) protection circuitries on the substrates of Silicon-On-Insulator (SOI) wafers improves SOI ESD protection performance to resolve reliability questions. A novel Through Oxide Buffer ESD protection scheme performs better than conventional SOI ESD protection because it allows bulk technology protection methods to be applied. A comparison of the results of ESD susceptibilities of various buffers, using Human Body Model stresses is given.

A self-aligned, electrically separable double-gate MOS transistor technology is described and discussed.

Research into the performance of large-grain polysilicon-on-insulator metal oxide semiconductor transistors is presented. The study shows that they perform in gigahertz range, reaching 3.4 GHz and 2.6 GHz at 1.2 micronm channel length.

A new photodetector on a silicon-on-insulator substrate is reported.