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Electrostatic charging of hospital personnel and patients during various activities increases the risk of electrostatic discharge (ESD) malfunctions of medical devices and the likelihood of patients’ adverse events. Therefore, the test level for ESD immunity of medical devices, specified in the IEC 60601-1-2 standard needs to reflect the reasonably maximum electrostatic voltages during usage. This study investigated the effects of material combinations and relative humidity on the body voltage while performing two routine clinical activities of lying down on a hospital bed and transferring to a bed using a sliding board. The peak body voltages in nearly 50% of the lying down experiments and 40% of sliding tests exceeded the test voltage level in the IEC 60601-1-2 standard (i.e., 15 kV). Using cotton blankets in lying down experiments and nylon sheets during sliding experiments resulted in 50% and 40% larger median than the median including all combinations, respectively. Sliding boards with antistatic coating reduced the peak body voltage by 24% on average, however, 33% of the tests still exceeded 15 kV. Based on the findings, recommendations are provided for healthcare facilities and medical device manufacturers to mitigate the risks of ESD malfunctions. [ABSTRACT FROM AUTHOR]

An analysis methodology is presented to investigate soft failures in electronic devices. This methodology combines transmission line pulse (TLP) full-wave simulations with system-level and TLP measurements. Information on susceptible parts in the device under test (DUT) and/or soft failure sensitivity of the integrated circuits (ICs) are obtained from the measurements. Then, the TLP current spreading within the printed circuit board (PCB) of the DUT is simulated. The susceptible signals can be determined by comparing the simulated voltages and/or currents at the signal terminations with the measured threshold values. If the simulated voltages and/or currents are higher than the threshold values, the signal is considered susceptible and a soft failure may occur in the DUT. Using the obtained information from simulations and measurements, the root causes of soft failures can be identified. Further, by utilizing full-wave simulations, the design of the product can be modified to reduce the electrostatic discharge (ESD) noise on the susceptible signals, and consequently prevent soft failures. The proposed analysis methodology is applied to a tablet which suffers from soft failure. The root cause of the soft failure is identified, and countermeasures are designed against the ESD-induced soft failure. [ABSTRACT FROM AUTHOR]

The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this brief. Owing to multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic silicon-controlled rectifier path featuring a very low holding voltage is found in the experimental silicon chip. Such a parasitic path is first reported in the literature. It may influence the electrostatic discharge robustness of CMOS IC products with the HV and LV circuits integrated together. Thus, the layout rules at the HV and LV interface should be carefully defined to avoid the occurrence of an unexpected parasitic path. [ABSTRACT FROM PUBLISHER]

This paper investigated the dependence of electrostatic field strength for spacecraft materials on voltage ramp rate, by applying an increasing incremental electrostatic field until electrostatic breakdown occurred. Tests on Kapton E found that at ramp rates two or three orders of magnitude lower than the maximum recommended rate, the electrostatic breakdown field, F\mathrm {ESD} was lower by a factor of two or more. This suggests that the tabulated values of F\mathrm {ESD} , which have been used by the spacecraft charging community, could substantially overestimate F\mathrm {ESD} in common slowly evolving spacecraft situations. This paper expanded these ramp rate tests to include a wider range of ramp rates and additional materials. By contrast, Kapton HN and biaxially oriented polypropylene (BOPP) data were found to be consistent with a single mean value F\mathrm {ESD} , rather than the proposed mean field and incremental voltage step ramp rate models. [ABSTRACT FROM PUBLISHER]

The generation of electrostatic charge is considered for the cases of standing up from a chair and removing a garment at dew points with temperature and relative humidity (RH) of −13.1 °C (5 °C, RH 25%), −10 °C (27 °C, RH 8%), −8.9 °C (18 °C, RH 15%), −1.7 °C (38 °C, RH 8%), 5 °C (27 °C, RH 25%), 5.6 °C (18 °C, RH 45%), and 13.9 °C (27 °C, RH 45%). Using ESD mitigation shoes/floors rather than non-ESD can reduce the voltages by a factor of ∼2 to 5 for garment removal and ∼2 to 7 for standing up from a chair. For the garment removal, the charge voltage will drop to 100 V within ∼0.5 to 6 s and within ∼1 to 30 min when ESD and non-ESD mitigation shoes/floors are used, respectively. For the standing-up form a chair, the corresponding times are ∼0.5 to 3 s and ∼1 to 4 min, respectively. For the extreme case at 22 °C, RH 5%, the voltage can surpass +/− 20 kV. Finally, it is shown that the voltages a person will charge up to may vary by +/− 30% just because of different capacitances to ground. Residential home settings will lead to the highest voltages (60 pF test person to ground, U.S. wood frame house), while standing on a concrete floor only half of the voltage may be reached (120 pF). [ABSTRACT FROM AUTHOR]

This paper presents a novel asymmetrical triboelectric nanogenerator (A-TENG) to produce, detect, and analyze contact electrification and electrostatic discharge (ESD) in the atmosphere. Thanks to the asymmetrical structures, the direct and continuous ESD phenomenon without any external electronic circuits is, for the first time, discovered by our experiments in A-TENG. Different from traditional contact-mode TENG, asymmetrical contact pairs introduce an unstable state, which causes a continuous surface charge increase and eventually the air breakdown. The ESD phenomena have been simultaneously detected and confirmed by a low-dark-current photoelectric detector. Four different steps have been summarized to describe irregular ESD transition processes before their stable state. At the same time, the frequency and efficiency of ESD have been generally regulated and controlled by systematically investigating several key influence factors (contact materials, contact pressure, tilted angle, surface morphology, etc.). This asymmetrical structure has proved TENG as powerful and real-time analytical equipment to explore fundamentals of contact electrification and ESD. Meanwhile, three necessary premises for ESD in TENG can be selectively avoided for the improvement of the stability of TENG. [ABSTRACT FROM AUTHOR]

Electrostatic breakdown leads to the majority of anomalies and failures attributed to spacecraft interactions with the plasma space environment. It is therefore critical to understand how the electrostatic field strength ( $F_{{ESD}} ) of spacecraft materials varies due to environmental conditions, such as duration of applied electric field, rate of field change, history of exposure to high fields, and temperature. We have developed a dual-defect, thermodynamic, mean-field trapping model in terms of recoverable and irrecoverable defect modes to predict probabilities of breakdown. Fits to a variety of measurements of the dependence of F {ESD} of insulating polymers on endurance time, voltage ramp rate, and temperature based on this model yield consistent results. Our experimental results for the prototypical materials, low-density polyethylene and polymer (PI or Kapton HN), suggest that the values of F {ESD} from standard handbooks, or cursory measurements that have been used routinely in the past, substantially overestimate the field required for breakdown in common spacecraft applications, which often apply subcritical fields for very long time periods as charge accumulates. [ABSTRACT FROM PUBLISHER]

In this study, the detecting structures in an embedded CUP wafer, which are called sensors, are investigated through a contactless sensing analysis. These novel sensing structures, which were designed using the ADS 2009 platform and the design rules for the TSMC 0.18-μm CMOS process, were placed under bonding pads. However, signals would still pass through these I/O sensing structures (i.e., ESD devices or circuits) and become coupled up to the pads of the top-layer metal as square, sinusoidal, or ESD pulse waveforms are injected. Through the resulting sensing relationship, we could then judge whether or not the bottom circuit is a good candidate for EMI consideration. Eventually, it was found that during an ESD occurred situation, a strong signal coupling can be sensed by the ESD protection circuits, especially by gate-coupled ESD protection circuitry. [ABSTRACT FROM AUTHOR]

A power-rail electrostatic discharge (ESD) clamp circuit realized with ESD clamp device drawn in the layout style of big field-effect transistor (BigFET), and with parasitic diode of BigFET as a part of ESD-transient detection mechanism, is proposed and verified in a 65-nm 1.2-V CMOS process. Skillfully utilizing the diode-connected MOS transistor as the equivalent large resistor and the parasitic reverse-biased diodes of BigFET as the equivalent capacitors, the new RC-based ESD-transient detection mechanism can be achieved without using an actual resistor and capacitor to significantly reduce the layout area by \sim82%, as compared to the traditional RC-based ESD-transient detection circuit. From the measured results, the new proposed power-rail ESD clamp circuit with body effect of ESD clamp device can perform adjustable holding voltage under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on under fast power-on and transient noise conditions. [ABSTRACT FROM AUTHOR]

The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances. [ABSTRACT FROM AUTHOR]

Abstract: Thickness non-uniformities in electrostatic capacitors and in electroactive polymers – arising from manufacturing processes or electromechanical induced inhomogeneous deformations – may lead to drastic charge and electric field localizations and, ultimately, to an anticipated device failure. Based on a geometric interpretation of the Gauss equation enlightening the effect of the electrode curvature, we obtain an analytic expression of the electric field and of the surface charge density localization for non perfectly planar capacitors with symmetric thickness non-uniformities. The efficiency of the model is exploited by analyzing specific boundary value problems of technological interest. [Copyright &y& Elsevier]

Time evolution of self-heating and current filamentation are discussed in this paper for shallow-trench-isolation (STI)-type drained-enhanced n-channel metal–oxide–semiconductor (DeNMOS) devices. A deeper insight toward regenerative n-p-n action and its impact over various phases of filamentation and the final thermal runaway is presented. A modified STI-type DeNMOS device is proposed in order to achieve an improvement (\sim\!\!\2 \times) in the failure threshold (IT2) and electrostatic discharge (ESD) window (VT2). The performance and filament behavior of the standard device under charge-device-model-like ESD conditions is also presented, which is further compared with the proposed modified device. [ABSTRACT FROM PUBLISHER]

The electrostatic discharge (ESD) characteristics of GaN-based light-emitting diodes (LEDs) with naturally textured p-GaN contact layers grown on c-axis miscut sapphire substrates are studied and demonstrated. Based on the machine model, the device grown on a 0.35 ^\circ miscut sapphire shows the highest ESD tolerance, whereas the device grown on a 0.2^\circ miscut sapphire exhibits the poorest tolerance. It is found that this phenomenon is primarily related to the presence of maximum capacitance Cm values rather than the difference in defect densities between LEDs. The variation in Cm values is caused by the parasitic capacitance effect induced by different p-GaN surface morphologies between the studied devices. This observation gives us a more reliable application in improving the ESD performance based on the device grown on a 0.35^\circ miscut sapphire. [ABSTRACT FROM PUBLISHER]

The authors demonstrate the fabrication of 1 mm 1 mm GaN-based power flip-chip light-emitting diodes (LEDs) with an internal electrostatic discharge (ESD) protection diode on Cu sub-mount. With the internal diode, it was found that forward voltage of the LED increased from 3.22 to 3.38 V while output power decreased from 366.5 to 273.9 mW when under 350 mA current injection due to the reduced light emitting area. It was also found that we can achieve a significantly better ESD robustness by building the internal diode inside the LED chip. Furthermore, It was found that 90% of the LEDs with internal diode survived with an applied reverse ESD surge of 12000 V and 25% of the LEDs can even endure 20000 V reverse ESD stressing. [ABSTRACT FROM AUTHOR]

A nonlinear power distribution network model for characterizing the immunity of integrated circuits (ICs) to electrical fast transients (EFTs) is proposed and validated. The model includes electrostatic discharge (ESD) protection diodes and passive impedances between power domains. Model parameters are based on external measurements using a vector network analyzer and curve tracer. Impedance is measured between pins while the IC is biased and operating, and is used to determine individual elements of the network model. Inclusion of active power-clamp circuitry is also explored. The model is able to successfully predict pin currents and voltages during EFTs on the power pin when the IC is operating or turned off and when the ESD power clamp is either activated or not activated. This model might be used to evaluate the immunity of the IC in a variety of systems and to better understand why failures occur within the IC and how to fix them. [ABSTRACT FROM AUTHOR]

A new on-chip RC-based transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed, which can detect fast electrical transients during the system-level ESD test. A novel on-chip transient-to-digital converter composed of four RC-based transient detection circuits and four different RC filter networks has been successfully designed and verified in a 0.18-μm CMOS process with 3.3-V devices. The output digital thermometer codes of the proposed on-chip transient-to-digital converter correspond to different ESD voltages under system-level ESD tests. The proposed on-chip transient-to-digital converter can be further combined with firmware cooperation to provide an effective solution to solve the system-level ESD protection issue in microelectronic systems equipped with CMOS ICs. [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESD) free bootstrapped BiCMOS inverter circuit is proposed. The proposed driver circuit uses the bootstrapped technique; the transistor base voltage is higher than the supply voltage. The input of circuit is arranged to protect the electrostatic discharge problem, and the output waveform is able to have full swing. The proposed circuit consumes low power with small delay time. The transistors in the circuit operate with high performance and efficiency. [ABSTRACT FROM AUTHOR]

A good representativeness of the test setup used for the qualification of solar arrays is fundamental. We know now that the fiashover current involved in the electrostatic discharge is related with the total dielectric surface neutralized during the electrostatic discharge. This paper presents experiments on samples of different sizes, performed in a large vacuum chamber, JONAS, installed in ONERA/DESP, Toulouse, France. The samples are tested in the inverted voltage gradient configuration obtained with electrons. We observed that secondary arcs obtained on a large sample (i.e., with a long fiashover) had much longer durations than those on a small sample, i.e., the flashover is a critical parameter for secondary arc initiation and sustainment. [ABSTRACT FROM AUTHOR]

The silicon-controlled rectifier (SCR) has been used as an effective on-chip electrostatic discharge (ESD) protection device in CMOS technology due to the highest ESD robustness in nanoscale integrated circuits (ICs). In this study, the SCR realized in a waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance. The waffle layout structure of the SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with a waffle layout structure and its turn-on time has also been investigated in a silicon chip. [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESD) damage to giant magnetoresistive (GMR) heads is investigated using a charged device model tester. The sensor of a GMR head is easily affected by ESD during handling in production. Simulation of the picking procedure reveals that elevating such a small-capacitance device above the work surface increases the potential by up to ten times and the discharge current by up to five times. With 20-V initial potential, which could be applied by the picking tool, the elevation of a 5-pF capacitance by just 10 mm increases the potential to 200 V and the peak discharge current to 578 mA. In the case of a 1-pF capacitor, however, the potential and peak current remained low due to the effect of stray capacitance. In the case of a GMR head with 3.7-pF capacitance, a 5-mm lift reduced the initial potential causing ESD damage from 60 V to less than 40 V. Waveforms of discharge reveal that the GMR head can be designed to reduce the ESD risk. [ABSTRACT FROM AUTHOR]

Various models have evolved to test the sensitivity of electronic devices to electrostatic discharge (ESD), which include the human body model, machine model, and field-induced charged device model. The objective of this paper is to review both the static and dynamic aspects of these models and to analyze the charge and potential control of ESD events. Charge and geometry sensitivity factors are defined for a general two-body problem. The results should provide a better understanding of models that are used to simulate the direct effect of ESD and to provide methods to evaluate the effectiveness of ESD control processes. In particular, the electrostatic implications of small-gap geometries with application to microelectromechanical systems are reviewed. [ABSTRACT FROM AUTHOR]

A method for analyzing electrostatic discharge (ESD) generators and coupling to equipment under test in the frequency domain is proposed. In ESD generators, the pulses are excited by the voltage collapse across relay contacts. The voltage collapse is replaced by one port of a vector network analyer (VNA). All the discrete and structural elements that form the ESD current pulse and the transient fields are excited by the VNA as if they were excited by the voltage collapse. In such a way, the method allows analyzing the current and field-driven linear coupling without having to discharge an ESD generator, eliminating the risk to the circuit and allowing the use of the wider dynamic range of a network analyzer relative to a real-time oscilloscope. The method is applicable to other voltage-collapse-driven tests, such as electrical fast transient, ultrawideband susceptibility testing but requires a linear coupling path. [ABSTRACT FROM AUTHOR]

This paper describes the evaluation of electric and magnetic fields due to electrostatic discharges (ESDs) using an efficient numerical prediction model and measurements obtained with simple field sensors. The numerical prediction model is implemented using software based on the finite integration technique (FIT). The ESD generator is efficiently modeled, and the contact-mode discharge current is well reproduced taking into account the loading effect of the generator. Simple free-space field sensors are effectively used to measure the fields from an ESD event. Suit- able numerical and theoretical characterizations of these sensors are proposed to derive a sensor transfer function that permits the fields to be reconstructed from the measured voltage. The numerical characterization is performed by Microwave Studio (MWS), while the theoretical characterization is based on lumped element circuit models of the sensors. The validation of both the proposed procedures indicates good accuracy up to 2 GHz as required by the International Electrotechnical Commission standard for ESD measurements. [ABSTRACT FROM AUTHOR]

The characteristics of oxide-trapped charges Qot induced by electrostatic discharge high-field current impulse stress, i.e., transmission line pulsing (TLP), were studied. It was observed that for a 3.2-nm-thin oxide, the centroid evolution and the critical density of positive oxide-trapped charges Qot+ to trigger oxide breakdown are about the same between dc and TLP impulse stresses. These results are consistent with the existing models of stress-induced trapping charges and hole-induced oxide breakdown. However, different behaviors of Qot- and centroid were found for 14-nm-thick oxides subjected to different stress tests. TLP impulse stress generates far less amount of negative oxide- trapped charges Qot- than dc stress, and the positive oxide-trapped charges finally dominate over the negative oxide-trapped charges. This impulse stress imposes a high density and transient current on the oxide, which induces traps at the tunneling distance locally. The hotter injected electrons generate more efficient hole trap- pings to provoke breakdown with lower density of oxide-trapped charges in comparison with dc stress test. [ABSTRACT FROM AUTHOR]

Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical experience and know-how. A technology computer-aided design (TCAD) methodology aimed to assist in the design and implementation of robust ESD devices is developed and presented. The methodology provides a systematic and practical means for the evaluation and optimization of ESD devices in a simulation environment. Advanced silicon-controlled-rectifier devices are considered to illustrate the approach, and experimental data measured from these devices are also included in support of the TCAD development. [ABSTRACT FROM AUTHOR]

Abstract: In this study, the effects of background doping concentration (BDC) of a high voltage operating extended drain N-type MOSFET (EDNMOS) device on electrostatic discharge (ESD) protection performances were evaluated. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC. [Copyright &y& Elsevier]

An experimental investigation of indirect electrostatic discharge events for an inline three-body geometry was undertaken. Using conducting cylinders of different sizes to model the test system's conductors, capacitance coefficients were measured, and body potential differences and electric fields were calculated for different geometries of the three floating conductors in close vicinity. The test geometry was chosen to model the approach of the charged human body to an electronic system, which has a neighboring floating conductor; this situation may arise in a manufacturing environment where faulty grounding exists. The parameters studied include body sizes, test geometry, and the relative magnitude and polarity of the charges on the three bodies. An analysis of both first and secondary discharge events is presented and interpreted using a series of charge sensitivity factors. Conditions to support secondary discharges are investigated as a two-body problem. [ABSTRACT FROM AUTHOR]

This paper provides two accurate and efficient models of electrostatic discharge generators which permit to reproduce the discharge current in the contact mode, taking into account the load effect. The first model is based on a circuit approach and is suitable to be implemented in any commercial circuit simulator. The second model is based on the numerical solution of the field equations by using the commercial numerical-code microwave studio based on the finite-integration technique. The validation of the proposed circuit and numerical models is carried out by comparison with measurements. [ABSTRACT FROM AUTHOR]

The detrimental effects of spacecraft charging are well known, particularly when the charging leads to arcing on solar array and, consequently, to permanent power loss. Motivated by these concerns, Alcatel Alenia Space has undertaken several test campaigns to qualify solar array design and to investigate margins. This paper describes the state-of-the-art Alcatel Alenia Space solar array electrostatic discharge laboratory test setup and procedure. The primary discharges are created using a plasma source and negative polarization of the sample rear side. The required power to feed the arc can be delivered by a solar array simulator with low-capacitance power sources. The test sample is fully representative of a flight model. [ABSTRACT FROM AUTHOR]

Through an electrostatic discharge (ESD) damage case study of giant magnetoresistive (GMR) head in shunting process of head gimbal assemblies (HGA), this paper unveils that GMR heads would be damaged by a combination of field-induced voltage on HGA and surrounding trigger event. This investigation further demonstrates that the ESD protection technique, which derives from metal-to-metal contact to GMR terminals and thus focuses on eliminating metal-to-metal contact to GMR terminals, is not sufficient to prevent ESD. The electromagnetic interference caused by nearby trigger event needs to be noted also in the ESD control. [ABSTRACT FROM AUTHOR]

Abstract: The aim of this work is the investigation of the transient magnetic field radiating by two different commercial generators of electrostatic discharges. Measurements of the magnetic field generated by contact electrostatic discharges have been conducted a few centimeters away from the discharge point. In this paper the current transducer, which is used for the measurement of the discharge current is not mounted on a grounded metal plate, but instead it is on an insulating material. With this aberration to the Standard a closer simulation to the magnetic field produced by the electrostatic discharge generators on the equipment under test is obtained. It is proved by the measurements that each generator produces a different transient magnetic field, which results in a different way on the equipment that is tested. Also, comparisons of the magnetic field between the two generators and useful conclusions for the decrease of the magnetic field are presented. [Copyright &y& Elsevier]

An experimental investigation of indirect electrostatic discharge (ESD) events for an inline three-body geometry was undertaken. Using conducting cylinders of different sizes to model the test system's conductors, capacitance coefficients were measured; body potential differences and electric fields in air gaps were calculated for different geometries of the three floating conductors in close proximity. The test geometry was chosen to model the approach of the charged human body to an electronic system that has a neighboring floating conductor. The possibility of primary and secondary discharges was studied for various body sizes and test geometries. The results of this work provide a better understanding of the fundamental principles involved in the ESD event involving three bodies separated by small gaps. The methodology may have application in analyzing ESD events in small-gap structures including microelectromechanical systems (MEMSs). [ABSTRACT FROM AUTHOR]

Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-μm CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 if parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 53 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7 ± 1 dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9± 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and high ESD robustness of the DA can be successfully codesigned to meet the application specifications. [ABSTRACT FROM AUTHOR]

The capacitive load, from the large electrostatic discharge (ESD) protection device for high ESD robustness, has an adverse effect on the performance of broad-band RF circuits due to impedance mismatch and bandwidth degradation. The conventional distributed ESD protection scheme using equal four-stage ESD protection can achieve a better impedance match, but degrade the ESD performance. A new distributed ESD protection structure is proposed to achieve both good ESD robustness and RF performance. The proposed ESD protection circuit is constructed by arranging ESD protection stages with decreasing device size, called as decreasing-size distributed electrostatic discharge (DS-DESD) protection scheme, which is beneficial to the ESD level. The new proposed DS-DESD protection scheme with a total capacitance of 200 IF from the ESD diodes has been successfully verified in a 0.25-μm CMOS process to sustain a human-body-model ESD level of greater than 8 kV. [ABSTRACT FROM AUTHOR]

Electrothermal characteristics of strained-Si MOSFETs, operating in the high-current regime have been studied using device simulation. The phonon mean-free-path of strained-Si devices in the presence of high electric fields is determined based on fullband Monte Carlo device simulation. Strained-Si: nMOS devices have higher: bipolar current gain and impact ionization rates compared to bulk-Si nMOS devices due to the smaller energy bandgap and longer phonon mean-free-path. Even though strained-Si devices have self-heating problems due to the lower thermal conductivity of the buried SiGe layer, the devices can be used beneficially for electrostatic discharge protection devices to achieve lower holding voltage(Vh) and higher second breakdown triggering current (It2), compared to those of bulk-Si devices, owing to the high bipolar current gain and current uniformity. [ABSTRACT FROM AUTHOR]

The electrostatic discharge (ESD) characteristics of a three-body problem comprised of a charged human body approaching an electronic system with an interposed guard electrode are investigated. Capacitance coefficients were measured; for an assumed charge on the human body, body potentials were calculated and the relative effectiveness of the guard electrode to control the ESD event evaluated. The results indicate that the concept of an active guard electrode can reduce the likelihood of an ESD event. [Copyright &y& Elsevier]

Electrostatic discharge (ESD) pulses comprise frequencies up to approximately 1 GHz. These pulses have been reported to be associated with health effects. Human exposure standards also set limits on the specific absorption (SA) in tissue. Electric fields and SA are computed using the finite-difference time-domain method and heterogeneous model of the human body. The avenge SA values in all organs and tissues are below the limits in the IEEE Standard for typical and realistically high ESD pulses. [ABSTRACT FROM AUTHOR]

A systematic and comprehensive procedure for understanding electrostatic discharge and electrical breakdown at the head-disk interface in a bard disk drive is described. First, the resistance, breakdown and field emission behavior for the individual and combined carbon overcoat films on the disk and slider was determined through current versus voltage testing. Second, different electrostatic mechanisms that can produce a voltage difference between the disk and slider or read transducer were studied. Results are explained in terms of the relative lime constants for the voltage on the head and disk. It is concluded that a potential difference between the disk and recording head as little as 2 V can result in electrical breakdown damage at the head-disk interface. [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESD) robustness of LDMOS (laterally diffused MOS) devices is found to be highly dependent on the type of ESD stress. In particular, the device's ESD robustness does not scale with the device width, and this condition is substantially aggravated during the International Electrotechnical Commission (IEC) 61000-4-2 stress condition. IEC 61000-4-2 is a system-level ESD standard increasingly being adopted in the industry for ESD robustness assessment at the integrated circuit level. A comprehensive evaluation under the IEC 61000-4-2 stress impacting precision circuit designs is introduced in this letter for variable width LDMOS devices fabricated in a 0.18-\mu\m bipolar-CMOS-DMOS process for 40-V mixed-signal applications. [ABSTRACT FROM PUBLISHER]

Low-voltage-triggering silicon-controlled rectifier (LVTSCR) having a gate structure can offer a low trigger voltage in electrostatic discharge (ESD) applications. To avoid the threat of latch-up, the lateral width of LVTSCR is often stretched to obtain a relatively high holding voltage. The resulting lateral dimension increase, however, enlarges the size of LVTSCR. In this letter, a new method to increase the holding voltage of LVTSCR is developed. It is based on adding a floating-n-well region in the LVTSCR and can increase the holding voltage without requiring additional layout area. Furthermore, with this new LVTSCR, it is possible to implement an ESD protection operation within a very small window of 1 V. [ABSTRACT FROM AUTHOR]

A novel capacitance coupling complementary dual-direction silicon-controlled rectifier (SCR) (CCCDSCR) for high-voltage electrostatic discharge protection is proposed and verified in 0.5- \mu\m BCD process. The trigger voltage of CCCDSCR can be adjusted by coupling capacitance to meet different protection requirements. Compared with traditional lateral double-diffusion NMOS, LDSCR, stacked field-oxide device, and stacked low-voltage-triggering SCR devices, the CCCDSCR has appropriate low trigger voltage of 27.3 V, high holding voltage of 24.3 V, and highest figure of merit (FOM) according to our defined FOM. [ABSTRACT FROM PUBLISHER]

Passing voltage levels measured from the human metal model tester are correlated with the failure current levels obtained from the transmission line pulsing (TLP) tester for electrostatic discharge protection devices fabricated in 0.18- and 0.35-\mu\m MOS technologies. Various relevant TLP parameters, including the holding voltage and on -state resistance, are accounted for in the improved correlation formula developed in this study. [ABSTRACT FROM PUBLISHER]

Latchup immunity is a challenging issue for the design of power supply clamps used in high-voltage electrostatic discharge (ESD) protection applications. While silicon-controlled rectifiers (SCRs) are highly robust ESD devices, they are traditionally not suited for high-voltage ESD due to their inherent low holding voltage and, thus, vulnerability to latchup. In this letter, a novel SCR stacking structure with an extremely high holding voltage, very small snapback, and acceptable failure current has been developed. The new and existing high holding voltage ESD devices are also compared to demonstrate the advancement of this work. [ABSTRACT FROM AUTHOR]

The electrical breakdown behavior and damage mechanisms for a recording head flying over a charged hard disk with and without an asperity is studied. It was found that the breakdown voltage flying over a 30-nm-high asperity was as low as 1.4 V, a 50% reduction compared with a smooth disk without the asperity. Also, the read sensor was easily damaged physically and magnetically when breakdown occurred while flying over the asperity. It is concluded that the inclusion of asperities in electrical breakdown testing is critically important in determining the lowest breakdown voltage and assessing the likelihood of damage to the sensor. [ABSTRACT FROM AUTHOR]

A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymmetrical I-V characteristics for ESD (electrostatic discharge) applications is presented. The device allows for the dual-polarity conduction with the proper selection of blocking junction configurations. This design enables high-level ESD protections for various mixed-signal integrated circuits operating under a wide range of symmetrical and asymmetrical bias conditions. [ABSTRACT FROM AUTHOR]

We demonstrate a new electrostatic discharge (ESD) protection structure for high-speed GaAs RF ICs. The structure is composed of small diodes and large transistors using an InGaP heterojunction bipolar transistor (HBT) technology. Its loading effect and its robustness are evaluated experimentally. The impedance of the new structure at OFF state, represented with an equivalent shunt capacitance and an equivalent shunt resistance, are 0.22 pF and 500 Ω at 10 GHz. The structure can withstand +2700-V and -2900-V human body model ESD pulses. It can clamp voltage more effectively than the conventional diode-based ESD structure. The new structure can be used to protect 10 Gb/s input/output pins of high-speed RF ICs against ESD. [ABSTRACT FROM AUTHOR]

Silicon-controlled rectifiers (SCRs) are frequently used to build on-chip electrostatic discharge (ESD) protection structures, but SCRs are not sufficiently robust to meet a wide range of ESD requirements in various integrated circuits. In this paper, a novel and robust SCR-based device called the HHLVTSCR is presented. It is demonstrated that HHLVTSCR can exhibit various characteristics useful for ESD solutions. An example is also included to illustrate how HHVLTSCRs can be used to provide ESD protection to a practical application. [ABSTRACT FROM AUTHOR]

The double snapback characteristic in the high voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit. [ABSTRACT FROM AUTHOR]