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The objective of this paper is to provide a framework by which jitter, in the output signals of a test-head board in an automatic test equipment (ATE), can be measured. In this paper, jitter phenomena caused by radiated electromagnetic interference (EMI) noise are considered. EMI noise is mainly present in the test head of an ATE as result of the activity of the dc-dc converters. An analysis has been pursued to establish the areas of the test-head board that are most sensitive to EMI noise. The most sensitive part of the test-head board has been found to occur in the loop filter of the phase-locked loop (PLL) that is used to obtain a high-frequency clock for the timing generator (TG). Different H-fields are then externally applied to the loop filter to verify the behavior of the output signal in terms of rms jitter. A frequency-domain methodology has been employed for the rms-jitter measurements. The rms-jitter variation for the radiated EMI magnitude and frequency has been characterized. Also, the orientation of the external H-field source has been investigated with respect to the target board and its effects on the measured rms jitter. For measuring the jitter, an interface circuitry has been designed on an adapter board to circumvent ground noise and connectivity problems arising from the test-head environment.

This paper deals with multisite testing of VLSI chips in a manufacturing environment. Multisite testing is analyzed and evaluated using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, fault coverage, and touchdown time for the head). The presence of idle time periods and their impact on the multisite test time is analyzed in depth. Two hybrid testing scenarios which combine built-in self-test (BIST) and automatic test equipment (ATE) are proposed and analytical models are provided to establish the corresponding multisite test time. It is shown that a hybrid approach based on screening chips through a BIST stage improves the performance of multisite test and allows a better utilization of channels in the head of an ATE.

This paper analyzes an environment which utilizes built-in self-test (BIST) and automatic test equipment (ATE), and presents closed-form expressions for fault coverage as a function of the number of BIST and ATE test vectors. This requires incorporating the time to switch from BIST to ATE (referred to as switchover time), and utilizing ATE generated vectors to finally achieve the desired level of fault coverage. For this environment, we model fault coverage as a function of the testability of the circuit under test and the numbers of vectors which are supplied by the BIST circuitry and the ATE. A novel approach is proposed; this approach is initially based on fault simulation using a small set of random vectors; an estimate of the so-called detection profile of the circuit under test is established as the basis of the test model. This analytical model effectively relates the testable features of the circuit under test to detection using both BIST and ATE as related testing processes.

Testing multimodule systems presents several challenges, particularly when systems use submicron technology. The authors propose strategies to diagnose interconnect faults in bus-structured systems using several models. We propose several methods and strategies for a diagnosis using different fault models, including those applicable to submicron technology. Besides defining new features, such as the logical extent of faults, we also propose a reduction strategy that permits 100% fault detection and identification (including fault location).

This paper presents a new approach to detecting faults in interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults with a weighted graph, which is then analyzed to appropriately compact the tests and schedule their execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weight heuristics from the weighted adjacency graph. Simulation has been performed for unweighted and weighted fault models. Results on random interconnects and the local interconnect of a commercially available field-programmable gate array are provided. The advantage of the proposed approach is that, on average, early detection of faults is possible using significantly fewer tests than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still having a small number of vectors.

We give three new algorithms to compute tests for faults in the interconnects of random access memories (RAM) using only read and write operations. Diagnosis of address line faults is the most difficult step. Our Adaptive Diagnosis Algorithm (ADA) considers each address line separately. Single line faults are easy to diagnose, so the objective is to ascertain which address lines are free of faults, thereby pruning impossible multi-line faults. Our Consecutive Diagnosis Algorithm (CDA) uses a more complicated and lengthier test sequence. However, with CDA, interpreting the test results is easier and the diagnostic resolution is superior. Our third algorithm, Adaptive Diagnosis Algorithm with Repair (ADAR), relies upon additional testing after repair in order to diagnose more faults than would otherwise be possible. ADAR has three test stages with two repair stages between them.

An accurate yield evaluation is essential in selecting redundancy allocation and testing strategies for memories. Yield evaluation can resolve the many issues revolving around cost-effective built-in self-test (BIST) and automatic test equipment (ATE)-based solutions for a higher test transparency. In this paper, two yield-calculation methodologies for SRAM arrays are proposed. General yield expressions for VLSI chips are initially presented. The regular and repetitive structure of an SRAM array is exploited, and substantial yield improvements can be achieved by the introduction of redundancy. Two repair yield-evaluation methods for one-dimensional redundant memory arrays are introduced and compared for ATE application. The first method is based on the sum of the probabilities of all repairable fault patterns; the second method is based on Markov modeling. Using industrial data, it is shown that these methods are applicable to ATE usage under different conditions of defect rate in the possible defects. Different features of the proposed methods are discussed

The objective of this paper is to provide a framework by which jitter phenomena, which are encountered at the output signals of a head board in an automatic test equipment (ATE), can be studied. In this paper, the jitter refers to the one caused by radiated electromagnetic interference (EMI) noise, which is present in the head of all ATE due to DC-DC converter activity. An initial analysis of the areas of the head board most sensitive to EMI noise has been made. It identifies a sensitive part in the loop filler of a phase locked loop which is used to obtain a high frequency clock for the timing generator. Different H-fields are then applied externally at the loop filter to verify the behavior of the output signal of the head board in terms of RMS jitter. As for RMS jitter measurements, a frequency domain methodology has been employed. A trend for RMS jitter variation with respect to radiated EMI magnitude as well as frequency has been obtained. Also the orientation of the external H-field source with respect to the target board and its effects on the measured RMS jitter has been investigated. For measuring the RMS value, a proper circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment.

This paper presents theoretical yet practical methodologies to model, assure and optimize the reliability of clockless wave pipeline. Clockless wave pipeline is a cutting-edge and innovative technology as an alternative to traditional pipeline, and a promising computing model towards ultra-high throughput and speed. The basic computational components of such clockless wave pipeline are data waves in association with request signals and switches. The key to the success of clockless wave pipeline is how to coordinate and ensure the processing of datawaves throughout the pipeline in association with the request signals without relying on any intermediate access points under clocked-control. Due to the complication of clockless operations, an efficient and effective method to model and analyze the confidence level (referred to as reliability or yield) of clockless operations of wave pipeline is exigently demanded, but has not yet been adequately addressed, in an integrated level such as datawaves in association with request signals, leaving this as a challenge. In this regard, out-of-orchestration between datawaves and request signals, referred to as datawave fault, is the major concern in assuring and optimizing the reliability of the system. This paper specifically addresses and resolves: extensive and practical clockless-induced datawave-fault modeling; assurance and optimization; clockless-oriented fault tolerant design methods. The proposed methods will establish a sound and adequate theoretical foundation for development of innovative yet practical test/diagnosis/fault-tolerant design methods in early design stage of clockless wave pipeline.

This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (OUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, coverage and touchdown time for the head). Two scenarios which permit immediate and delayed replacements, are considered and analytical models are given to establish the multisite test time of an ATE. A hybrid BIST and ATE approach is also analyzed to improve the performance of a multisite test environment and to better utilize the channels in the head of the tester.

Recent research on modeling timing jitter has raised a requirement for a predictable, high magnitude, uniform, and wide bandwidth H-field. In this paper, a novel H-field generator design methodology is proposed. It consists of a single layer air core solenoid and a digital power switch driver that takes advantage of low power, wide bandwidth, and big current-driven capability. With input overdrive voltage, the digital switch can drive rail-to-rail voltage with output current up to 16 A and power bandwidth more than 3 MHz. This paper demonstrates a novel solenoid driver circuit to generate an accurate H-field by comparing digital and analog approaches and comparing the experimental data with the theoretical data.

Advances in spaceborne vehicular technology have made possible the long-life duration of the mission in harsh cosmic environments. Reliability and data integrity are commonly emphasized requirements of spaceborne solid-state mass storage systems, because faults due to the harsh cosmic environments - such as extreme radiation - can be experienced throughout the mission. Acceptable dependability for these instruments have been achieved by using redundancy and repair. Reconfiguration (repair) of memory arrays using spare memory lines is the most common technique for reliability enhancement of memories with faults. Faulty cells in memory arrays are known to show spatial locality. This physical phenomenon is referred to as fault clustering. This paper initially investigates a quadrat-based fault model for memory arrays under clustered faults to establish a sound foundation of measurement. Then, long-life dependability of a fault-tolerant spaceborne memory system with hierarchical active redundancy, which consists of spare columns in each memory module and redundant memory modules, is measured in terms of reliability (i.e., the conditional probability that the system performs correctly throughout the mission) and mean-time-to-failure (MTTF i.e., the expected time that a system will operate before it fails).

Performance and reliability are two of the most crucial issues in today's high-performance instrumentation and measurement systems. Instrumentation and measurement systems have found and enjoyed their performance enhancement through parallel and distributed processing. High speed and density Multistage Interconnection Networks (MINs) are widely-used subsystems of parallel processing and communication systems. New performance models are proposed to evaluate the fault tolerant MIN in this paper, thereby establishing a sound foundation for assuring the performance and reliability of fault tolerant MINs with high confidence level during parallel instrumentation. A concurrent fault detection and recovery scheme for MINs is introduced to enable a generic approach to fault tolerance by rerouting over the redundant interconnection links. A switch architecture to realize the concurrent testing and diagnosis is shown. The proposed performance models are developed and used to evaluate the compound effect of the fault tolerant operations such as testing, diagnosis and recovery on the throughput and delay. Results are shown on single transient and permanent stuck-at fault on links and storage units in switching elements. it is shown that the performance degradation for the overhead due to the fault tolerance is quite graceful while the performance degradation without fault recovery is unacceptable.

This paper presents a novel approach for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Different testing objectives (detection and maximal diagnosis) are considered. An extensive analysis of the faults is pursued to characterize their impact on the BCMRS as well as on the test operations (such as WRITE and READ).

We give a comprehensive model of interconnect testing in boundary scan architectures. This includes two fault categories: driver faults (stuck-at, stuck-driving, and stuck-not-driving (equivalent to stuck-open)) and net faults (shorts). We permit short faults to exhibit zero-dominance (wired-AND), one-dominance (wired-OR), and net-dominance. We split the built-in self-test hardware into two components: a control pattern test generator (CTPG) and a data pattern test generator (DTPG). For the DTPG, we use a complementary counting sequence, which is an instance of a maximal independent test set. We give novel designs for CTPGs that guarantee 100% fault coverage with low hardware overhead and time complexity. We give a general and complete procedure to implement the CTPGs. Using a linear feedback shift register as a one-shot counter to cover all control cells in the boundary scan, we ensure that no two control cells of one net are assigned to a single register; this avoids circuit damage when testing.

We present a novel approach for detecting faults in tristate system environments-e.g., in multiple board systems. These environments are made of an interconnect and drivers/receivers with tristate features. We present a comprehensive fault model that includes faults in terminals (drivers/receivers) and nets. Under this fault model, physical faults (stuck-at and short), as well as functional faults (dominance, permanently enabled or permanently disabled driver modes), are taken into account. We show that, for a single net with L drivers, 2L tests are necessary and sufficient for fault detection. This is independent of the number of receivers. We extend this result to a system environment with N nets and where K is the maximal number of drivers for a net. Under the proposed fault model, any number of faults of any type can be detected in a system environment using any types that can be detected in a system environment using max (2K, P) tests, where P is the minimal integer that satisfies C/sub /2//sup P//spl ges/N. If only the traditional (wired-AND or wired-OR) model is assumed, then the test set required for fault detection can be further reduced. We provide simulation results and show that the proposed approach outperforms previous methods found in the technical literature.

The average new chip design already exceeds two million devices. Companies are racing to produce innovative systems-on-a-chip (SoC). Economic exigencies are mandating the re-use of core designs. These trends have led to new research concerns in SoC testing, SoC yield prediction, core interfacing, and intellectual property (IP) protection. In this work, we address design decisions associated with embedded cores that have defect-tolerant properties. Specifically, we address whether knowledge about the remainder of the chip would result in different core design decisions pertaining to yield.

This paper presents new approaches for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short, open and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Detection and maximal diagnosis are considered under a restricted fault model (short faults only) as well as a general fault model (all types of faults).

A second-order state space load model was developed and adapted for parameter identification. A weighted least squares identification process was developed to identify model parameters from measurements of load current response due to changes in input voltage. An induction motor model response was used to provide measured input-output load response. The state space load model was implemented in a typical power system stability program. The application of the state space load model to transient stability studies demonstrates that it can more accurately reflect actual load response than conventional stability load models. The state space load model is shown to adequately model the dynamics of power system composite bus load.

This paper is one of a series presented on behalf of the Systems Operations Subcommittee with the intent of focusing industry attention on current problems faced by electric utilities in the operation of its bulk power system. Four short note reports are presented which direct attention to problem areas being faced by utilities in regard to non-utility generation systems. Each report focuses on different aspects of the nonutility generation problem. Reports which are included address generation and fuel, transmission, distribution, and Energy Management and Control Systems.