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Through-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process to prevent stacking yield loss. Thus, the development of effective prebond testing techniques becomes of great importance. In this direction, recent research effort has been devoted to the development of two main prebond techniques: 1) prebond probing and 2) built-in self-test (BIST) techniques. The prebond probing poses economic and technological challenges, whereas current BIST proposals have disadvantages for certain solutions. Hence, there is still a need for an effective methodology in terms of fault coverage, area overhead, and test time. This paper proposes a BIST technique based on a simple unbalanced circuit comparing the behavior of two TSVs. Electrical simulation results show the viability of the proposal to detect weak defects, i.e., resistive opens and resistive bridges, adding reasonable area overhead in a short-test application time. Furthermore, an experimental design is built on a 65-nm technology, where resistive open defects are intentionally injected. Automated test equipment measurements confirm the simulation results.

Microelectromechanical systems fabrication and packaging may induce parametric defects which have to be efficiently diagnosed to improve fabrication yield and device reliability. In this work, the possibilities of diagnosing single parametric defects in dual axis IC accelerometers are explored. The proposed method is a reuse of a mixed-signal diagnosis strategy based on Lissajous compositions. It consists of a dynamic correlation of the two orthogonal output signals of the device. This leads to a Lissajous trace which is able to manifest parametric deviations. Several device parameters have been studied and characterized under different deviation levels. The definition of a metric and the evaluation of its diagnosis efficiency is used to optimize the diagnosis procedure against noisy measurements. The method has been experimentally applied to diagnose the misalignment degree in a commercial dual axis accelerometer. The Lissajous characterization of the defect is illustrated and experimental results are reported. Misalignment diagnosis results show the viability of the proposal.

Accurate diagnosis of open defects is key to identifying process problems and achieving fast yield improvement. Current diagnosis methodologies for interconnect full open defects have demonstrated their efficiency, assuming that the defective line voltage is mainly determined by neighboring lines and downstream transistor parasitic capacitances. However, the continuous reduction of oxide thickness with every technology node increases gate leakage current significantly, even for high-k dielectrics. In this context, in nanometer CMOS technologies, the defective line cannot be assumed to be electrically isolated because of the impact of gate leakage currents, which may invalidate diagnosis results provided by present methodologies. In this paper, a new methodology is proposed to diagnose interconnect full open defects under the influence of gate leakage currents in CMOS technologies. To the authors' knowledge, such influence has not been previously considered by any of the existing methodologies. Simulation and experimental results demonstrate the proposal efficiency.

Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information that correlates with circuit performances. In this work, a multiple specification band guarding technique is proposed as a method to achieve a test target of misclassified circuits. The acceptance/rejection test regions are encoded using octrees in the measurement space, where the band guarding factors precisely tune the test decision boundary according to the required test yield targets. The generated octree data structure serves to cluster the forthcoming circuits in the production testing phase by solely relying on indirect measurements. The combined use of octree based encoding and multiple specification band guarding makes the testing procedure fast, efficient and highly tunable. The proposed band guarding methodology has been applied to test a band-pass Butterworth filter under parametric variations. Promising simulation results are reported showing remarkable improvements when the multiple specification band guarding criterion is used.

The development of accurate diagnosis methodologies is important to identify process problems and achieve fast yield improvement. As open defects are becoming dominant in some CMOS technologies, their accurate diagnosis is key to improving the quality of new very large-scale integrated circuits. Widely used interconnect full open diagnosis procedures are based on the assumption that neighboring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, where the influence of transistor capacitances is significant. This paper presents a diagnosis methodology for interconnect full open defects which considers and models the impact of transistor parasitic capacitances on the defective node accurately. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behavior. Diagnosis results for real defective devices from different technology nodes are also provided.

An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the behavior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The occurrence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are analyzed and the defective logic response of downstream gates after reaching the steady state is predicted. Experimental evidence of this behavior is presented for circuits belonging to a 180 nm and a 65 nm CMOS technologies. Technology trends show that the impact of gate leakage currents is expected to increase in future technologies.

An accurate electrical fault characterization is required for the correct diagnosis and localization of CMOS interconnect defects. It has been traditionally accepted that a resistive open defect located at the beginning of an interconnecting line causes the maximum possible delay. The first-order approximation is sufficient to model the behaviour of high resistive opens. However, in this paper it is shown that low resistive opens do not follow this behaviour. In these cases, a second-order model is required for a more precise prediction of their defective behaviour, since the maximum delay is obtained for an intermediate location, which depends on the relationship between the open resistance, the on-resistance of the transistor network driving the defective net, the parasitic capacitances and the threshold voltage of the transistors driven by the defective net. For that purpose, an experimental circuit has been designed and fabricated where open defects have been intentionally added in a set of interconnect CMOS lines. Both simulation and experimental results on defective interconnect lines show maximum delays for opens located at intermediate positions provided that the resistance of the open is on the order of the on-resistance of the driving transistor network.

The CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. For this reason, alternate solutions are being proposed in literature, to possibly replace charge based memories. One of the most promising of these solutions is the spin-transfer-torque magnetic random access memory (STT-MRAM). To evaluate the viability of such solution, one must understand how it behaves under the effect of the various reliability degradation factors. In this paper we propose a methodology which allows for fast reliability evaluation of an STT-MRAM cell under process, voltage, and temperature variations. Our proposed method allows for a sensitivity analysis which will show the designer/test engineer which is the main reliability concern of a certain design. The method is general, and it can be applied to any memory design.

Testing mixed-signal circuits is a challenging task requiring high amounts of human and technical resources. To overcome these drawbacks, indirect testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure CUT information. In this work, the acceptance/rejection regions are encoded using octrees with arbitrary precision regardless of the complexity of the boundary separating these regions. The strategy relies on two phases: (1) A statistical training phase generates the circuit samples to encode the acceptance/rejection regions using octrees. (2) The testing phase corresponds to the actual production testing of the fabricated ICs. The first phase is performed only once and requires sufficient samples of each pass/fail region to generate the octree under realistic CUT variations. The second phase is fast and only requires to evaluate the octree using the measures of the tested IC. In order to illustrate the proposal, the method has been applied to test a band-pass Biquad filter. Successful simulation results are reported showing considerable advantages in terms of test application time.

Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.

Testing mixed-signal circuits is a difficult task due to defect modeling challenges, observability and controllability restrictions and ATE bandwidth limitations. In this paper, the X-Y Zoning test of a Biquad filter is addressed to select the optimal excitation frequency and the best partition of the X-Y plane. Thus we obtain the best sensitivity of the BIST scheme to parametric shifts of the parameters defining the filter. The study has been particularized to shifts in the natural frequency f0 of the Biquad filter. Analytical results on the best input as well as the best partition of the observed X-Y Lissajous plots are obtained. Extensive MATLAB simulations validate the proposal, which has also been validated experimentally. For these experiments, multiple implementations of the Biquad with nominal and shifted parameters have been performed using a commercial Field Programmable Analog Array (FPAA). The experimental measures show good correlation with the analytical expressions and the simulations performed, and validate the proposed testing methodology.

Test power requirements for complex components are becoming stringent. The purpose of this paper is to reuse a recently proposed RT (Register Transfer) Level test preparation methodology to drive innovative Low-Energy (LE)/Low-Power (LP) BIST solutions for digital SoC (System on a Chip) embedded cores. RTL test generation is carried out through the definition of a reduced set of partially specified input vectors (masks), leading to a high correlation between multiple detection of RTL faults and single detection of likely physical defects. The methodology is referred as masked-based BIST, or m-BIST. BIST quality is evaluated considering three attributes: test effectiveness (TE), test length (TL) and test power (TP). LE BIST sessions are defined as short test sequences leading to high values of RT-level IFMB metrics and low-level Defects Coverage (DC). The energy and power of the BIST sessions, with and without mask forcing, is computed. It is shown that, by forcing vectors with the RTL masks, short BIST sessions, with low energy and with a comparable (or smaller) average power consumption, as compared to pseudo-random test, are derived. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and modules of the CMUDSP and TORCH ITC'99 benchmark circuits.

Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and may undergo defects during the fabrication process and also during their life time. The detection of defective TSVs in the earliest process step is of major concern. For this reason, testing TSVs is usually done at different stages of the fabrication process. In fact, effective pre-bond testing is a key factor to prevent stacking yield loss. Extensive research effort has been devoted to develop efficient pre-bond techniques. In this direction, two main approaches have been explored: pre-bond probing and built-in self test (BIST) techniques. Pre-bond probing is challenging since TSVs are too small for standard test probes and the number of probe pads for testing is not affordable. Present BIST proposals have some disadvantages depending on the particular solution considered, namely: the detection of certain types of defects solely, inability to detect weak defects, large area overhead and long test application time. In this context, this work proposes a simple solution, adding low area overhead and fast application test procedure. Simulation results confirm the proposal viability.

Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent failure mechanism affecting TSVs. Although there is considerable research effort dedicated to improve TSVs testing, no much attention has been paid to weak defects, especially to weak open defects (resistive opens) causing small delays. In this work, a testing strategy is proposed to detect small delay defects by means of a post-bond oscillation test. Variations in the Duty Cycle of transmitted signals after unbalanced logic gates are shown to detect weak open defects in TSVs. HSPICE simulations including process parameter variations show the effectiveness of the method in the detection of weak open defects above 1 kO.

Opens in interconnection paths disconnect the driven gate(s) from the driving gate. Detectability conditions to test full opens in interconnections are investigated. It has been found that the detectability of this defect depends strongly on the signals at the driving gate and coupling lines. Three possible situations are analyzed. The first is when there is full controllability of both the signal driving the open and the signal(s) at the coupling line(s). Then, the cases of partial and low controllability of the signals are analyzed. Conditions for reliable detection of this defect by logic and IDDQ testing have been determined. In addition, it has been found that the detectability of interconnection opens depends on the metal level where the signals are laid-out. Routing design for testability techniques are recommended for some interconnection opens non detectable by either a stuck-at based or IDDQ testing. Experimental data on intentionally designed defective circuit is presented.

The purpose of this paper is to analyze an optimization method to improve the testability of structural and parametric faults in analog circuits. The approach consists of finding an optimum sub-set of tests which maximizes the fault coverage with minimum cost. The method is based on covering a discrete set of intervals by taking advantage of strategies effectively used in digital synthesis. A simple application example is given to illustrate the proposal by studying the fault coverage obtained using different test sets on the ITC'97 benchmark op-amp.

The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. A technique to test open defects producing data retention faults is proposed. An initial condition is forced during the writing phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (I_DDQ) increases and the fault can be detected sensing the I_DDQ. The testability regions for the defective memory cell were determined using state diagrams. Conditions to obtain the optimum vector have been stated. A DFT circuitry has been proposed. The cost of the proposed approach in terms of area, test time, and performance degradation is analyzed.

A unified approach to tackle the characterization of the floating gate defect in analog and mixed-signal circuits is introduced. An electrical level model of the defective circuit is proposed extending previous models used effectively in the digital domain. The poly-bulk, poly-well, poly-power rail and metal-poly capacitances are significant parameters in determining the behavior of the floating gate transistor. The model is used to analyze the feasibility of testing a simple analog cell with the floating gate defects through the observation of the quiescent current consumption and the dynamic behavior.

Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.

The behavior of basic CMOS combinational gates in the presence of a floating gate defect is characterized in order to investigate its detectability by IDDQ . The defect is modeled at the circuit level by the poly-bulk and metal-poly capacitances, which determine the quiescent power supply current consumption (IDDQ ) of the defective circuit. The testing implications on the type of defective gate are studied. Experimental measures have been made on basic CMOS combinational modules designed with intentional floating gate defects. A good agreement is observed between the simulation results and the experimental data. A conventional ATPG for stuck-at faults is used to obtain the required exciting vector to test the floating gate defects by IDDQ Testing.

built-in self test integrated circuit testing three-dimensional integrated circuits Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects

The goal of this work is to analyze the performance of PN junction-based Built-in Current Sensors (BICS) for IDDQ testing. Two types of BIC Sensors are analyzed: one based on a simple PN junction as the sensing element (DBICS), and the other based on a lateral BJT (PBICS). The sensitivity, speed and performance of the BICS are studied by showing their dependence on circuit parameters. Design constraints of such sensors in order to achieve performance criteria on CUT and BICS are analyzed. The dynamic analysis of the BICS is compared with experimental results when the PN junction BICS are used on a CMOS circuit.

Current testing of dynamic CMOS integrated circuits with single phase clock is investigated. The analysis is performed on a single phase stage dynamic module in the presence of internal bridging defects of low resistance. These defects produce intermediate voltage levels which cause difficulties to the logic testing methods based on voltage level comparison. It is shown that current testing may be an effective complement to the usual logic methods. Theoretical bounds on the coverage of single internal bridges obtainable by current testing are given.

Designers must target realistic faults if they desire high-quality test and diagnosis of CMOS circuits. The authors propose a strategy for generating high-quality I/sub DDQ/ test patterns for bridging faults. They use a standard ATPG tool for stuck-at faults that adapts to target bridging faults via I/sub DDQ/ testing. The authors discuss I/sub DDQ/ test set diagnosis capability and specifically generated vectors that can improve diagnosability, and provide test and diagnosis results for benchmark circuits.

Test structures are key elements to characterise and identify the main contributors to yield loss in wiring structures. Among such monitors, comb–meander–comb structures have been widely used owing to their simplicity and reduced number of pads. With continuous scaling of dimensions and use of copper in interconnections, open defects has arisen as the most common defect affecting the interconnection, focusing thus on an important part of the research effort. In fact, present electrical methodologies are able to detect, localise and predict the resistance of weak (resistive) opens. However, such methodologies are not able to locate full opens. This lack of information may be useful for faster ramp-up and yield improvement, among others. In this context, a simple electrical methodology to predict the location of full opens in comb–meander–comb structures is presented. Experimental measurements carried out in a 65 nm technology die corroborate the feasibility of the approach.

The development of accurate diagnosis methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes a key factor. Widely used interconnect full open diagnosis procedures are based on the assumption that neighbouring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, when the influence of transistor capacitances becomes important. This work presents a diagnosis methodology for interconnect full open defects where the impact of transistor parasitic capacitances is included. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behaviour. Diagnosis results for real defective devices from different technology nodes are presented.

Increased die-to-die and on-die variations in scaled technologies can lead to parametric failures (Read/Write/Access) in embedded SRAMs. Conventionally, SRAM bit-cell failure analysis is based on the Static Noise Margin (SNM), a metric that leads to conservative estimate of design yield. In this paper we present a method of dynamic noise margin (DNM) estimation based on the modeling technique developed in [9] that can efficiently estimate failures in bit-cells under parameter variations. The proposed DNM estimation method is fast, and can accurately estimate the SRAM yield. Monte Carlo simulation results show that the proposed DNM closely matches the results from SPICE analysis.

Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.

A new design of a BIC sensor for current testing static CMOS circuits is proposed. It is based on a lateral BJT device which is easy to incorporate in any standard CMOS process. The design diverts a fraction of the iDD current from the cell under test and a resistive component generates a voltage proportional to iDD Additional features are the possibility of continuous measure of iDD and increased speed of this sensor compared with sensors based on the current integration principle. The design does not have substrate currents due to the parasitic vertical BJTs. Experimental work on the sensor is reported.

Physical defects widely encountered in today’s CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on I DDQ has been investigated by electrical simulation and experimentation.

Although many integrated circuit processing or in-field defects change the functional behaviour of the circuit and may be detected by classical testing techniques, small spot and break defects in the active area of the transistors may just cause electrical parameter changes. In our work, experimental results are presented in order to characterize the behaviour of a class of such faulty devices. A fault model for gate oxide shorts is presented and used to analyse the conditions under which a typical CMOS inverter becomes functionally faulty. Static current inspection testing technique is considered for this kind of fault, proposing a static current circuit checker.

Full open defects on interconnect lines cause broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and trapped charge. However, in nanometer CMOS technologies gate oxide thickness is reduced below a few tens of A, resulting in the gate tunnelling leakage strongly influencing the behaviour of defective circuits with full open defects. Floating lines cannot be considered electrically isolated anymore and are subjected to transient evolutions until reaching a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of gate tunnelling leakage are expected to increase for future technologies. The transient response of full open defects on interconnect lines is analysed for nanometer technologies based on predictive technology models. A method to estimate the delay of defective circuits is proposed. Experimental evidence of this behaviour is presented for a test chip design of 0.18 mum technology.

Full open defects on the interconnect lines cause the broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely: parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and the trapped charge. However, in nanometric CMOS technologies, the oxide thickness is reduced below a few tens of Aring causing the gate tunnelling leakage to strongly impact the behaviour of defective circuits with full open defects. Floating lines can not be considered electrically isolated anymore and are subjected to transient evolutions until arriving at a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of the gate tunnelling leakage is expected to increase for future technologies. The analysis of full opens affecting basic CMOS gates is presented and their defective behaviour characterized. The prediction of the defective logic response of such basic gates is presented for nanometric technologies based on predictive technology models. The final steady state is found to be independent on the initial state of the floating node. Experimental evidence of this behaviour is presented for an industrial chip of 0.18 mum technology.

Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. The authors demonstrate that the impact of downstream current is minimized at low power supply (Vdd) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at VVLV are used for the diagnosis of fifteen failing 0.18mum technology devices, which are demonstrated to contain a bridging defect.

Electronics Letter of the Month Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented. Peer Reviewed Award-winning

Best Paper Award al millor article del congrés IEEE VLSI Test Symposium 2007 A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect. Award-winning

Signal integrity verification is becoming an important issue as technological process features continues to shrink and logic speed increases. Advanced technologies permit a large number of integrated devices onto chip, this characteristic enable to have high performance systems which request good levels of signal integrity. A monitoring technique for the verification of the signal integrity is presented. Two monitors are proposed in order to sense signal undershoots and overshoots at high and low logic levels respectively. The cost of the proposed verification strategy has been estimated in terms of area, extra pins and delay penalisation. Using coherent sampling, the monitors detect signal integrity violations for high speed critical signals.

The interconnect structures in high speed circuits play an important role in present CMOS technologies. Inductance and capacitance coupling effects (crosstalk) may cause a significant loss in signal integrity in high performance systems. One way to reduce these effects is to place a signal line between two grounded lines (shield). In this paper we study the influence of defective grounding of shielding lines. We focus on resistive open defects due to manufacturing problems or broken vias. Faulty shields may cause undershoots or ringings in signals traveling in long interconnect lines. Simple expressions for undershoots and overshoots have been derived using dominant poles and employed to determine the zones of signal integrity violation for different lengths of interconnect lines. The results show the impact of defective grounded shields.

Analog switches (AS) have played an essential role in a large number of mixed signal (M-S) circuits. Depending on the use of the AS, designers have optimised their topology to the needs of each specific switching function. The success of field programmable devices in the digital domain has motivated some manufacturers to explore similar solutions to fast prototyping in the analog and M-S domains. In this work we explore the defective behaviours of programmable AS under realistic catastrophic and parametric defects. A classification of the defective behaviours for bridge and open defects is done. It shows that the. simple fault model, with faulty state of permanently transistor stuck-on or stuck-off, is not sufficient to reflect the real behaviour of the switch.

International audience; The paper deals with a European experience of education in industrial test of ICs and SoCs using remote testing facilities. The project addresses the problem of the shortage in microelectronics engineers aware with the new challenge of testing mixed-signal SoCs far multimedia/telecom market. It aims at providing test training facilities at a European scale in both initial and continuing education contexts. This is done by allowing the academic and industrial partners of the consortium to train engineers using the common test resources center (CRTC) hosted by LIRMM (Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier, France). CRTC test tools include up-to-date/high-tech testers that are fully representative of real industrial testers as used on production testfloors. At the end of the project, it is aimed at reaching a cruising speed of about 16 trainees per year per center. Each trainee will have attend at least one one-week training using the remote test facilities of CRTC.

In this paper, two techniques to reduce the energy and the average power consumption of the system are proposed. They are based on the fact that as the test progresses, the detection efficiency of the pseudo-random vectors decreases very quickly. Many of the pseudo-random vectors will not detect faults in spite of consuming a significant amount of energy from the power supply. In order to prevent this energy consumption, a filtering of the non-detecting vectors and a reseeding strategy are proposed. These techniques are evaluated on the set of ISCAS-85 benchmark circuits. Extensive simulations have been made using the SAIL energy simulator showing that, in large circuits, the energy consumption and the average power savings reach 90.0% with a mean value of 74.2% with the filtering technique, and 97.2% with an average value of 90.9% with the reseeding strategy.

Low-power design looks for low-energy BIST. This paper considers the problem of minimizing the energy required to test a BISTed combinational circuit without modifying the stuck-at fault coverage and with no extra area or delay overhead over the classical LFSR architectures. The objective of this paper is twofold. First, is to analyze the impact of the polynomial and seed selection of the LFSR used as TPG on the energy consumed by the circuit. It is shown that appropriately selecting the seed of the LFSR can lead to an important energy reduction. Second, is to propose a method to significantly decrease the energy consumption of BIST sessions. For this purpose, a heuristic method based on a simulated annealing algorithm is briefly described in this paper. Experimental results using the ISCAS benchmark circuits are reported, showing variations of the weighted switching activity ranging from 147% to 889% according to the seed selected for the LFSR. Note that these results are always obtained with no loss of stuck-at fault coverage.

Two test strategies for external and internal shorts in FCMOS combinational circuits, based on current consumption monitoring, are proposed and analysed: (a) pseudorandom test with a small number of vectors, and (b) a new strategy called current testing vector generation based on stuck at Faults (CUTEGENS). Both test strategies have been experimented on a set of combinational benchmark circuits. The pseudorandom test strategy has been found efficient when testing external shorts but coverages for internal shorts are not as satisfactory. CUTEGENS provides test sets with a reduced number of vectors, which have a very high coverage for both external and internal shorts. In most of the experimented circuits, the coverage has been shown to be the highest obtainable with current consumption monitoring. >

The floating gate transistor is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The location of the open in the open track influences the value of the poly-bulk and metal-poly capacitances who determines the degree of conduction of the defective transistor. The induced voltage in the floating gate and the quiescent current are estimated by means of analytical expressions. A good agreement is observed between the simple analytical expressions, simulations (SPICE) and experimental measures performed on defective circuits. It is shown that a floating gate transistor is not a stuck-open transistor and that significative values of quiescent current consumption may exist.

An I/sub DDQ/ testing strategy combined with logical scan-out observation for bridging faults in scan-based sequential circuits is presented. Internal and external zero resistance bridging faults in both the combinational part and the scan path are considered. The testing strategy targets the faults beginning with those harder to detect. Thus, combinational internal shorts and combinational external shorts are targeted first. Remaining external shorts in the scan path are considered later. A standard ATPG for stuck-at faults, adapted to short fault detection, is used. In order to reduce the test application time, the time to apply I/sub DDQ/ test vectors and the time to produce a shift in the scan chain is taken into account. Results of the experimentation on ISCAS'89 circuits show that the strategy provides high quality test sets of reduced size with the highest obtainable coverages for both internal and external shorts. >

The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. Two techniques to test open defects producing data retention faults are proposed. In the first technique an initial condition is forced during the working phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (I/sub DDQ/) increases and the fault can be detected sensing the I/sub DDQ/. A second technique controlling the power supply level in conjunction with sequential access is proposed. This allows detection of open defects by I/sub DDQ/ testing. The cost of both proposed approaches is analyzed.

A new BIST structure, based on the information provided by the XY-operation (Lissajous curves) is introduced in this paper. A digital signature is obtained which is used to discriminate catastrophic as well as parametric defects. High fault coverage is achieved when applying the proposed BIST on an ITC'97 benchmark circuit where 92% of the catastrophic defects and 87.5% of the parametric defects analyzed produced digital signatures clearly distinguishable from the golden signature.

The objective of this paper is to generate an Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault." Then, it is commented that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is also commented that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.

A Markov model taking into account physical and design faults for a two-version architecture oriented to safety-related applications is developed. Only a probabilistic knowledge of the initial state of the versions in relation to the presence of related design faults is assumed. The model can be split into two submodels accounting separately for physical and design faults, and a closed form expression for the unsafety of the system is obtained. The parameter estimation problem is discussed and a method to predict the probability distribution of the number of related design faults at the beginning of the operational life of the system is proposed. The method uses a pool model to process fault-occurrence data collected during a “face-to-face” debugging of the two versions. It has by nature a limited capacity for proving version diversity, but it is shown that the limit is of the order of the diversity reported by recent experiments on real software. Finally, the impact of version correction during operation is shown to be negligible for critical applications.