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The article reports on the development of Xilinx Inc.'s forthcoming Virtex 5 generation of field programmable gate array in the U.S. Semiconductor companies are shifting to 65-nanometer design rules which predict exceptional logic density and performance. The design rules showed an edge in process technology, circuit design, physical lay-out and software methodologies and equipped with engineering talent.

The article features on the new designs in field programmable gate array (FPGA) architecture developed and distributed by Actel Corp., Altera Corp., Amtel Systems Corp., Lattice Semiconductor Corp., QuickLogic Corp., Xilinx Inc., GiDEL Ltd., Nallatech, SBS Technologies Inc., and VMetro Inc..

The article presents information on low-cost programmable gate arrays. Now nothing will impede the field-programmable gate array's (FPGA) march into scores of volume applications. New architectures both lower the cost and improve functionality, enabling them to cost-effectively compete with application specific integrated circuits (ASICs). Smaller process geometries that shrink chip size go a long way toward reducing cost. But size isn't the only factor in the cost equation. Also driving the use of programmable devices is the shorter product life of many mass-market products. With ASICs, designers typically must allow for manufacturing cycle times of a month or more. Then there are the nonrecurring-engineering (NRE) costs. Programmable logic devices combat all of the above issues. These off-the-shelf parts have no significant NRE charges. If the system is designed properly, they can be updated in the field to correct system flaws or add new features. The per-chip costs might be higher than those of an ASIC, but after considering these other factors, FPGAs become a more cost-effective solution. To further the trend, all companies that offer FPGAs have developed families of low-cost devices that now target mass-market applications.

This article focuses on application specific integrated circuits (ASIC). The rules of the ASIC game are changing as the cost to fabricate a custom solution creeps past the million-dollar mark. And, new rules are emerging due to the shorter market life of the end system and the continuous need to upgrade or update a product's features. Device cost is always a key factor for filed programmable gate arrays (FPGAs), especially those used in the final version of a product. The high-density, resource-rich, top-of-the-line FPGAs tend to cost several hundred dollars to over a $1000 apiece, even in moderate volume. INSETS: FPGAs ENTER NEW DESIGN TERRITORY;STRUCTURED ASICs COMPETE WITH, AND COMPLEMENT, FPGAs.

Programmable logic has become a vital part of design. This article explores the options for complex programmable logic devices and field programmable gate arrays for optimizing system performance in electronic design. Details are presented on input and output issues, capacity and memory options, hard and soft options for embedded processors, and design tools to pull the design together.

Over the last half decade, a new class of configurable application specific integrated circuits (ASIC) has made inroads by bridging the performance and cost gap between designs based on full custom ASIC and high density field programmable gate arrays (FPGA). Known as platform and structured ASICs, these system-on-a-chip solutions are some of the best aspects of custom ASIC and FPGA. As a result, designers have a quick time-to-market option that features lower development costs than ASIC and higher performance and often lower unit costs that FPGAs.

Discusses the design of field-programmable gate arrays (FPGA) from QuickLogic Corp. that combine multiple serial interfaces and logic. Configuration of the dual-ported random access memory to appear as multiple asynchronous first-in, first-out buffers; Direct circuit balancing; Division of the clock grid; Timing and interface flexibility.

Reports that high-density field programmable gate arrays (FPGA) take on system ASIC features and performance levels. Additional logic for clocks; Configuration of the Nios central processing unit soft core; ORCA FPGA technology crafted by Lucent Technologies Inc.; System solution on a chip from Triscend Corp. INSETS: Synthesis Tools Come Of Age For FPGAs.;Extending The Boundaries Of Digital Systems..

Explores the flexible, reconfigurable multiplier block as an embedded function for field programmable gate arrays (FPGA). Functions of the multiplier-block concept; Dedicated blocks of memory or application-specific logic; Networking and data communications as one of FPGA applications. INSET: System-On-A-Chip Designs Also Can Leverage Programmable Tec....

Reports the creation of ProASIC 500K family of flash-based field programmable gate arrays (FPGA) by Actel. Specifications and advantages of the ProASIC FPGA series; Relevance of finegrained logic-cell architecture in the flexibility of the 500K series; Availability and price of ProASIC chips.

Reports that advances in the complex, programmable logic devices (CPLD) have challenged field programmable gate arrays. List of CPLD manufacturers; Technique for lowering manufacturing cost of electrically erasable technology without compromising CPLD performance; Features of the Vantis MACH 5 series.

Features various high-density field programmable gate arrays (FPGA) which feature capacities of 250 kilogates and more. Includes Lucent Technologies' ORCA series of FPGAs; DynaChip Corp.'s DL6000 family; Actel Corp.'s MX series. INSET: ASIC alternatives..

Focuses on the next-generation of field programmable gate arrays that handles PCI-interface function in a single chip. Prototyping and low-volume production needs; Additional support capabilities; Ability to reuse the logic and try various options without the delay of mask iterations. INSET: Checking out the design in a test environment..

Features enhanced field-programmable gate arrays (FPGA) with distributed or dedicated random access memory (RAM). Ease of system design with the use of FPGAs; FPGA family releases by various manufacturers; Engineering design and capabilities of efficient FPGAs.

Reports that Xilinx has crafted a family of fine-grained field-programmable gate arrays (FPGAs) that employ sea-of-gates (SOG) architecture that stacks three levels of metal interconnections above the silicon. XC8100 series to initially include four family members; Secure operation; Cascading; Price and availability.

Part II. Discusses many of the architectural innovations that the suppliers of RAM-based field programmable field arrays (FPGA) have come up with to achieve gate-array-like densities of up to 100,000 gates. Antifuse options. INSET: Analog circuits take a lesson from FPGAs..

Part I. Focuses on RAM-based reconfigurable field-programmable gate arrays. Creation of innovative device architectures based on a variety of technologies; Features of the FLEX 10K series; Advantages of using the FLEX 10K. INSET: A fast-turn alternative to FPGAs..

Focuses on designs of field programmable gate arrays. Challenges facing application specific integrated circuits system-on-a-chip design; Megagate competition. INSET: MEGAGATE FPGAs.

Reports on the development of high-performance field-programmable gate arrays (FPGA) family with on-chip dedicated static random access memory (SRAM), by designers at the Vantis company, which is capable of delivering speeds of 250 MHz. Features of the FPGA; Indepth look at the usage of trench technology; What the variable-grain architecture consists of; Information on the configurable building block.

Focuses on the advancement of circuits and process technologies implemented to field-programmable gate array (FPGA) architectures. Participation of several system designers in the technology; Internal structure of the FPGA; Categories of routing resources which are part of the advancement.

Describes QuickLogic Corporation's speedy field-programmable gate array family that offers both logic and memory. Advantages of the product; What family includes; Availability of the product; Web site address.

Highlights Amtel's AT40K series of dynamically reconfigurable field-programmable gate arrays (FPGAs) that distributes SCRAM and flexible logic. Features and benefits of the product; Availability of the product; Factor contributing to development of the product; Plans of Amtel in relation to the product.

Reports on a second-generation family of low-density FPGA, QuickLogic's pASIC 2 series, that offers 3000 up to 20000 usable gates, datapath speeds exceeding 200 MHz and counter speeds that go beyond 150 MHz without increasing chip area or slowing the logic. Three-layer metallization scheme created to achieve denser interconnections for the logic; Design of the pASIC 2 series. INSET: Not the only three-level metal antifuse solution..

The article discusses the development of a high-performance programmable-logic platform by Velogix Inc. to keep pace with the accelerating shift of Field-programmable gate array (FPGA). Accordingly, FPGA can take on data-path-dominated designs that calls substantial computation capabilities which also allows billions of multiply-accumulate operations. The company developed the logic platform to run billions of operations in video and imaging, test and measurements and communications.

The article reports that DRC Computer Corp. and XtremeData Inc., the first two companies to provide socket-compatible coprocessors for AMD64 Opteron processor sockets, are offering programmable solutions that can speed up time-critical algorithms. These coprocessors take advantage of the flexibility of Xilinx and Altera field-programmable arrays.

The article reports on developments relevant to field-programmable logic array (FPGA) circuits and devices in the United States, which dominates the application specific integrated circuit market. When circuit designers were asked what percentage of their design projects employ FPGA, they shared that 81 percent of their projects include FPGAs.

The article presents information related to Altera Corp.'s new 65-nm field programmable gate arrays. The company has launched the enhanced version of its adaptive logic module (ALM) for 65-nanometer FPUAs. The enhanced ALMs developed for the Stratix III line incorporate software configurable features. The incorporation of 65-nm process technology and configurable power in each ALM helps drive down overall power in the Stratix III line. The next Quartus II release will include support for design-space convergence.

The article reports that the next-generation field programmable gate array, which is based on 65-nanometer design rules, manufactured by Xilinx Inc., is set for sampling in the second half of 2006 in the U.S. According to Chuck Tralka, director of product marketing for Advanced Products Division, the field programmable gate array will have higher gate counts than the 90-nanometer Virtex-4 devices without consuming more power.

The article presents questions and answers related to the Field-Programmable Gate-array (FPGA). One of the questions asks about the various FPGA technologies rank with respect to standby power consumption. The editor answers that the three mainstream FPGA approaches significantly vary in static and standby power consumption due to the differences in the configuration technologies employed within the chips, volatile static RAM cells, reprogrammable flash-based nonvolatile memory cells, and antifuse, metal-to-metal one-time programmable nonvolatile programmable elements. Another question is about the impact of switching between active and low-power modes on system performance. The editor answers that when an FPGA switches into a standby mode, the circuits usually can power down immediately. In older FPGAs, externally gating the clock and possibly lowering the supply voltage can do this. The latest FPGAs have been designed to be more power-aware and include power-management circuitry on board to quickly switch into the standby state and help minimize leakage currents.

Informs on the dual implementation approach developed by Altera to solve the performance issue of field-programmable gate arrays (FPGA) and deliver a single-chip solution. Development of its RISC microprocessor, dubbed Nios; Partnerships with Advanced RISC Machines Ltd. and MIPS Inc.

The article presents questions and answers related to the functioning of field-programmable gate-array (FPGA). One question was related to the efficiency of FPGAs in keeping the standby power consumption lower. Flash-based FPGAs typically use less than 25% of the transistors needed to configure the logic versus the static random access memory (SRAM) configuration scheme, because only a single flash transistor serves as the configuration element. So, leakage currents can be considerably smaller than SRAM-based FPGAs. Typical stand-by currents range from 1 to 10 mA. The three mainstream FPGA approaches significantly vary in static and standby power consumption due to the differences in the configuration technologies employed within the chips. Second question was how switching between active and low-power modes impacts the system performance. When an FPGA switches into a standby mode, the circuits usually can power down immediately. In older FPGAs, externally gating the clock and possibly lowering the supply voltage can do this.

Focuses on the RAM-based field-programmable gate arrays (FPGAs), with reference to the release of the Spartan series of FPGAs from Xilinx. Cost of the devices; Discussion on the performance of the devices; What the Spartan architecture is based on; Features of the devices.

Highlights GateField Corporation's flash-based field-programmable gate-array family, the GFD260F series, that adds 46 Kbits of static random-access memory (SRAM). Enhancement of the series; Benefits of the product; Comparison of GFD260F series to the GF250F series; Details pertaining to the product.

Features Lucent Technologies Inc.'s series of static random access memory-based field programmable gate arrays that will allow electronic designers to merge in standard cell blocks to achieve greater system functionality and higher levels of performance. Design specifications; Market price; Contact information.

Presents the field-programmable gate array (FPGA) family XC4000EX from Xilinx. Features; Capabilities; Price and availability.

The article presents information about various digital electronics products. Now that a billion-plus transistors can fit onto one processor chip, the race to push CPU clock rates has reached a point of diminishing returns due to increasing power consumption. In the nonvolatile memory arena, this year saw the introduction of the first 16-Gbit flash-memory chips from Samsung. These chips are the highest-capacity devices yet released and can replace many of the micro hard drives now used in portable music players. A more realistic gaming experience, on a PC or gaming console, is the charge of advanced graphics chips from ATI and nVidia that deliver 3D images that are more lifelike. In addition to CPUs, memory, and graphics, many other noteworthy products help to drive next-generation system designs. Multi-megagate FPGAs with 10-Gbit serializer/deserializer ports, low-power media processors, and high-resolution imaging chips are among the many candidates.

This article reports that control applications in space-based systems ranging from low-earth orbit to deep-space exploration need microcontrollers that can withstand extreme levels of radiation and temperature. To meet those requirements, Silicon Laude leveraged Actel Corp.'s RTAX-S series of radiation-tolerant field programmable gate arrays (FPGAs). Also, Silicon Laude implemented a radiation-hardened and radiation-tolerant version of the MCS8051 microcontroller in the UT6325 rad-hard FPGAs from Aeroflex. Adding a nonvolatile 64-kword by 16-bit rad-hard magnetoresistive memory from Honeywell Corp. creates a microcontroller subsystem in a single package that can handle up to a 300-krad total ionizing dose of radiation. The microcontrollers include 256 bytes of triple-module-redundancy (TMR) internal RAM, 1536 bytes of on-chip TMR extended data RAM, and memory soft-error detection and correction capability. The microcontrollers include Silicon Laude's proprietary hardware monitor and data exchange (HMDX) technology for real-time monitoring and debugging via an IEEE 1149.1-compatible test port. The HMDX technology also can be used to download programs into the MRAM and examine or edit data memory contents.

The article presents information on programmable-logic devices (PDL). Applications traditionally supported by high-density complex programmable-logic devices (CPLDs) and low-capacity field-programmable gate arrays (FPGA) now have another option, the MachXO series of logic devices. Developed by Lattice Semiconductor, the family brings lower cost and more features to the table. Lattice harnessed the efficiency of a logic architecture based on a lookup table and combined it with high-density, nonvolatile flash storage and distributed blocks of static memory. As a result, the MachXO devices shave cost by as much as 50 per cent per logic function. The MachXO series can handle many traditional FPGA and CPLD applications due in part to its on-chip distributed memory, a low-power sleep mode, and the ability to transparently update configuration data. Similar to the fabric in the company's XP series, the logic fabric consists of an array of programmable function units that each contains four logic slices. Each slice packs a pair of four-input lookup tables and the associated configuration SRAM. Such blocks perform logic, arithmetic, distributed RAM and distributed ROM functions.

The article discusses the Fusion mixed-signal FPGA architecture from Actel, which eliminates those components so electronic designers can implement a true single-chip system. Actel will bring this architecture to market by early next year. The Fusion architecture combines configurable analog peripherals, flash memory, and a multi-megagate FPGA fabric on a single chip. The analog functions will leverage the high-voltage transistors available as part of the embedded flash-memory process used for the FPGA configuration data storage. Based on the company's ProASIC 3 FPGA fabric, the FPGA portion of the Fusion devices will be able to deliver clock speeds of over 150 MHz on datapath logic. Soft processors such as an ARM7 32-bit CPU or an 8051 MCU can be instantiated in the logic fabric.

Introduces the EasyPath series of Spartan-3 and Virtex-4 family FPGA from Xilinx Inc. Distinct features of the product; Product offering; Usability of the device; Cost of the product.

Evaluates the Cyclone II series of field programmable gate arrays from Altera Corp.

Many of today's static random-access memory-based field programmable gate arrays employ four-input look-up tables (LUT) to implement basic logic functions that expand beyond a single LUT or simple functions that occupy only a fraction of an LUT, the basic four input structure can be very inefficient. To overcome this problem, Altera Corp. has developed a novel structure formed what the company calls 'adaptive logic modules'. These circuits enable adjacent logic functions to share logic. As a result, ALMs implement a function with higher performance and greater efficiency.

Reports on topics related to modular field programmable gate arrays (FPGA) designing in the U.S. Efforts by the Xilinx Inc. to keep FPGA designs as generic as possible; Incorporation of the application-specific modular block, a highly modularized architecture for FPGA; Benefits of the technology on the computer industry.

Features the HardCopy, hardwired versions of the Stratix field programmable gate arrays from Altera Corp. Reduction of the size of integrated circuits; Inclusion of optimized embedded digital-signal-processing blocks; Support of the design by the version 3.0 of the Quartus II computer software.

Describes the capabilities of reconfigurable computer fabric to replace application specific integrated circuits and field programmable arrays for base-station signal processing and other applications. Specification of the multiplier-accumulator and other computer resources; Development of computational array.

Features the Cyclone field programmable gate arrays (FPGA) from Altera Corp. Logic density of the FPGA; Redevelopment of the logic architecture; Pricing per 1000 logic elements.

Focuses on Actel Corp.'s Supercluster logic module, an efficient routing scheme for field programmable gate arrays (FPGA). Clock management; Fabrication of antifuse-based FPGA; Clock rates; Supercluster architecture.

Features QuickLogic Corp.'s QuickDSP family of field-programmable gate arrays (FPGA). Programmable logic flexibility; Dedicated multiplier-and-arithmetic blocks; Embedded computational units; Enhancement of each basic logic cell in the FPGA; Fan-in capability; Inclusion of an additional multiplexer.

Features the antifuse design of high-density family of field programmable gate arrays (FPGA) called the MX series developed by Actel Corp. Capability of the MX series; Improvement in the MX series design; Configuration of the MX FPGA.

Highlights DynaChip Corporation's DL5000, high-speed biCMOS field-programmable gate arrays, that handles 270-MHz data rates. Benefits of the product; Features of the product; Company's Web site address.