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A novel sub-threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9 T-SRAM cell offers an improved access time in comparison to the 8 T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8 T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at VDD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling. [ABSTRACT FROM PUBLISHER]

Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed. [ABSTRACT FROM AUTHOR]

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules. [ABSTRACT FROM AUTHOR]

Negative Bias Temperature Instability (NBTI) is one of the major time-dependent degradation mechanisms that impact the reliability of advanced deeply scaled CMOS technologies. NBTI can cause workload-dependent shifts on a transistor’s threshold voltage ( V TH ), and performance during its lifetime. This study presents a comparison of the NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes. The first part of the study focuses on the NBTI-induced performance degradation of 32-bit adders (one of the most fundamental block of a processor’s arithmetic logic unit) from the points of architectural topology and workload dependency in the planar technologies (i.e. commercial 28 , 45 , 65 nm nodes), while the second part investigates the energy-delay product degradation of ring oscillators beyond the planar nodes (i.e. research-grade 14 , 10 , 7 nm FinFET technology nodes for several FET channel materials, e.g. Si, SiGe, Ge, InGaAs). Results show the tight coupling between the NBTI aging and the architectural topology, run-time workload, and technology choice. [ABSTRACT FROM AUTHOR]