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In this work, we present a compact “adaptive downsampling” method that mitigates the nonlinearity problems associated with FPGA-based TDCs that utilize delay lines. Additionally, this generic method allows for trade-offs between resolution, linearity, and resource utilization. Since nonlinearity is one of the predominant issues regarding delay lines in FPGA-based TDCs, combined with the fact that delay lines are utilized for a wide range of TDC architectures (not limited to the delay-line TDC), other implementations (e.g., Vernier or wave union TDCs), also in different FPGA devices, can directly benefit from the proposed adaptive method, with no need for either custom routing or complex tuning of the converter. Furthermore, implementation-related challenges regarding clock skew, measurement uncertainty, and the placement of the TDC are discussed and we also propose an experimental setup that utilizes only FPGA resources in order to characterize the converter. Although the TDC in this work was implemented in a Xilinx Virtex-6 device and was characterized under different operational modes, we successfully optimized the converter’s nonlinearity and resource utilization while retaining single-shot precision. The best performing (in terms of linearity) implementation reached DNLrms and INLrms values of 0.30 LSB and 0.45 LSB, respectively, and the single-shot precision (σ) was 9.0 ps.

Current tapped delay line time to digital converters (TDL-TDC) use simple algorithms to correct the bubble error inherent in the TDL. There is interest in knowing if machine learning could improve upon those algorithms Time interval measurements, measures of time between a START event and STOP event, are used in many applications; for example, time-of-flight experiments. Currently, FieldProgrammable Gate Arrays (FPGAs) are preferred to implement Time-to-Digital Converters (TDCs), due to their low non-recurring costs. Nowadays, the preferred TDC architecture in FPGAs is the Tapped Delay-Line; unfortunately, it suffers from Bubble Errors (Bes). The current methods used to solve those BEs worsen the resolution and precision of the TDC; therefore, we propose multiple new methods of solving BEs, based on Machine Learning, to improve the resolution and precision. The ML methods proposed were tested in two Xilinx FPGAs, the Artix-7 and the Kintex UltraScale. The best ML method achieved a precision in the Artix-7 of 12.749 ps r.m.s, with respect to the 12.789 ps r.m.s of the traditional method; while in the Kintex UltraScale was 13.486 ps r.m.s and 13.481 ps r.m.s respectively. Medir intervalos de tiempo es necesario en muchas aplicaciones; por ejemplo, en experimentos que miden tiempos de vuelo. Hoy en día, los dispositivos conocidos como FPGA son los preferidos para implementar medidores de tiempo (TDC), debido a sus bajos costes no recurrentes; la arquitectura preferida para TDCs en FPGAs está basada en una línea de retardo (TDL), sin embargo, sufre de errores. Los métodos actuales para corregir los errores empeoran la precisión del instrumento. Por esto, en este trabajo proponemos nuevos métodos basados en Inteligencia Artificial (IA), para corregir los errores sin perder precisión. Los métodos propuestos han sido provados en dos FPGAs de Xilinx, la Artix-7 y la Kintex UltraScale. La mejor precisión obtenida con los métodos propuestos fue de 12.749 ps r.m.s en la Artix-7, frente a los 12.789 ps r.m.s del método tradicional; en la UltraScale, fue de 13.486 ps r.m.s y 13.481 ps r.m.s respectivamente. Mesurar intervals de temps és necessari en moltes aplicacions; per exemple, en experiments que mesuren temps de vol. Avui en dia, els dispositius coneguts com FPGA son els preferits per implementar mesuradors de temps (TDCs), degut als seus baixos costos no recurrents; la arquitectura preferida per TDCs en FPGAs esta basada en una línia de retard (TDL), però sofreix errors. Els mètodes actuals de correcció d?errors empitjoren la precisió del TDC. Per això, proposem nous mètodes basats en Inteligencia Artificial, per corregir errors sense perdre precisió. Els mètodes proposats han estat provats en dos FPGAs de Xilinx, la Artix-7 i la Kintex UltraScale. La millor precisió obtinguda amb els nous mètodes ha estat de 12.749 ps r.m.s en la Artix-7, enfront dels 12.789 ps r.m.s del mètode tradicional; en la UltraScale, ha estat de 13.486 ps r.m.s i 13.481 ps r.m.s respectivament.

We present a small, portable, plug–and–play time measurement instrument entirely based on Field Programmable Gate Array (FPGA). Its performance is state–of–the–art in terms of the most recent Application–Specific Integrated Circuit (ASIC) solutions of Time–to–Digital Converters (TDCs), and all operating features are fully–programmable. The instrument offers an excellent cost–performance and is suitable for detector test and time correlation measurement applications. More generally, the instrument is very well suited for fast–prototyping of systems where time measures are involved, at low cost and design effort. All the features of the instrument can be easily accessed through either the Graphical User Interface (GUI) or directly from the software Application Programming Interface (API).

The aim of this Ph.D. work is to reason and show how an open-source multi-channel and standalone time-tagging device was developed, validated and used in combination with a new generation of single-photon array detectors to pursue super-resolved time-resolved fluorescence lifetime imaging measurements. Within the compound of time-resolved fluorescence laser scanning microscopy (LSM) techniques, fluorescence lifetime imaging microscopy (FLIM) plays a relevant role in the life-sciences field, thanks to its ability of detecting functional changes within the cellular micro-environment. The recent advancements in photon detection technologies, such as the introduction of asynchronous read-out single-photon avalanche diode (SPAD) array detectors, allow to image a fluorescent sample with spatial resolution below the diffraction limit, at the same time, yield the possibility of accessing the single-photon information content allowing for time-resolved FLIM measurements. Thus, super-resolved FLIM experiments can be accomplished using SPAD array detectors in combination with pulsed laser sources and special data acquisition systems (DAQs), capable of handling a multiplicity of inputs and dealing with the single-photons readouts generated by SPAD array detectors. Nowadays, the commercial market lacks a true standalone, multi-channel, single-board, time-tagging and affordable DAQ device specifically designed for super-resolved FLIM experiments. Moreover, in the scientific community, no-efforts have been placed yet in building a device that can compensate such absence. That is why, within this Ph.D. project, an open-source and low-cost device, the so-called BrightEyes-TTM (time tagging module), was developed and validated both for fluorescence lifetime and time-resolved measurements in general. The BrightEyes-TTM belongs to a niche of DAQ devices called time-to-digital converters (TDCs). The field-gate programmable array (FPGA) technology was chosen for implementing the BrightEyes-TTM thanks to its reprogrammability and low cost features. The literature reports several different FPGA-based TDC architectures. Particularly, the differential delay-line TDC architecture turned out to be the most suitable for this Ph.D. project as it offers an optimal trade-off between temporal precision, temporal range, temporal resolution, dead-time, linearity, and FPGA resources, which are all crucial characteristics for a TDC device. The goal of the project of pursuing a cost-effective and further-upgradable open-source time-tagging device was achieved as the BrigthEyes-TTM was developed and assembled using low-cost commercially available electronic development kits, thus allowing for the architecture to be easily reproduced. BrightEyes-TTM was deployed on a FPGA development board which was equipped with a USB 3.0 chip for communicating with a host-processing unit and a multi-input/output custom-built interface card for interconnecting the TTM with the outside world. Licence-free softwares were used for acquiring, reconstructing and analyzing the BrightEyes-TTM time-resolved data. In order to characterize the BrightEyes-TTM performances and, at the same time, validate the developed multi-channel TDC architecture, the TTM was firstly tested on a bench and then integrated into a fluorescent LSM system. Yielding a 30 ps single-shot precision and linearity performances that allows to be employed for actual FLIM measurements, the BrightEyes-TTM, which also proved to acquire data from many channels in parallel, was ultimately used with a SPAD array detector to perform fluorescence imaging and spectroscopy on biological systems. As output of the Ph.D. work, the BrightEyes-TTM was released on GitHub as a fully open-source project with two aims. The principal aim is to give to any microscopy and life science laboratory the possibility to implement and further develop single-photon-based time-resolved microscopy techniques. The second aim is to trigger the interest of the microscopy community, and establish the BrigthEyes-TTM as a new standard for single-photon FLSM and FLIM experiments.

V sklopu tega magistrskega dela smo se lotili izdelave hitrega časovno-digitalnega pretvornika visoke ločljivosti na cenovno dostopni plošči Red Pitaya, ki temelji na zmogljivem polno programirljivem čipu Xilinx Zynq 7010. Časovno-digitalni pretvornik (TDC) je popolnoma digitalen in v celoti implementiran na programirljivem polju vrat (FPGA) v ravnokar omenjenem čipu, tako da za opravljanje meritev ne potrebujemo nobenih dodatnih zunanjih komponent. TDC je bil zasnovan po principu časovne interpolacije, kjer čas štejemo z uporabo sinhronega binarnega števca, za zelo natančno določitev časa prihoda med urinimi cikli pa skrbi integrirana zakasnilna linija. Posamezen kanal TDC je na voljo v obliki strojne komponente intelektualne lastnine (jedra IP) z vmesnikom AXI, kar je zelo priročno za gradnjo večkanalnih sistemov. Procesni sistem Zynq bere časovne značke aktivnih časovno-digitalnih pretvornikov in jih preko omrežja Ethernet pošilja odjemalcu, recimo osebnemu računalniku, kjer jih lahko ustrezno obdelamo in prikažemo v grafičnem uporabniškem vmesniku. V sklopu tega magisterija smo implementirali dva kanala TDC in ju podrobno okarakterizirali. Posamezen časovno-digitalni pretvornik teče na frekvenci 350~MHz in je ob mrtvem času $sim$14~ns sposoben vzorčiti do 70 milijonov značk na sekundo. Časovna ločljivost posameznega kanala dosega odličnih 11~ps in ostane zelo visoka tudi pri večjih časovnih intervalih, vsaj nekje do 100~ns. Izkazalo se je, da lahko tudi s povsem običajnimi signali s hitrostjo naraščanja 10~ns opravljamo meritve visoke ločljivosti, prav tako pa je meritev robustna na spremembe temperature. Izdelani TDC je zelo natančen in periodo zunanjega signala izmeri z relativno natančnostjo $10^{-5}$ v 60 stopinj širokem temperaturnem intervalu. Nazadnje smo inštrument preizkusili še v realistični postavitvi s pulznim laserjem in hitro silicijevo fotopomnoževalko (SiPM), kjer se je novi TDC odlično obnesel. Vse to dokazuje, da se da z izbiro primerne arhitekture in modernega čipa FPGA tudi na cenovno zelo dostopnih platformah, kot je Red Pitaya, implementirati izredno zmogljiv časovni merilni inštrument, ki je uporaben tako za študente kot profesionalne raziskovalce. This Master’s Thesis presents an implementation of a fast high-resolution time-to-digital converter (TDC) on the affordable Red Pitaya board, featuring a powerful all programmable Xilinx Zynq 7010 SoC. The design is fully digital, enabling the TDC to be implemented entirely within the Zynq FPGA, thus requiring no additional external components. The architecture of the TDC is based on the time interpolation technique which employs a coarse binary counter and a tapped delay line for fine time measurements between adjacent clock cycles. A TDC channel is packaged into an AXI-interfaced IP core, making it easy to build multichannel systems. Produced timestamps from active TDC channels are read by the Zynq processing system and sent via Ethernet to a client, for example a PC which can process and display them with a graphical user interface. A two-channel TDC system has been implemented and thoroughly characterized during this Thesis work. An individual channel runs at 350~MHz and has a dead time of $sim$14~ns, sampling up to 70 million timestamps per second. Its time resolution can reach an astounding 11~ps and remains very high even at larger time intervals of up to 100~ns. It turned out that high-resolution measurements can also be done with standard 10~ns rise time signals and with widely varying temperatures. The implemented TDC is very accurate and can measure the period of an externally applied signal with relative accuracy of $10^{-5}$ over a 60 degree temperature swing. Finally, the instrument was put to the test in a realistic setup with a pulsed laser and a fast silicon photomultiplier (SiPM), where the new TDC performed exceedingly well. This concludes that by choosing the right architecture and a modern FPGA, a very powerful time measurement instrument, useful both for students and professionals, can be implemented on perfectly affordable hardware platforms such as the Red Pitaya.

This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution.This project improves the resolution further by using a bit-counter to handle bubbles in the TDL without removing any taps.The bit counter also adds the possibility of using a wave-union approach previously dismissed as unusable on this architecture.The final implementation achieves an RMS resolution of 1.8 ps.

Dissertação de mestrado integrado em Engenharia Eletrónica Industrial e Computadores (área de especialização em Sistemas Embebidos e Computadores), There is an expected increase in the demand for Advanced Driver-Assistance Systems (ADAS) over the next decade, incited by regulatory and consumer interest in safety applications that protect drivers and reduce accidents [1]. Even though ADAS applications are still beginning, both the OEMs and their suppliers are realizing that they could become one of the essential characteristics differentiating the various automotive brands, consequently, one of their most important revenue sources. Furthermore, the technologies used in ADAS could be used in the future to create fully autonomous vehicles, which are now becoming a major focus of research and development. There are three main sensor solutions used in ADAS. Firstly, there are optical sensors and camera based-solutions. These are the most versatile and cost-efficient solutions. However, they are easily affected by poor weather and other environmental hazards. Furthermore, they require complex software algorithms to recognize objects [1]. The second solution incorporates short and long range Radars for determining the distance, speed, and direction of objects. These sensors work better than the others in adverse weather conditions. Nonetheless there is typically a compromise between the measurement range and angle [1]. The last type of solution involves using LiDAR systems, which use laser pulses to scan the surroundings and generate a complete and precise three-dimensional image of the environment. The LiDAR is less sensitive to light and weather conditions than optical systems and provides the location of the surrounding objects directly. Due to the ever-growing use of ADAS, there is a need to develop a more advanced LiDAR sensor. To answer that need and to overcome some of the limitations of the current LiDAR sensors, the Chassis Systems Control of the Bosch Group is developing an automotive LiDAR, and the current Master’s thesis is integrated in the project. In this Master’s thesis, an Acquisition System for Bosch’s LiDAR sensor was developed. For measuring the Time-of-Flight of the laser pulses of the LiDAR, to do so multiple TDC Peripherals were developed in an FPGA platform. The measurement precision of the developed Acquisition System varies between 232.17 ps and 188.66 ps, with an average precision of 207.47 ps., É expectável que nas próximas décadas exista um aumento na procura das ADAS, potenciado pelos interesses dos reguladores e dos consumidores em aplicações que protejam o condutor e reduzam o número de acidentes. Tanto os OEMs, como os seus fornecedores aperceberam-se que, apesar das ADAS ainda estarem numa fase inicial, podem-se tornar uma característica diferenciadora entre as diversas marcas de automóveis, e por isso, uma das suas principais fontes de rendimento. Além disso, as tecnologias usadas nas ADAS poderão vir a ser utilizadas para criar veículos autónomos, os quais se estão a revelar como um dos principais focos da pesquisa e desenvolvimento. Existem três principais soluções de sensores usadas nas ADAS. Primeiro, existem as soluções baseadas em sensores óticos, que são as soluções mais versáteis e económicas. No entanto, este tipo de soluções é facilmente afetado pelo mau tempo e outros fatores ambientais. Para além do facto de necessitarem o uso de algoritmos complexos para reconhecerem objectos. A segunda solução incorpora o uso de RADARs de longo e curto alcance, com o objetivo de determinar a distância, velocidade e direção dos objetos. Estes sensores são pouco afetados por condições meteorológicas adversas. Porém, existe um compromisso entre o alcance e o ângulo de medição do sensor. A última solução envolve o uso de sistemas de LiDAR. Estes sistemas usam pulsos de laser para examinar meio-envolvente, de modo a gerar uma imagem tridimensional completa do mesmo. O LiDAR é menos sensível à luz e às condições meteorológicas e consegue fornecer diretamente a localização dos objetos à sua volta. Devido à crescente utilização das ADAS, existe a necessidade de desenvolver sensores LiDAR mais avançados. Para suprir essa necessidade e para ultrapassar algumas das limitações dos sensores atuais, a divisão Chassis Systems Control, do grupo Bosch, está atualmente a desenvolver uma solução de um sensor LiDAR para a indústria automóvel, projeto onde se insere esta dissertação. Nesta dissertação foi desenvolvido um Sistema de Aquisição para o sensor LiDAR. Este sistema mede o TOF dos pulsos de laser usado pelo LiDAR. Para isso, vários periféricos de TDC foram desenvolvidos numa FPGA. A precisão de medição do sistema varia entre os 232.17 ps e os 188.66 ps, com um valor médio de 207.47 ps., This work is supported by European Structural and Investment Funds in the FEDER component, through the Operational Competitiveness and Internationalization Programme (COMPETE 2020) [Project nº 037902; Funding Reference: POCI-01-0247-FEDER-037902].

U sklopu diplomskog rada projektiran je jedan vremensko-digitalni pretvornik te je implementiran na FPGA pločici i prikazani su rezultati mjerenja. Sklop je prošao kroz više promjena dok nisu dobiveni zadovoljavajući rezultati. TDC je projektiran u Quartus II kao shema i prebačena je u VHDL kod. TakoĎer je izvedena MATLAB simulacija jednostavnog vremensko digitalnog pretvornika i prikazani su rezultati simulacije Time-to-digital converters are electronic devices which measure very short time intervals and can digitalise those intervals. They are often use din PLL circuits and particle physics and therefore are interesting. One kind of time-to-digital converter is implemented in FPGA circuit board and measurement results are shown in this thesis. The circuit went through some changes until satisfying results are obtained. TDC is designed in Quartus II as a schematic and then it is transfered to VHDL code. A simulation in MATLAB was made and the results are displayed in this paper.

This article presents an application of a novel technique for precise measurements of time and charge based solely on a field programmable gate array (FPGA) device for positron emission tomography (PET). The described approach simplifies electronic circuits, reduces the power consumption, lowers costs, merges front-end electronics with digital electronics, and also makes more compact final design. Furthermore, it allows to measure time when analog signals cross a reference voltage at different threshold levels with a very high precision of ~15 ps (rms) and thus enables sampling of signals in a voltage domain.

Detecting and counting single photons is useful in an increasingly large number of applications. Most applications require large formats, approaching and even far exceeding 1 megapixel. In this thesis, we look at the challenges of massively parallel photon-counting cameras from all performance angles. The thesis deals with a number of performance issues that emerge when the number of pixels exceeds about 1/4 of megapixels, proposing characterization techniques and solutions to mitigate performance degradation and non-uniformity. Two cameras were created to validate the proposed techniques. The first camera, SwissSPAD, comprises an array of 512 x 128 SPAD pixels, each with a one-bit memory and a gating mechanism to achieve 5ns high precision time windows with high uniformity across the array. With a massively parallel readout of over 10 Gigabit/s and positioning of the integration time window accurate to the pico-second range, fluorescence lifetime imaging and fluorescence correlation spectroscopy imaging achieve a speedup of several orders of magnitude while ensuring high precision in the measurements. Other possible applications include wide-field time-of-flight imaging and the generation of quantum random numbers at highest bit-rates. Lately super-resolution microscopy techniques have also used SwissSPAD. The second camera, LinoSPAD, takes the concepts of SwissSPAD one step further by moving even more 'intelligence' to the FPGA and reducing the sensor complexity to the bare minimum. This allows focusing the optimization of the sensor on the most important metrics of photon efficiency and fill factor. As such, the sensor consists of one line of SPADs that have a direct connection each to the FPGA where complex photon processing algorithms can be implemented. As a demonstration of the capabilities of current lowcost FPGAs we implemented an array of time-to-digital converters that can handle up to 8.5 billion photons per second, measuring each one of them and accounting them in high precision histograms. Using simple laser diodes and a circuit to generate light pulses in the picosecond range, we demonstrate a ubiquitous 3D time-of-flight sensor. The thesis intends to be a first step towards achieving the world's first megapixel SPAD camera, which, we believe, is in grasp thanks to the architectural and circuital techniques proposed in this thesis. In addition, we believe that the applications proposed in this thesis offer a wide variety of uses of the sensors presented in this thesis and in future ones to come.

Time to digital converter (TDC) is a digital unit that measures the time interval between two events.This is useful to determine the characteristics and patterns of a signal or an event. In this thesis ahybrid TDC is presented consisting of a tapped delay line and a clock counter principle. The TDC is used to measure the time between received data in a QKD application. If the measuredtime does not exceed a certain value then data had been sent without any interception. It is alsopossible to use TDCs in other fields such as laser-ranging and time-of-flight applications. The TDC consists of two carry chains, an encoder, a FIFO and a counter for each channel, anAXI-module and a control unit to generate command signals to all channels that are implemented.The time is measured by sampling the signal that has propagated through the carry chain and from thissample encode the propagation length. In this thesis a TDC is implemented that has a 10 ns dead time and a resolution below 28 psin a four channel mode. The propagation variation is approximately two percent of the total valueduring testing. For the implementation an FPGA-board with a Zynq XC7Z020 SoC is used withSystemVerilog that is a hardware describing language (HDL).

El presente trabajo resume el proceso de implementación y calibración de un convertidor de tiempo a digital que se utilizara para medir frecuencias desde 200Mzh hasta 400Mhz. La implementación del mismo se realiza utilizando la FPGA Cyclone IV de Altera.

The construction and design process of a highresolution time-interval measuring system implemented in a SRAM-based FPGA device is discussed in this paper. The TDC can increase the precision on the measurement by interpolating time within the system clock cycle. A two step phase interpolation has been constructed, one based on the phase information delivered by the VIRTEX-5 Digital Clock Manager (DCM) and thus providing a fine time, a second level phase interpolation was based on carry lines thus delivering an hyper fine time measurement. We have designed and built a PCB hosting a Virtex-5 Xilinx FPGA. The board we have designed provides 7 TDC channels. The number of channels turns out to be limited by the number of input connectors inserted on the board and not on the code density on the FPGA. The range is in principle slightly longer than 1 day (127941 sec), but our tests are preliminary and have been made on intervals less than 20 μsec. In this range we have measured a resolution which is better than 55 psec for the time interval on a single channel in single and multi-hit mode.

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh cryogenic environment. The proposed architecture employs time-to-digital converters (TDCs) and phase interpolation techniques to reach a sampling rate, higher than the clock frequency (maximum 400 MHz), up to 1.2 GSa/s. The resulting FPGA ADC can achieve a 6 bit resolution (ENOB) over a 0.9 to 1.6 V input range and an effective resolution bandwidth (ERBW) of 15 MHz. This implies that the ADC has an effective Nyquist rate of 30 MHz, with an oversampling ratio of $40\times $. The system non-linearities are less than 1 LSB. The main advantages of this architecture are its scalability and reconfigurability, enabling applications with changing demands on one single platform.

LinoSPAD is a reconfigurable camera sensor with a 256x 1 CMOS SPAD (single-photon avalanche diode) pixel array connected to a low cost Xilinx Spartan 6 FPGA. The LinoSPAD sensor's line of pixels has a pitch of 24 pm and 40% fill factor. The FPGA implements an array of 64 TDCs and histogram engines capable of processing up to 8.5 giga-photons per second. The LinoSPAD sensor measures 1.68 mmx6.8 mm and each pixel has a direct digital output to connect to the FPGA. The chip is bonded on a carrier PCB to connect to the FPGA motherboard. 64 carry chain based TDCs sampled at 400 MHz can generate a timestamp every 7.5 ns with a mean time resolution below 25 ps per code. The 64 histogram engines provide time-of n-arrival histograms covering up to 50 ns. An alternative mode allows the readout of 28 bit timestamps which have a range of up to 4.5 ms. Since the FPGA TDCs have considerable non-linearity we implemented a correction module capable of increasing histogram linearity at real-time. The TDC array is interfaced to a computer using a super-speed USB3 link to transfer over 150k histograms per second for the 12.5 ns reference period used in our characterization. After characterization and subsequent programming of the post-processing we measure an instrument response histogram shorter than 100 ps FWHM using a strong laser pulse with 50 ps FWHM. A timing resolution that when combined with the high fill factor makes the sensor well suited for a wide variety of applications from fluorescence lifetime microscopy over Raman spectroscopy to 3D timen-of-flight.