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In this paper, we design and analysis of mean filter using field programmable gate arrays (FPGAs) for digital images, FPGAs are integrated circuits consisting of interconnections that connect programmable internal hardware blocks allows users to customize operations for a specific application. FPGA is an ideal choice for real-time image processing, these FPGA devices are controlled in Verilog or VHDL languages, allowing to design at different levels and adapt to design changes or even support new applications throughout the life of the component. Digital image filtering is the most important task in image processing and with the help of computers, image recognition involves identifying and classifying objects in an image. This paper design of mean filter for digital image processing, implementation and analysis of image processing algorithms on FPGAs. The results obtained on the FPGA are compared and analyzed with the results by MATLAB software. [ABSTRACT FROM AUTHOR]

The current study uses Field-Programmable Gate Array (FPGA) hardware to advance smart home technology through a self-learning system. The proposed intelligent three-hidden layer system outperformed prior systems with 99.21% accuracy using real-world data from the MavPad dataset. The research shows that FPGA solutions can do difficult computations in seconds. The study also examines the difficulties of maximizing performance with limited resources when incorporating deep learning technologies into FPGAs. Despite these challenges, the research shows that FPGA-based solutions improve home technology. It promotes the integration of sophisticated learning algorithms into ordinary electronics to boost their intelligence. [ABSTRACT FROM AUTHOR]

A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Process–Voltage–Temperature stable IODELAYs. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and especially resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field. [ABSTRACT FROM AUTHOR]

Introduction: In the field of industrial manufacturing, accurate inspection of mechanical components such as gears and bearings is of Paramount importance. However, the traditional mechanical testing methods are often disturbed by human factors, which not only affects the stability of the test results, but also leads to low efficiency and large error. In order to solve these problems, this research focuses on developing a new edge detection model. Methods: A novel edge detection model based on field-programmable gate array image processing technology was used in this study. The model uses adaptive threshold multi-directional edge detection technology to identify the edge features of mechanical gears and bearings, aiming at improving the precision of detection. Results and Discussion: After performance verification, the running time of the model was controlled within 11 s, and the detection error was limited to less than 9%. Compared with the control group and the experimental group, their performance was superior. Further analysis data show that the detection accuracy of this model is as high as 0.9004, its internal resource utilization rate is 88%, and the detection rate is as high as 91%, which are better than the comparison model. Conclusion: The proposed test model not only significantly improves the efficiency and accuracy of the test, but also fully meets the requirements of the test. This new edge detection model has potential application value in industrial manufacturing field, and provides a new solution for industrial manufacturing quality inspection. [ABSTRACT FROM AUTHOR]

An improved combined-mode power converter (CMPC) for a solar photovoltaic (SPV) system is presented in this paper. Ten-power electronic switches are utilised for the functioning of the converter. The proposed converter has four modes of operation: buck, boost, inverter, and mixed mode. The new CMPC topology provides a unique and complex switching sequence for implementing the mixed-mode operation. This work uses a field-programmable gate array (FPGA) for mode selection and to create PWM (MS-PWM) signals. A digital MS-PWM controller is configured to switch between improved stepped perturb and observe (ISPO) maximum-power point tracking (MPPT) and sine wave PWM (SPWM). The ISPO provides the appropriate duty cycle for buck/boost operation, while the SPWM controls the inverter operation. This work's new digital PWM control algorithm supports mode selection, PWM generation, and reconfiguring PWM generation timings. The whole framework for constructing the MS-PWM controller employs a very high-speed integrated circuit hardware description language (VHDL). Simulation and experimental results are presented, proving that the digital MS-PWM controller uses fewer resources with improved accuracy. [ABSTRACT FROM AUTHOR]

March algorithms are widely used in Memory Built-In Self-Test (MBIST) on-chip memory testing, providing linear test complexities that reduce the test time and cost. However, studies show that March algorithms with complexities lower than 18N have poor coverages of faults that have emerged with the advent of the nanometer process technologies and are more relevant to nowadays memories. New March AZ1 and March AZ2 algorithms, with 13N and 14N complexities, respectively, were introduced to provide optimum coverage of those faults and to produce a shorter test than an 18N-complexity test algorithm with a lesser area overhead, thus reducing chip manufacturing costs. This paper presents the implementation and validation of MBIST controllers that applied the March AZ1 and March AZ2 algorithms in a Field-Programmable Gate Array (FPGA) device. They were implemented in the Intel Max 10 DE10-Lite FPGA Development Board. A test generator was built in FPGA, as an alternative to the external tester, to provide test vectors required in initiating the test on the memory model using the implemented MBIST. The FPGA experimental tests demonstrated that they function correctly as the expected test sequences were observed. In addition, their fault detection abilities were also validated through tests on a fault-injected memory model, which shows that the implemented March AZ1 and March AZ2 provide 80.6% and 83.3% coverage of the intended faults, respectively, which outperform any other existing 14N-complexity March algorithms. [ABSTRACT FROM AUTHOR]

A new dual-frequency, dual-mode reconfigurable digital receiver based on Field-Programmable Gate Array (FPGA) dynamic reconfiguration is proposed, which is based on a common hardware platform of high-bandwidth RF front-end, high-speed data acquisition, and real-time signal processing. The receiver adopts the design of dynamically reconfigurable down-conversion, filter extraction, and matched filtering in the digital domain. In this study, we completed the design and development of the digital receiver, experimental platform construction, and field detection test with hardware and software cooperation. The experimental results show that the receiver achieves full digital reception and signal processing for 53.8 MHz stratosphere–troposphere (ST) detection and 35.0 MHz meteor detection and successfully acquired the number of meteors versus time, the meteor trail, and low-altitude atmospheric radial winds. This dual-frequency, dual-mode reconfigurable digital receiver can be applied to new-generation multifunction integrated radar systems such as dual-frequency ST/meteor radars. [ABSTRACT FROM AUTHOR]

In this letter, a tunable hybrid metasurface (THMS) with electromagnetic switching characteristics based on the field‐programmable logic gate array (FPGA) is developed, which combines the mechanisms of both phase cancellation and absorption. Compared to other hybrid metasurface, the proposed design possesses two major functions of electromagnetic switching and dynamic tuning. By adjusting the bias voltage of the active components controlled by FPGA module, the in‐band tuning and active switching at different frequency bands of 3.63–5.57, 4.86–10.47, and 9.40–12.36 GHz can be obtained. A physical prototype with the size of 350 mm × 370 mm is fabricated and measured for verification, and the measurement shows that the monostatic radar cross section achieves varying degrees of reduction from 1.66 to 12.04 GHz. [ABSTRACT FROM AUTHOR]

Modern applications require the ability to measure time events with high resolution, a full-scale range, and multiple input channels. Time-to-Digital Converters (TDCs) are a popular option to convert time intervals into timestamps. To reduce the time-to-market and Non-Recurring Engineering (NRE) costs, a Field-Programmable Gate Array (FPGA) implementation has been chosen. The high number of requested bits and channels, however, gives rise to routing congestion issues when routed in a parallel manner. In this paper, we will propose and analyze a novel solution, the Belt-Bus (BB), which involves a parallel-to-serial conversion of the timestamp stream coming from the TDC while maintaining chronological order and a sufficient high rate, and flagging the presence of timestamp overflow. Moreover, two new useful features are added. The first is a "Virtual Delay" to compensate for offsets due to cable length and FPGA routing path mismatch. The second is a "Virtual Dead-Time" to filter out unforeseen events. Finally, the BB was tested on a Xilinx 28 nm 7-Series Kintex-7 325T FPGA, achieving an overall data rate of 199.9 Msps with very limited resource usage (i.e., lower than a total of 4.5%), consuming only 480 mW in a 16-channel implementation. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to the reconfigurable digital down converter (DDC) reducing the sampling frequency from 3.64 GHz to 28.4375 MHz on the field-programmable gate array (FPGA) device. The proposed DDC consists of a polyphase mixer and a resampling filter. The polyphase mixer can reduce the high-speed sampling rate signal and generates a complex baseband signal having sufficient noise margin. The resampling filter produces a large decimation factor and improves the filtering quality. The design has been optimized at the sub-component level using very few multiplier blocks, resulting in low power consumption. The sampling rate factors can be dynamically programmed in real-time to increase the flexibility of the design. In addition, truncation is used in each filter stage to protect from overflow errors. Moreover, the design is described in optimum hardware description language to reduce the available resources, without compromising the functionality. Finally, the proposed DDC has been simulated and tested on the Xilinx Kintex-7 FPGA board. According to synthesis results, it is noticed that the proposed design reduces the area and power consumption compared to other existing architectures. In the end, the feasibility of the proposed architecture is tested to certify the system's validity. [ABSTRACT FROM AUTHOR]

The fractional Fourier transform (FrFT) is a useful mathematical tool for signal and image processing. In some applications, the eigendecomposition-based discrete FrFT (DFrFT) is suitable due to its properties of orthogonality, additivity, reversibility and approximation of continuous FrFT. Although recent studies have introduced reduced arithmetic complexity algorithms for DFrFT computation, which are attractive for real-time and low-power consumption practical scenarios, reliable hardware architectures in this context are gaps in the literature. In this paper, we present two hardware architectures based on the referred algorithms to obtain N-point DFrFT ( N = 4 L , L is a positive integer). We validate and compare the performance of such architectures by employing field-programmable gate array implementations, co-designed with an embedded hard processor unit. In particular, we carry out computer experiments where synthesis, error and latency analyses are performed, and consider an application related to compact signal representation. [ABSTRACT FROM AUTHOR]

e present the implementation of the hardware ANS compressor in FPGAs. The main goal of the design was to propose a solution suitable to low-cost, low-energy embedded systems. We propose the streaming-rANS algorithm of the ANS family as a target for the implementation. Also, we propose a set of algorithm parameters that substantially reduce the use of FPGA resources, and we examine what is the influence of the chosen parameters on compression performance. Further, we compare our design to the lossless codecs found in literature, and to the streaming-rANS codecs with arbitrary parameters. [ABSTRACT FROM AUTHOR]

Local optical field modulation using plasmonic materials or photonic crystals provides a powerful strategy for enhancing upconversion emission of lanthanide-doped upconversion nanocrystals (UCNPs). However, it is restricted to static UC enhancement and the corresponding dynamic modulation of UC is yet to be reported, limiting its practical applications in information devices. Here, a dynamic UC modulation system is reported through electric stimulation by integrating UCNPs with electrically sensitive WO3_x plasmonic photonic crystals (PPCs). The tunable emission enhancement of UCNPs varying from five to 26 folds is achieved in WO3_x PPCs/UCNPs hybrids through external electric stimulation within +1.6 and _1.6 V. It stems from the reversible control of the photonic bandgaps and localized surface plasmon resonance of WO3_x PPCs, ascribed to the variation of refractive index and oxygen vacancy of WO3_x, induced by the reversible change of atomic ratio of W5+ to W6+ under different applied voltages. Moreover, the electrically triggered information encryption devices are developed, employing a programmable logic gate array based on WO3_x PPCs/UCNPs with the ability to convert information-encrypted electrical signals into visible patterns. These observations offer a new attempt to manipulate the UC and will simulate the new applications in the display and optical storage devices. [ABSTRACT FROM AUTHOR]

Square-root unscented Kalman filter (SRUKF) is a widely used state estimator for several state of-the-art, highly nonlinear, and critical applications. It improves the stability and numerical accuracy of the system compared to the non-square root formulation, the unscented Kalman filter (UKF). At the same time, SRUKF is less computationally intensive compared to UKF, making it suitable for portable and battery-powered applications. This paper proposes a low-complexity and power-efficient architecture design methodology for SRUKF presented with a use case of the simultaneous localization and mapping (SLAM) problem. Implementation results show that the proposed SRUKF methodology is highly stable and achieves higher accuracy than the extensively used extended Kalman filter and UKF when developed for highly critical nonlinear applications such as SLAM. The design is synthesized and implemented on resource constraint Zynq-7000 XC7Z020 FPGA-based Zedboard development kit and compared with the state-of-the-art Kalman filter-based FPGA designs. Synthesis results show that the architecture is highly stable and has significant computation savings in DSP cores and clock cycles. The power consumption was reduced by 64 % compared to the state-of-the-art UKF design methodology. ASIC design was synthesized using UMC 90-nm technology, and the results for on-chip area and power consumption results have been discussed. [ABSTRACT FROM AUTHOR]

Summary: This research work reports the finding of a new 4‐D hyperchaotic two‐scroll system having three second‐order nonlinear terms. It is detailed that the system does not have any rest point for non‐zero values of the system parameters. Thus, we deduce that the new hyperchaotic system has a hidden attractor. The main findings of the new hyperchaotic system include a detailed bifurcation analysis, coexisting attractors, and offset‐boosting control. The new 4‐D hyperchaotic two‐scroll system with hidden attractor is prototyped using the field‐programmable gate array (FPGA) Zybo Z7‐20 development board, Xilinx Vivado tool, and the hardware description by VHDL. It is highlighted that the simulation of the circuit design, and the experimental results from the FPGA synthesis, all of them are in good agreement with theoretical simulations. [ABSTRACT FROM AUTHOR]

Phase jitter is one of the crucial factors in modern digital electronics, determining the reliability of a design. This paper presents a novel approach to designing a jitter comparison system and methodology for FPGA chips using a Tapped Delay Line (TDL)—commonly used to implement a Time-to-Digital Converter (TDC). The design and its revision utilizing latches replacing some of the flip-flops are presented and discussed, with potential further improvements. A minimal temperature influence is verified and presented. The methodology of automated relative jitter measurements is discussed. Multiple different FPGA clock signal path configurations are measured, and the results are presented. The influence of clock routing is identified as critical when MMCM or PLL modules are omitted. It is demonstrated that with careful resource and routing allocation, the clock signal's jitter performance does not have to be deteriorated by the absence of jitter filtering blocks. The proposed technique was implemented and verified and relative jitter performance was measured in the AMD/Xilinx Artix 7 35T FPGA platform. [ABSTRACT FROM AUTHOR]

Error Correction Codes (ECCs) stand as a linchpin in ensuring data accuracy in wireless communication. As the landscape of modern communication standards continues to expand, there is a mounting inclination towards efficient ECC technologies, such as Low-Density Parity-Check codes (LDPCs). Distinguished by their near-capacity performance and low computational complexity, LDPCs are increasingly utilized in the successful encoding and decoding of data. This study undertakes an exploration of recent advancements in LDPC research, encompassing the analysis of decoding algorithms, architectures, applications, simulations, real-world implementations, and complexities across various hardware platforms. The central research problem addressed within this work is the identification of the most efficacious LDPC decoder implementation, with an emphasis placed on Field-Programmable Gate Array (FPGA) technology. From the outcomes of this study, the MinSum algorithm emerged as the favored choice for LDPC decoding, particularly within FPGA implementations. The selection of this algorithm is attributable to its simplicity and implementation feasibility, thus directly addressing the posed research problem. The inherent simplicity of the Min-Sum algorithm's structure renders it a practical choice for real-world applications. Further, its proficiency in error correction and compatibility with FPGA hardware underscore its potential for augmenting the reliability of data transmission in communication systems. The findings of this study advocate for the Min-Sum algorithm as a valuable asset in LDPC decoding, notably within FPGA implementations. This positions it as a promising candidate for optimizing data communication systems. The selection of FPGA as the implementation platform reaffirms its practicality and relevance in contemporary communication technology, thus offering a comprehensive solution to the identified research problem. [ABSTRACT FROM AUTHOR]

We describe a study on the effect of temperature variations on multi-channel time-to-digital converters (TDCs). The objective is to study the impact of ambient thermal variations on the performance of field-programmable gate array (FPGA)-based tapped delay line (TDL) TDC systems while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study, we chose two devices, Artix-7 and ProASIC3L, manufactured by Xilinx and Microsemi, respectively. The radiation-tolerant ProASIC3L device offers better stability in terms of thermal sensitivity and power consumption compared to the Artix-7. To assess the performance of the TDCs under varying thermal conditions, a laboratory thermal chamber was utilized to maintain ambient temperatures ranging from −75 to 80 °C. This analysis ensured a comprehensive evaluation of the TDCs' performance across a wide operational range. By utilizing the Artix-7 and ProASIC3L devices, we achieved root mean square (RMS) resolution of 24.7 and 554.59 picoseconds, respectively. Total on-chip power of 0.968 W was achieved using Artix-7, while 1.997 mW of power consumption was achieved using the ProASIC3L device. We worked to determine the temperature sensitivity for both FPGA devices, which could help in the design and optimization of FPGA-based TDCs for many applications. [ABSTRACT FROM AUTHOR]

We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union type A architecture where only the first multiplexer is used to generate the wave union pulse train at the arrival of the start signal to minimize the required computational processing. In addition, an auto-calibration algorithm is proposed to help improve the TDC performance by improving the TDC Differential Non-Linearity and Integral Non-Linearity. [ABSTRACT FROM AUTHOR]

Domain-specific accelerators for signal processing, image processing, and machine learning are increasingly being implemented on SRAM-based field-programmable gate arrays (FPGAs). Owing to the inherent error tolerance of such applications, approximate arithmetic operations, in particular, the design of approximate multipliers, have become an important research problem. Truncation of lower bits is a widely used approximation approach; however, analyzing and limiting the effects of carry-propagation due to this approximation has not been explored in detail yet. In this article, an optimized carry-aware approximate radix-4 Booth multiplier design is presented that leverages the built-in slice look-up tables (LUTs) and carry-chain resources in a novel configuration. The proposed multiplier simplifies the computation of the upper and lower bits and provides significant benefits in terms of FPGA resource usage (LUTs saving 38.5%–42.9%), Power Delay Product (PDP saving 49.4%–53%), performance metric (LUTs × critical path delay (CPD) × PDP saving 68.9%– 73.1%) and errors (70% improvement in mean relative error distance) compared to the latest state-of-the-art designs. Therefore, the proposed designs are an attractive choice to implement multiplication on FPGA-based accelerators. [ABSTRACT FROM AUTHOR]

This paper investigates the performance of deep convolutional spiking neural networks (DCSNNs) trained using spike-based backpropagation techniques. Specifically, the study examined temporal spike sequence learning via backpropagation (TSSL-BP) and surrogate gradient descent via backpropagation (SGD-BP) as effective techniques for training DCSNNs on the field programmable gate array (FPGA) platform for object classification tasks. The primary objective of this experimental study was twofold: (i) to determine the most effective backpropagation technique, TSSL-BP or SGD-BP, for deeper spiking neural networks (SNNs) with convolution filters across various datasets; and (ii) to assess the feasibility of deploying DCSNNs trained using backpropagation techniques on low-power FPGA for inference, considering potential configuration adjustments and power requirements. The aforementioned objectives will assist in informing researchers and companies in this field regarding the limitations and unique perspectives of deploying DCSNNs on low-power FPGA devices. The study contributions have three main aspects: (i) the design of a low-power FPGA board featuring a deployable DCSNN chip suitable for object classification tasks; (ii) the inference of TSSL-BP and SGD-BP models with novel network architectures on the FPGA board for object classification tasks; and (iii) a comparative evaluation of the selected spike-based backpropagation techniques and the object classification performance of DCSNNs across multiple metrics using both public (MNIST, CIFAR10, KITTI) and private (INHA_ADAS, INHA_KLP) datasets. [ABSTRACT FROM AUTHOR]

Processing large-scale graphs is challenging due to the nature of the computation that causes irregular memory access patterns. Managing such irregular accesses may cause significant performance degradation on both CPUs and GPUs. Thus, recent research trends propose graph processing acceleration with Field-Programmable Gate Arrays (FPGA). FPGAs are programmable hardware devices that can be fully customised to perform specific tasks in a highly parallel and efficient manner. However, FPGAs have a limited amount of on-chip memory that cannot fit the entire graph. Due to the limited device memory size, data needs to be repeatedly transferred to and from the FPGA on-chip memory, which makes data transfer time dominate over the computation time. A possible way to overcome the FPGA accelerators' resource limitation is to engage a multi-FPGA distributed architecture and use an efficient partitioning scheme. Such a scheme aims to increase data locality and minimise communication between different partitions. This work proposes an FPGA processing engine that overlaps, hides and customises all data transfers so that the FPGA accelerator is fully utilised. This engine is integrated into a framework for using FPGA clusters and is able to use an offline partitioning method to facilitate the distribution of large-scale graphs. The proposed framework uses Hadoop at a higher level to map a graph to the underlying hardware platform. The higher layer of computation is responsible for gathering the blocks of data that have been pre-processed and stored on the host's file system and distribute to a lower layer of computation made of FPGAs. We show how graph partitioning combined with an FPGA architecture will lead to high performance, even when the graph has Millions of vertices and Billions of edges. In the case of the PageRank algorithm, widely used for ranking the importance of nodes in a graph, compared to state-of-the-art CPU and GPU solutions, our implementation is the fastest, achieving a speedup of 13 compared to 8 and 3 respectively. Moreover, in the case of the large-scale graphs, the GPU solution fails due to memory limitations while the CPU solution achieves a speedup of 12 compared to the 26x achieved by our FPGA solution. Other state-of-the-art FPGA solutions are 28 times slower than our proposed solution. When the size of a graph limits the performance of a single FPGA device, our performance model shows that using multi-FPGAs in a distributed system can further improve the performance by about 12x. This highlights our implementation efficiency for large datasets not fitting in the on-chip memory of a hardware device. [ABSTRACT FROM AUTHOR]

Because of the linear and nonlinear variations in the operating environment, autonomous underwater vehicles (AUVs) are one of the most difficult applications. The complexity of the control algorithm should be less for real-time implementation in a field programable gate array logic (FPGA) device. In this work, a highly accurate FPGA implementation of PID-Fuzzy control strategy is proposed for an AUV operation that is extremely precise. Parameters such as weight, water density, and depth are used to perform highly efficient and accurate control for the proposed system. A type II fuzzy logic controller and accompanying proportional-integralderivative controller are used to confine pitch and depth boundaries. The proposed design is modeled using SIMULINK software, and Verilog code is generated using hardware description language coder from MATLAB. Xilinx software is used to synthesize the Verilog code for spartan FPGA. The proposed technique improves the accuracy and reduces the response time when compared to the conventional control strategy. [ABSTRACT FROM AUTHOR]

Field-Programmable Gate Arrays (FPGAs) can be found in an increasing number of application domains, such as the telecom industry, the automotive electronics sector, or automation technology as well as in the area of reconfigurable computing. In recent years, it can be observed that the open-source idea which is known from the software domain for a long time also became popular in the world of hardware and FPGA design. In the era of the Internet of Things, many of today's electronic devices implement some kind of network interface with Ethernet being known as one of the most widely used network standards. Thus, there is consequently a high demand on available Ethernet implementations for FPGA platforms. The goal of this work is to survey available open-source Ethernet MAC IP cores, evaluate existing designs in terms of performance, resource utilization, code quality, or maturity, and to present and summarize the evaluation results herein. Furthermore, advantages of commercial solutions and related publication work are discussed. To the authors' best knowledge, this is the first publication that evaluates and compares existing open-source Ethernet MAC IP cores on a large scale. This work should help designers to select an appropriate open-source Ethernet MAC for an FPGA design and shows possible pitfalls and things to pay attention when using an open-source IP core in general. Finally, the authors would like to show that the open-source community can be also very helpful in the world of hardware in terms of design reuse or time to market. [ABSTRACT FROM AUTHOR]

Due to technological advancements and voltage scaling, leakage power has become an important concern in CMOS design. The implementation of a field-programmable gate array (FPGA) circuit utilizes a portion of the FPGA's resources as compared to an application-specific integrated circuit (ASIC). Both the utilized and unutilized parts of the FPGA dissipate leakage power. In this work, two dynamic power gating techniques, PSG-1 and PSG-2, are proposed, which are able to reduce the leakage power of the 6-input look-up table (LUT) used in the Xilinx Spartan-6 series. The obtained results show that the proposed approaches PSG-1 and PSG-2 reduce average leakage power by 54.61% and 66.69%, respectively, at the expense of nominal area and delay overhead. The proposed method is also capable of lowering the average total power of the 6-input LUT. The suggested PSG-1 and PSG-2 approaches reduce average power by 53.75% and 60.83%, respectively. However, header-based power supply gating is extremely vulnerable to the negative-bias temperature instability (NBTI) aging effect and, due to this, the lifetime of the circuit is reduced considerably. Therefore, in this work, lifetime estimation-based analysis is performed by varying the stress probability of the sleep transistor. The results show that the LUT with PSG-1 and PSG-2 techniques has a lifetime of 4.55 years and 11.13 years, respectively. The stress time of the sleep transistor is 50% for the PSG-1 technique and 25% for the PSG-2 technique, respectively. [ABSTRACT FROM AUTHOR]

Introduction. Currently, the direct torque control is very popular in industry and is of great interest to scientists in the variable speed drive of asynchronous machines. This technique provides decoupling between torque control and flux without the need to use pulse width modulation or coordinate transformation. Nevertheless, this command presents two major importunities: the switching frequency is highly variable on the one hand, and on the other hand, the amplitude of the torque and stator flux ripples remain poorly controlled throughout the considered operating speed range. The novelty of this article proposes improvements in performance of direct torque control of asynchronous machines by development of a fuzzy direct torque control algorithm. This latter makes it possible to provide solutions to the major problems of this control technique, namely: torque ripples, flux ripples, and failure to control switching frequency. Purpose. The emergence of this method has given rise to various works whose objective is to show its performance, or to provide solutions to its limitations. Indeed, this work consists in validation of a fuzzy direct torque control architecture implemented on the ML402 development kit (based on the Xilinx Virtex-4 type field programmable gate array circuit), through hardware description language (VHDL) and Xilinx generator system. The obtained results showed the robustness of the control and sensorless in front of load and parameters variation of induction motor control. The research directions of the model were determined for the subsequent implementation of results with simulation samples. [ABSTRACT FROM AUTHOR]

This paper presents a new recursive trigonometric (RT) technique for Field-Programmable Gate Array (FPGA) design implementation. The traditional implementation of trigonometric functions on FPGAs requires a significant amount of data storage space to store numerous reference values in the lookup tables. Although the coordinate rotation digital computer (CORDIC) can reduce the required FPGA storage space, their implementation process can be very complex and time-consuming. The proposed RT technique aims to provide a new approach for generating trigonometric functions to improve communication accuracy and reduce response time in the FPGA. This new RT technique is based on the trigonometric transformation; the output is calculated directly from the input values, so its accuracy depends only on the accuracy of the inputs. The RT technique can prevent complex iterative calculations and reduce the computational errors caused by the scale factor K in the CORDIC. Its effectiveness in generating highly accurate cosine waveform is verified by simulation tests undertaken on an FPGA. [ABSTRACT FROM AUTHOR]

Many shortcomings of chaos-based applications stem from the weak dynamic properties of the chaotic maps they use. To alleviate this problem, inspired by the buffeting effect in aeroelasticity, this article proposes the buffeting chaotification model (BCM). Using the especially designed buffeting and modulo operators, the BCM can generate numerous new chaotic maps with strong dynamic properties from existing one-dimensional chaotic maps. The effectiveness of the BCM is mathematically proven according to the Lyapunov exponent, and further numerical experiments confirm the superiority of the chaotic maps generated by the BCM in terms of the dynamic properties. The field-programmable gate array implementation also shows that the BCM owns simplicity in hardware devices. To investigate the practical application, a scheme for constructing the pseudorandom number generator is designed. Performance analyses indicate that our generators have a strong ability to produce high-quality pseudorandom sequences rapidly. [ABSTRACT FROM AUTHOR]

The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs. [ABSTRACT FROM AUTHOR]

Intelligent sensor systems are essential for building modern Internet of Things applications. Embedding intelligence within or near sensors provides a strong case for analog neural computing. However, rapid prototyping of analog or mixed signal spiking neural computing is a non-trivial and time-consuming task. We introduce mixed-mode neural computing arrays for near-sensor-intelligent computing implemented with Field-Programmable Analog Arrays (FPAA) and Field-Programmable Gate Arrays (FPGA). The combinations of FPAA and FPGA pipelines ensure rapid prototyping and design optimization before finalizing the on-chip implementations. The proposed approach architecture ensures a scalable neural network testing framework along with sensor integration. The experimental set up of the proposed tactile sensing system in demonstrated. The initial simulations are carried out in SPICE, and the real-time implementation is validated on FPAA and FPGA hardware. [ABSTRACT FROM AUTHOR]

The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and variable index-based algorithms. However, these algorithms require large amounts of computation, making them difficult to apply in radar applications that require real-time target detection. We propose a new CFAR algorithm that determines the environment of a received signal through a new decision criterion and applies the optimal CFAR algorithms such as the modified variable index (MVI) and automatic censored cell averaging-based ordered data variability (ACCA-ODV). The Monte Carlo simulation results of the proposed CFAR algorithm showed a high detection probability of 93.8% in homogeneous and nonhomogeneous environments based on an SNR of 25 dB. In addition, this paper presents the hardware design, field-programmable gate array (FPGA)-based implementation, and verification results for the practical application of the proposed algorithm. We reduced the hardware complexity by time-sharing sum and square operations and by replacing division operations with multiplication operations when calculating decision parameters. We also developed a low-complexity and high-speed sorter architecture that performs sorting for the partial data in leading and lagging windows. As a result, the implementation used 8260 LUTs and 3823 registers and took 0.6 μ s to operate. Compared with the previously proposed FPGA implementation results, it is confirmed that the complexity and operation speed of the proposed CFAR processor are very suitable for real-time implementation. [ABSTRACT FROM AUTHOR]

Synthetic aperture radar (SAR), which can generate images of regions or objects, is an important research area of radar. The chirp scaling algorithm (CSA) is a representative SAR imaging algorithm. The CSA has a simple structure comprising phase compensation and fast Fourier transform (FFT) operations by replacing interpolation for range cell migration correction (RCMC) with phase compensation. However, real-time processing still requires many computations and a long execution time. Therefore, it is necessary to develop a hardware accelerator to improve the speed of algorithm processing. In addition, the demand for a small SAR system that can be mounted on a small aircraft or drone and that satisfies the constraints of area and power consumption is increasing. In this study, we proposed a CSA-based SAR processor that supports FFT and phase compensation operations and presents field-programmable gate array (FPGA)-based implementation results. We also proposed a modified CSA flow that simplifies the traditional CSA flow by changing the order in which the transpose operation occurs. Therefore, the proposed CSA-based SAR processor was designed to be suitable for modified CSA flow. We designed the multiplier for FFT to be shared for phase compensation, thereby achieving area efficiency and simplifying the data flow. The proposed CSA-based SAR processor was implemented on a Xilinx UltraScale+ MPSoC FPGA device and designed using Verilog-HDL. After comparing the execution times of the proposed SAR processor and the ARM cortex-A53 microprocessor, we observed a 136.2-fold increase in speed for the 4096 × 4096-pixel image. [ABSTRACT FROM AUTHOR]

We propose a multidimensional reconciliation encoding algorithm based on a field-programmable gate array (FPGA) with variable data throughput that enables quantum key distribution (QKD) systems to be adapted to different throughput requirements. Using the circulatory structure, data flow in the most complex pipeline operation in the same time interval, which enables the structural multiplexing of the algorithm. We handle the calculation and storage of eight-dimensional matrices cleverly to conserve resources and increase data processing speed. In order to obtain the syndrome more efficiently, we designed a simplified algorithm according to the characteristics of the FPGA and parity-check matrix, which omits the unnecessary operation of matrix multiplication. The simplified algorithm could adapt to different rates. We validated the feasibility and high speed of the algorithm by implementing the multidimensional reconciliation encoding algorithm on a Xilinx Virtex-7 FPGA. Our simulation results show that the maximum throughput could reach 4.88 M symbols/s. [ABSTRACT FROM AUTHOR]

Field‐programmable gate array (FPGA)‐based real‐time simulators are often applied in simulations of active distribution networks (ADNs) because of their parallel architectures and low cost. The overall performance of an FPGA‐based real‐time simulator is mainly determined by its kernel solver, which solves the nodal equation at each simulation time step. With the increasing scale of ADNs, real‐time simulations of fast switching dynamics, along with limited computation hardware, have increased the requirements of the solver in terms of both time and resource consumption. In this study, a highly parallel kernel solver is proposed to improve the simulation efficiency of the FPGA‐based real‐time simulator. The multi‐level parallel design and its implementation, including the parallelism at the system and module and element levels, are presented in detail. A modified IEEE 123‐node system with distributed photovoltaics (PVs) is then simulated using a three‐FPGA‐based real‐time simulator. Simulation results are compared with the commercial simulation tool PSCAD/EMTDC to validate the proposed kernel solver. [ABSTRACT FROM AUTHOR]

In this paper, the design and experimental validation of a prototype phasor measurement unit (PMU) that simultaneously meets the P and M class requirements of the IEC/IEEE Std 60255-118-1-2018 are presented. The device is based on a synchrophasor estimation (SE) algorithm, previously formulated by the authors, which exploits the generation and use of a delayed in-quadrature complex signal to mitigate the self-interference of the fundamental tone. The method is deployed to a NI CompactRIO-9039 platform, requiring a total use of 19.2% flip-flops, 50.6% LUTs, 77.9% DSPs and 13.7% BRAM for a single-channel configuration and operating under a 50-fps report rate, 50 kHz sampling rate, and three nominal cycle observation windows. A PMU calibrator is used to perform a comprehensive metrological analysis of the device and verify its compliance with the standard. The results show that the prototype meets the requirements of both P and M classes with a worst-case measurement reporting latency of 36.21 ms. • Phasor measurement unit prototype simultaneously compliant with P- and M- classes. • Metrological validation according to IEC/IEEE 60255-118-1-2018 Standard. • Time-delay interpolated discrete Fourier transform algorithm. • Deployment in a field-programmable gate array based on a commercial compactRIO-9039. [ABSTRACT FROM AUTHOR]

Time-to-digital converters (TDCs) are major components for the measurements of time intervals. Recent developments in field-programmable gate array (FPGA) have enabled the opportunity to implement high-performance TDCs, which were only possible using dedicated hardware. In order to eliminate empty histogram bins and achieve a higher level of linearity, FPGA-based TDCs typically apply compensation methods either using multiple delay lines consuming more resources or postprocessing, leading to a permanent loss of temporal information. In this article, we propose a novel TDC with a single delay line and without compensation to realize a highly linear TDC by encoding the states of the delay lines instead of the thermometer code used in the conventional TDCs. The experimental results show our states-based approach achieves an improved differential nonlinearity of [ $-$ 0.998, $-$ 1.533] for time resolution of 5.00 ps, [ $-$ 0.44, 0.49] for 10.04 ps, [ $-$ 0.16, 0.19] for 21.65 ps, [ $-$ 0.10, 0.11] for 43.87 ps, [ $-$ 0.06, 0.07] for 64.12 ps, and [ $-$ 0.07, 0.05] for 87.73 ps, whilst no empty bins have been observed. To the best of authors’ knowledge, the achieved raw linearity together with the zero empty bins and a simple delay line structure exceeds previously reported of the FPGA-based TDCs. [ABSTRACT FROM AUTHOR]

Advanced technology used for arithmetic computing application, comprises greater number of approximatemultipliers and approximate adders. Truncation and Rounding-based Scalable ApproximateMultiplier (TRSAM) distinguish a variety of modes based on height (h) and truncation (t) as TRSAM (h, t) in the architecture. This TRSAM operation produces higher absolute error in Least Significant Bit (LSB) data shift unit. A new scalable approximate multiplier approach that uses truncation and rounding TRSAM (3, 7) is proposed to increase themultiplier accuracy. With the help of foremost one bit architecture, the proposed scalable approximate multiplier approach reduces the partial products. The proposed approximate TRSAM multiplier architecture gives better results in terms of area, delay, and power. The accuracy of 95.2% and the energy utilization of 24.6 nJ is observed in the proposed multiplier design. The proposed approach shows 0.11%, 0.23%, and 0.24% less Mean Absolute Relative Error (MARE) when compared with the existing approach for the input of 8-bit, 16-bit, and 32-bit respectively. It also shows 0.13%, 0.19%, and 0.2% less Variance of Absolute Relative Error (VARE) when compared with the existing approach for the input of 8-bit, 16-bit, and 32-bit respectively. The proposed approach is implemented with Field-Programmable Gate Array (FPGA) and shows the delay of 3.640, 6.481, 12.505, 22.572, and 36.893 ns for the input of 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit respectively. The proposed approach is applied in digital filters designwhich shows the Peak-Signal-to-NoiseRatio (PSNR) of 25.05 dB and Structural Similarity Index Measure (SSIM) of 0.98 with 393 pJ energy consumptions when used in image application. The proposed approach is simulated with Xilinx and MATLAB and implemented with FPGA. [ABSTRACT FROM AUTHOR]

Since Google proposed Transformer in 2017, it has made significant natural language processing (NLP) development. However, the increasing cost is a large amount of calculation and parameters. Previous researchers designed and proposed some accelerator structures for transformer models in field-programmable gate array (FPGA) to deal with NLP tasks efficiently. Now, the development of Transformer has also affected computer vision (CV) and has rapidly surpassed convolution neural networks (CNNs) in various image tasks. And there are apparent differences between the image data used in CV and the sequence data in NLP. The details in the models contained with transformer units in these two fields are also different. The difference in terms of data brings about the problem of the locality. The difference in the model structure brings about the problem of path dependence, which is not noticed in the existing related accelerator design. Therefore, in this work, we propose the ViA, a novel vision transformer (ViT) accelerator architecture based on FPGA, to execute the transformer application efficiently and avoid the cost of these challenges. By analyzing the data structure in the ViT, we design an appropriate partition strategy to reduce the impact of data locality in the image and improve the efficiency of computation and memory access. Meanwhile, by observing the computing flow of the ViT, we use the half-layer mapping and throughput analysis to reduce the impact of path dependence caused by the shortcut mechanism and fully utilize hardware resources to execute the Transformer efficiently. Based on optimization strategies, we design two reuse processing engines with the internal stream, different from the previous overlap or stream design patterns. In the stage of the experiment, we implement the ViA architecture in Xilinx Alveo U50 FPGA and finally achieved ~5.2 times improvement of energy efficiency compared with NVIDIA Tesla V100, and 4–10 times improvement of performance compared with related accelerators based on FPGA, that obtained nearly 309.6 GOP/s computing performance in the peek. [ABSTRACT FROM AUTHOR]

Sound source localization (SSL) has been widely applied in industrial and civil fields. And with the development of wearable devices and the Internet of Things (IoT), it is attractive to deploy the SSL system onto embedded and portable devices. However, the software-based SSL system causes excessive response delay and is often affected by environmental noise. To overcome this obstacle, we propose the fast and precise localization (FPL) algorithm for distributed SSL systems. It combines the benefits of both time difference of arrival (TDOA) and steered response power (SRP) methods, and thus it is able to localize sound sources fast and precisely. To further improve the localization speed, we propose the fast and reconfigurable localization (FRL) accelerator, which is an algorithm-hardware co-designed SSL accelerator. It adopts multiple distributed localization nodes for higher localization precision and higher robustness to environmental interference, and it can be configured into either the fast or precise mode to adapt to various environments. Experimental evaluations show that our proposed FPL algorithm can achieve high localization speed and precision, and the field-programmable gate array (FPGA)-based FRL accelerator outperforms the software implementation by $48.6\times $ and outperforms the prior FPGA-based SSL accelerators by $20\times \sim 838.2\times $. [ABSTRACT FROM AUTHOR]

In this article, we present a hardware architecture optimized for sparse and dense matrix processing in TensorFlow Lite and compatible with embedded-heterogeneous devices that integrate central processing unit and field-programmable gate array (FPGA) resources. The fused architecture for dense and sparse matrices design offers multiple configuration options that tradeoff parallelism and complexity, and uses a dataflow model to create four stages that read, compute, scale, and write results. All stages are designed to support TensorFlow Lite operations including asymmetric quantized activations, column-major matrix write, per-filter/per-axis bias values, and current scaling specifications. The configurable accelerator is integrated with the TensorFlow Lite inference engine running on the ARMv8 processor. We compare performance/power/energy with the state-of-the-art RUY software multiplication library showing up to 18× acceleration and 48× in dense and sparse modes, respectively. The sparse mode benefits from structural pruning to fully utilize the digital signal processing blocks present in the FPGA device. [ABSTRACT FROM AUTHOR]

Convolutional neural networks (CNNs) have had great success when applied to computer vision technology, and many application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) CNN accelerators have been proposed. These accelerators primarily focus on the acceleration of a single input, and they are not particularly optimized for video applications. In this article, we focus on the similarities between continuous inputs in video, and we propose a YOLOv3-tiny CNN FPGA accelerator using incremental operation. The accelerator can skip the convolution operation of similar data between continuous inputs. We also use the Winograd algorithm to optimize the conv $3\times 3$ operator in the YOLOv3-tiny network to further improve the accelerator’s efficiency. Experimental results show that our accelerator achieved 74.2 frames/s on ImageNet ILSVRC2015. Compared to the original network without Winograd algorithm and incremental operation, our design provides a $4.10\times $ speedup. When compared with other YOLO network FPGA accelerators applied to video applications, our design provided a $3.13\times $ – $18.34\times $ normalized digital signal processor (DSP) efficiency and $1.10\times $ – $14.2\times $ energy efficiency. [ABSTRACT FROM AUTHOR]

Spiking neural networks (SNNs) have been witnessing the developing trends to reduce the model size and improve the hardware efficiency for area- and energy-based applications, which are processed by model pruning and data compressions. However, it is challenging to exploit the unstructured sparsity of SNNs for the dense neuromorphic processors. In this article, we present an efficient sparse SNN accelerator (ESSA), which leverages both the temporal sparsity of spike events and the spatial sparsity of weights in SNN inference. It provides both the compressed weights for sparse SNNs and the uncompressed weights for compact SNNs. The self-adaptive spike compression is proposed for sparse spike scenarios, leading to the improvement of throughput by $3.2\times $. ESSA executes a flexible fan-in–fan-out tradeoff by using combinable dendrites, which overcomes the fan-in limitation in neuromorphic systems. Furthermore, a low-latency intrachip spike multicast method is adopted to reduce the resource overhead. Implemented on the Xilinx Kintex Ultrascale field-programmable gate array (FPGA), ESSA achieves an equivalent performance of 253.1 GSOP/s and an energy efficiency of 32.1 GSOP/W for 75% weight sparsity at 140 MHz. The implementation of a four-layer fully connected SNN is expected to perform $2.6~\mu \text{s}$ per time step and the energy consumption is $14.6~\mu \text{J}$. Our results demonstrate that ESSA outperforms several state-of-the-art application-specific integrated circuit (ASIC) or FPGA neuromorphic processors. [ABSTRACT FROM AUTHOR]

Recently, secure neural network (NN) inference, a combination of homomorphic encryption (HE) and NN, has attracted much attention. Nevertheless, a large number of computations, mainly brought by the HE scheme, form the bottleneck in real-time applications. In this article, we present a hardware accelerator on a field-programmable gate array (FPGA) for the homomorphic convolution layer (HomConvL), which is the most computation-intensive part of the HE-based secure inference. First, we propose a new HomConvL algorithm called packed rotations at inputs (PaRotI), which is suitable for hardware implementation for its inherent high parallelism and low complexity with acceptable noise growth and moderate resource consumption. Then, we present three highly parallel architectures for different parameter sets and application scenarios of state-of-the-art HomConvL algorithms. The new architectures are implemented on a Xilinx VCU110 FPGA board, and the experimental results demonstrate that our designs can achieve 15.31– $19.46\times $ speedups compared with the software implementations. [ABSTRACT FROM AUTHOR]

The Transformer has been an indispensable staple in deep learning. However, for real-life applications, it is very challenging to deploy efficient Transformers due to the immense parameters and operations of models. To relieve this burden, exploiting sparsity is an effective approach to accelerate Transformers. Newly emerging Ampere graphics processing units (GPUs) leverage a 2:4 sparsity pattern to achieve model acceleration, while it can hardly meet the diverse algorithm and hardware constraints when deploying models. By contrast, we propose an algorithm–hardware co-optimized framework to flexibly and efficiently accelerate Transformers by utilizing general N:M sparsity patterns. First, from an algorithm perspective, we propose a sparsity inheritance mechanism along with inherited dynamic pruning (IDP) to obtain a series of N:M sparse candidate Transformers rapidly. A model compression scheme is further proposed to significantly reduce the storage requirement for deployment. Second, from a hardware perspective, we present a flexible and efficient hardware architecture, namely, STA, to achieve significant speedup when deploying N:M sparse Transformers. STA features not only a computing engine unifying both sparse–dense and dense–dense matrix multiplications with high computational efficiency but also a scalable softmax module eliminating the latency from intermediate off-chip data communication. Experimental results show that, compared to other methods, N:M sparse Transformers, generated using IDP, achieves an average of 6.7% improvement on accuracy with high training efficiency. Moreover, STA can achieve $14.47\times $ and $11.33\times $ speedups compared to Intel i9-9900X and NVIDIA RTX 2080 Ti, respectively, and perform $2.00 \,\,\sim 19.47 \times $ faster inference than the state-of-the-art field-programmable gate array (FPGA)-based accelerators for Transformers. [ABSTRACT FROM AUTHOR]

We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms such as intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a field-programmable gate array (FPGA) platform. Our FPGA implementation eliminates the need for digital signal processor (DSP) units and reduces the number of Look-Up Tables (LUTs). By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from MP approximation. The implementation of this proposed multiplierless MP-kernel machine on FPGA results in an estimated energy consumption of 13.4 pJ and power consumption of 107 mW with ~9 k LUTs and Flip Flops (FFs) each for a 256 $\times $ 32 sized kernel making it superior in terms of power, performance, and area compared with other comparable implementations. [ABSTRACT FROM AUTHOR]

In the explicit model predictive control (EMPC), memory increases exponentially with the number of states, inputs, constraints, and prediction horizons; this often limits its applicability to large systems. In this article, we present a novel memory reduction technique for the lightweight EMPC using a novel posit number format implemented on a field-programmable gate array (FPGA), aiming to reduce the memory footprints and power utilization of the EMPC. We developed a fully automatic framework for the design of fast embedded EMPC on FPGAs using posit arithmetic and logical unit (ALU). The proposed technique is based on encoding all data (i.e., the critical regions and the feedback laws) as posit numbers, which can be viewed as a more memory-efficient alternative to the IEEE 754 floating-point standard. The performance and efficiency of the developed posit-based offset-free EMPC are demonstrated on the anesthesia control problem. We show the results of hardware-in-the-loop co-simulation with the detailed analysis of the resource utilization, power utilization, clock achieved, and the memory footprints comparison between IEEE 754 floating-point and posit formats. By doing so, we illustrate that the total memory footprints can be reduced by 50%–75% with achieving low power utilization as compared to floating-point numbers without sacrificing the control performances. The proposed technique can be applied on top of other existing complexity reduction techniques used in EMPC as well as for the online optimization methods. [ABSTRACT FROM AUTHOR]

Using field-programmable gate arrays (FPGAs) for software and hardware verification and development is a standard step in the digital application-specific integrated circuits (ASICs) design flow. However, asynchronous FPGAs are not available on the market and commercially available FPGAs provide support only for synchronous circuits. Although a lot of research effort has been undertaken in order to use synchronous FPGA to map asynchronous circuits, proposed solutions are typically lacking automation and target-specific circuit style and sometimes specific FPGA vendor. In this work, we present an automated solution for asynchronous circuits mapping onto the synchronous FPGAs. We build a synchronous model of the original asynchronous circuit based on the event-driven simulation concepts. The proposed approach supports a wide range of circuit styles, including those with various timing assumptions and complex circuitry structures incompatible with the standard synchronous flow. We avoid using vendor-specific features so that the model we generate can be implemented on any commercially available FPGA. We provide an extensive evaluation of our solution and demonstrate that our approach results in a speedup factor of $1.3\times 10^{5}$ against an asynchronous circuit simulator, $2.8\times 10^{4}$ against commercial digital simulators, and is 16.5 times slower than the expected performance of the original asynchronous circuit implemented as an ASIC. [ABSTRACT FROM AUTHOR]

Chip manufacturers define voltage margins on top of the “best-case” operational voltage of their chips to ensure reliable functioning in the worst-case settings. The margins guarantee correctness of operation, but at the cost of performance and power efficiency. Violating the margins is tempting to save energy, but might lead to timing errors. This article proposes an algorithmic solution that enables reliable removal of the margins by detecting errors on the fly. In contrast to previous approaches that require special hardware to detect timing errors, the proposed method is fully implementable using high-level synthesis tools without reliance on additional hardware. The approach is demonstrated using a $32 \times 32$ matrix-matrix multiplication and a simple multilayer neural network implemented on two Xilinx ZC702 field-programmable gate array (FPGA) System-on-Chip (SoC) platforms, showcasing its utility in detecting errors that may originate from different sources of logic circuits, clock tree, or memory. Results show that the energy dissipation is halved, while the implementation is clocked at 2.5x faster than specified by the design tool of the vendor. [ABSTRACT FROM AUTHOR]

Energy consumption has become a bottleneck in modern integrated circuits (ICs) with a significant part of the energy spent on data communication. High-speed, serial interfaces are widely used, offering important advantages over parallel buses. The energy demand of source synchronous, serial buses can be effectively decreased by employing encoding techniques that reduce the bit transitions of the transmitted data stream. However, these techniques are not applicable for asynchronous interfaces, such as Peripheral Component Interconnect Express (PCIe), where frequent bit transitions are required to recover the clock at the receiver to maintain link integrity. Recognizing this fundamental trait, an encoding technique named serial tuned transition encoding (STTE) is proposed that regulates the number of transitions such that the clock can be reliably recovered, while the communication energy is lowered. The proposed scheme provides at least 25% decrease in energy for a short interposer-based interconnect compared to scrambling, which is typically used in serializer/deserializer (SerDes) devices. The link integrity is experimentally evaluated using both an electrical and an optical link that interconnect two field-programmable gate array (FPGA) devices. Results demonstrate that STTE successfully preserves link integrity as no errors are induced during transmission. In addition, STTE adjusts the number of transitions, thus allowing energy reduction and link integrity to be traded off. [ABSTRACT FROM AUTHOR]

Reconfigurable computing can significantly improve the performance and energy efficiency of many applications. However, FPGA-based chips are evolving rapidly, increasing the difficulty of evaluating the impact of new capabilities such as HBM and high-speed links. In this paper, a real-world application was implemented on different FPGAs in order to better understand the new capabilities of modern FPGAs and how new FPGA technology improves performance and scalability. The aforementioned application was the preconditioned conjugate gradient (PCG) method that is utilized in underground analysis. The implementation was done on four different FPGAs, including an MPSoC, taking into account each platform's characteristics. The results show that today's FPGA-based chips offer eight times better performance on a memory-bound problem than 5-year-old FPGAs, as they incorporate HBM and can operate at higher clock frequencies. [ABSTRACT FROM AUTHOR]