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The epitaxial growth of Si and SiGe layers on (1 1 0) Si substrates using UHV-CVD is studied with comparing that on (1 0 0) substrates. It is revealed that, while the growth rate on (1 1 0) surfaces is quite lower than that on (1 0 0) surfaces, the Ge content of SiGe is the same between (1 0 0) and (1 1 0) surfaces, meaning that the ratio of decomposition yields of source molecules for Si and Ge are same in both the (1 0 0) and (1 1 0) substrates. This characteristic is expected to lead to the epitaxial growth of SiGe films with uniform Ge content over the three-dimensional patterned structure, which can be utilized for vertical FET and Fin-FETs. Actually, it has been experimentally confirmed that the SiGe films grown over trench structures has a uniform Ge content. [Copyright &y& Elsevier]

Abstract: Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, we review our recent results on high hole mobility p-MOSFETs using global/local SiGe or Ge channels. There are two directions for introducing SiGe or Ge channels into Si CMOS platform. One is to use SiGe or Ge global substrates and the other is to form SiGe or Ge-channel regions locally on Si wafers. In both cases, the Ge condensation technique, where Ge-channel layers are formed by oxidizing SiGe films on SOI substrates, are effectively utilized. As for the global technologies, ultrathin GOI substrates are prepared and used to fabricate high mobility GOI p-MOSFETs. As for the local technologies, SGOI or GOI channels are formed locally in the active area of p-MOSFETs on SOI wafers. It is shown that the hole mobility enhancement factor of as high as 10 is obtained in locally fabricated p-MOSFETs through the effects of high-Ge content and the compressive strain. Furthermore, the local Ge-channel technologies are combined with global SiGe or Ge substrates for pursuing the optimal and individual design of n-MOSFETs and p-MOSFETs on a single Si wafer. The CMOS device composed of strained-Si n-MOSFETs and SGOI p-MOSFETs is successfully integrated on a same wafer, which is a promising CMOS structure under deep sub 100nm technology nodes. [Copyright &y& Elsevier]

Abstract: We propose a novel method to form Ge nano-wire structures by utilizing a three-dimensional (3D) Ge condensation technique. Since this method needs only top-down and Si compatible processes, Ge nano-wire MOSFETs fabricated by this technique are suitable for actual LSI applications. Based on this concept, we have fabricated SiGe on insulator wire pMOSFETs with Ge content up to 92% and diameter down to 35 nm. 3× enhancement of transconductance against a control Si device has been demonstrated in pMOSFETs with Ge content of 79%, though the performance enhancement in the highest Ge content device has not been obtained yet because of the non-optimized 3D Ge condensation processes. Further performance enhancement is expected after optimizing 3D Ge condensation processes especially for higher Ge content SiGe channels. [Copyright &y& Elsevier]