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Modern digital systems can be viewed as compositions of combinational and sequential blocks. In the article, we discuss a case when sequential blocks are represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper proposes a novel design method which allows diminishing the number of LUTs and increasing the operating frequency of multi-level LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the transformation of states into FSM outputs and two-fold state encoding. The proposed method results in three-level logic circuits of Mealy FSMs with regular systems of interconnections. Each function for any level of logic is implemented using a single LUT. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to decreasing LUT counts from 11.9% to 62.6%. Also, it leads to increasing the operating frequency from 11.77% to 18.43% on average compared with other investigated approaches (Auto and One-hot of Vivado, JEDI, and replacement of FSM inputs and encoding the collections of outputs). The economy in used LUTs and gain in operating frequency grow with the growth of the FSM complexity.

A method is proposed for optimizing hardware expenditure in the Moore FSM circuit implemented with FPGA. The method is based on joint input replacement use and transformation of state codes into codes of classes of pseudoequivalent states. This approach leads to a three-level FSM circuit. An example of synthesis of a Moore FSM with application of the proposed method is shown. Analysis of positive and negative features of the proposed method is constructed. The researches based on standard benchmark FSMs show that the proposed method allows reducing hardware expenditure and consumed power with insignificant amount of degradation of FSM performance.

The optimization methods of the logic circuit of Moore finite-state-machine are proposed. These methods are based on the existence of pseudo equivalent states of Moore finite-state-machine, wide fan-in of PAL macrocells, and free resources of embedded memory blocks. The methods are oriented on hypothetical VLSI microcircuits based on CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm of choice of the best model of finite-state-machine for given conditions is proposed. The examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated. The analysis of the effectiveness of proposed methods showed that optimal in the given conditions method always permits a decrease of the hardware amount in comparison with earlier known methods of the Moore finite-state-machine design. This decrease in hardware does not lead to a decrease in the performance of the control unit. Moreover, there are some special cases, when some other models of Moore finite-state-machine are more effective. The proposed methods can be modified for real CPLDs, where embedded memory blocks are absent. In this case, the system of microoperations is implemented using PAL macrocells too. The same effectiveness of proposed methods should be tested for both cases of FPGA with embedded memory blocks and for CPLD CoolRunner based on PLA technology. The proposed methods should be modified to meet the specific requirements of these chips.

One of the very important problems connected with FPGA-based design is reducing the hardware amount in implemented circuits. In this paper, we discuss the implementation of Mealy finite state machines (FSMs) by circuits consisting of look-up tables (LUT). A method is proposed to reduce the LUT count of three-block circuits of Mealy FSMs. The method is based on finding a partition of set of internal states by classes of compatible states. To reduce the LUT count, we propose a special kind of state code, named complex state codes. The complex codes include two parts. The first part includes the binary codes of a state as the element of some partition class. The second part consists of the code of corresponding partition class. Using complex state codes allows obtaining FPGA-based FSM circuits with exactly four logic blocks. If some conditions hold, then any FSM function from the first and second blocks is implemented by a single LUT. The third level is represented as a network of multiplexers. These multiplexers generate either additional variable encoding collections of outputs or input memory functions. The fourth level generates FSM outputs. An example of synthesis and experimental results is shown and discussed. The experiments prove that the proposed approach allows reducing hardware compared to such methods as auto and one-hot of Vivado, JEDI. Further, the proposed approach produces circuits with fewer LUTs than for three-level Mealy FSMs based on joint use of several methods of structural decomposition. The experiments show that our approach allows reducing the LUT counts on average from 11 to 77 percent. As the complexity of an FSM increases, the gain from the application of the proposed method grows; the same is true for both the FSM performance and power consumption.

A method is proposed for reducing the number of LUTs in the circuit of a microprogrammed Mealy FSM implemented in a basis of FPGA. The method is based on elimination of some elements from the sets of microoperations for their implementation by EMB. This approach reduces logic levels and interconnections for a circuit implemented with LUTs. An algorithm is proposed for searching for a partition of the set of microoperations. An example of synthesis is given as well as results of the investigations.

Almost any digital system includes sequential blocks which can be represented using a model of finite state machine (FSM). It is very important to improve such characteristics of FSM circuits as the number of logic elements, operating frequency and consumed energy. The paper proposes a novel design method targeting a decrease in the number of look-up table (LUT) elements in logic circuits of FPGA-based Moore FSMs. The method is based on using two sets of variables for encoding the collections of outputs. It results in a partition of the set of outputs by two blocks. The outputs from the first block depend on state variables, the outputs from the second block on additional variables. A method is proposed for splitting the set of outputs. The conditions for using the proposed method are given. An example of synthesis is shown. The results of experiments with standard benchmarks are discussed. The experiments outcomes show that the proposed approach allows diminishing the number of LUTs and consumed energy. Also, it leads to an increase in the operating frequency. The method targets rather complex FSMs when the number of state variables exceeds the number of LUT's inputs.

Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed approach leads to LUT-based Mealy FSM circuits having two levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. The proposed method is illustrated by an example of synthesis. The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based circuits with significantly higher operating frequency than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, twofold state assignment). The performance is increased by an average of 15.9 to 25.49 percent. These improvements are accompanied by a small growth of the numbers of LUTs compared with circuits based on twofold state assignment. Our approach provides the best area-time products compared with other investigated methods. The advantages of the proposed approach increase as the number of FSM inputs and states increases.

A method is proposed for optimizing circuits of sequential devices which are used in cyber-physical systems (CPSs) implemented using field programmable gate arrays (FPGAs). The optimizing hardware is a very important problem connected with implementing digital parts of CPSs. In this article, we discuss a case when Mealy finite state machines (FSMs) represent behaviour of sequential devices. The proposed method is aimed at optimization of FSM circuits implemented with look-up table (LUT) elements of FPGA chip. The method aims to reduce the LUT count of Mealy FSMs with extended state codes. The method is based on finding a partition of the set of internal states by classes of compatible states. To reduce LUT count, we propose a special kind of state codes named composite state codes. The composite codes include two parts. The first part includes the binary codes of states as elements of some partition class. The second part consists of the code of corresponding partition class. Using composite state codes allows us to obtain FPGA-based FSM circuits with exactly two levels of logic. If some conditions hold, then any FSM function from the first level is implemented by a single LUT. The second level is represented as a network of multiplexers. Each multiplexer generates either an FSM output or input memory function. An example of synthesis is shown. The experiments prove that the proposed approach allows us to reduce hardware compared with two methods from Vivado, JEDI-based FSMs, and extended state assignment. Depending on the complexity of an FSM, the LUT count is reduced on average from 15.46 to 68.59 percent. The advantages of the proposed approach grow with the growth of FSM complexness. An additional positive effect of the proposed method is a decrease in the latency time.

Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper proposes a novel design method optimizing LUT counts of LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the replacement of FSM inputs and encoding of the collections of outputs. The proposed method results in three-level logic circuits of Mealy FSMs. These circuits have regular systems of interconnections. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to reducing the LUT counts from 12% to 59% in average compared with known methods of synthesis of single-level FSMs. Furthermore, our approach provides better LUT counts as compared to methods of synthesis of two-level FSMs (from 9% to 20%). This gain is accompanied by a small loss of FSM performance.

A method is proposed targeting implementation of FPGA-based Mealy finite state machines. The main goal of the method is a reduction for the number of look-up table (LUT) elements and their levels in FSM logic circuits. To do it, it is necessary to eliminate the direct dependence of input memory functions and FSM output functions on FSM inputs and state variables. The method is based on encoding of the terms corresponding to rows of direct structure tables. In such an approach, only terms depend on FSM inputs and state variables. Other functions depend on variables representing terms. The method belongs to the group of the methods of structural decomposition. The set of terms is divided by classes such that each class corresponds to a single-level LUT-based circuit. An embedded memory block (EMB) generates codes of both classes and terms as elements of these classes. The mutual using LUTs and EMB allows diminishing chip area occupied by FSM circuit (as compared to its LUT-based counterpart). The simple sequential algorithm is proposed for finding the partition of the set of terms by a determined number of classes. The method is based on representation of an FSM by a state transition table. However, it can be used for any known form of FSM specification. The example of synthesis is shown. The efficiency of the proposed method was investigated using a library of standard benchmarks. We compared the proposed with some other known design methods. The investigations show that the proposed method gives better results than other discussed methods. It allows the obtaining of FSM circuits with three levels of logic and regular interconnections.

The Chapter is devoted to the method of mixed encoding of microoperations. The main idea is discussed regarding Mealy FSMs. There is proposed a formal method allowing a partition of the set of microoperations by two sets. The elements of the first set are encoded by one-hot codes; the elements of the second set are combined into collections of microoperations. Next, the same approaches are discussed for FPGA-based Moore FSMs. There are proposed different structural diagrams of FSMs and corresponding methods of synthesis. The classes of pseudoequivalent states are used to optimize the hardware for Moore FSMs. Further, it is discussed the using proposed methods for combined FSMs. It is shown how to combine different methods of structural decomposition for synthesis of the FPGA-based combined FSMs. At last, it is discussed the mixed encoding of microoperations for LUT-based Mealy FSMs. It is proposed to form the collections of microoperations for elements of both parts of the partition of the set of microoperations.

The chapter provides some basic information. It is shown that control algorithms could be implemented using either microprogram control units or finite state machines. The language of GSA is introduced. Next, the connections are shown with GSAs and state transition graphs of Mealy, Moore and combined FSMs. Classical principles are discussed for logic synthesis of Mealy and Moore FSMs. The FSM logic circuits are implemented with using system gates. The methods of preliminary assessment of hardware amounts are discussed in the last part of the chapter.

The Chapter is devoted to the using linear chains in Mealy FSMs. The known counter-based models of Moore FSMs are discussed together with corresponding design methods. Then, there are proposed models and design methods for counter-based Mealy FSMs. There are proposed synthesis methods based on natural and extended linear chains of states. Next, there is discussed the case of synthesis for regular GSA having a single chain of states. There are proposed different models of counter-based Mealy FSMs based on combining together known and proposed methods of structural decomposition.

The chapter starts from main idea of using the twofold state assignment for optimizing the circuits of FPGA-based Moore FSMs. This method could be combined with refined state assignment leading to minimizing the block of microoperations. It is shown that using classes of pseudoequivalent states could be combined together with the twofold state assignment. There is proposed the formal method of partition of the classes of PES leading to the minimal number of LUT-based blocks in the final FSM circuit. Next, it is shown how to combine the twofold state assignment with encoding of the collections of microoperations. The last part of the chapter is devoted to combining the twofold state assignment with encoding of the fields of compatible microoperations. There are proposed structural diagrams of FSM circuits. The examples of synthesis are given for majority of proposed FSM models.

The chapter deals with analysis of methods of structural decomposition. Main idea of these methods is reduced to diminishing the numbers of literals in systems of Boolean functions due to increasing the number of logic levels in FSM circuits. Methods of state assignment are analysed. Next, the basic features of field programmable gate arrays are discussed. It is shown that embedded memory blocks allow implementing systems of regular Boolean functions. The modern design flow targeting FPGA-based projects is analysed. Different methods of structural decomposition are considered such as the replacement of logical conditions, encoding of the collections of microoperations, encoding of the fields of compatible microoperations and verticalization of initial GSA. The methods basing of classes of pseudoequivalent states are discussed for Moore FSM. The FPGA-based structural diagrams of FSM circuits based on structural decomposition are shown.

A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.

The review is devoted to methods of structural decomposition that are used for optimizing characteristics of circuits of finite state machines (FSMs). These methods are connected with the increasing the number of logic levels in resulting FSM circuits. They can be viewed as an alternative to methods of functional decompositions. The roots of these methods are analysed. It is shown that the first methods of structural decomposition have appeared in 1950s together with microprogram control units. The basic methods of structural decomposition are analysed. They are such methods as the replacement of FSM inputs, encoding collections of FSM outputs, and encoding of terms. It is shown that these methods can be used for any element basis. Additionally, the joint application of different methods is shown. The analysis of change in these methods related to the evolution of the logic elements is performed. The application of these methods for optimizing FPGA- based FSMs is shown. Such new methods as twofold state assignment and mixed encoding of outputs are analysed. Some methods are illustrated with examples of FSM synthesis. Additionally, some experimental results are represented. These results prove that the methods of structural decomposition really improve the characteristics of FSM circuits.

A method is proposed for hardware reduction in FPGA-based Moore FSMs. The method is based on encoding of the terms corresponding to rows of FSM direct structure table. The example of synthesis is given. The application of this method allows reducing the numbers of LUTs in FSM circuits.

A method is proposed for decreasing hardware in FPGA-based Mealy FSMs. The method is based on transforming state codes into class codes. The class codes are generated by the second level of FSM circuit An example of synthesis is given. The results of investigations are shown.

A method is proposed for hardware reduction in FPGA-based Moore FSMs. The method is based on encoding of microoperations. An FSM circuit is implemented using a single EMB and LUTs. The example of synthesis is given.

The article presents a novel method for diminishing the hardware amount in LUT-based Mealy FSMs. The method targets FSMs with state counters. It is based on replacement of FSM inputs by additional variables. To decrease the number of literals, the pairs of inputs are encoded. An example of synthesis is shown.

The chapter is devoted with FPGA-based implementing control algorithms represented using the language of graph-schemes of algorithms. We use models of Mealy and Moore finite state machines (FSM) to design the circuits of control units. We start from single-level FSM circuits implemented using look-up table (LUT) elements and/or embedded memory blocks (EMB). These methods are illustrated using standard benchmark FSMs. Next, the methods of structural decomposition are discussed. We discuss how to reduce hardware using the replacement of logical conditions, encoding the collections of microoperations, encoding the terms, and transformation of objects. We show how to use the pseudoequivalent states for optimization of logic circuits of Moore FSMs. The third section is devoted to hardware reduction of Moore FSMs targeting the replacement of logical conditions. At last, we discuss how to optimize hardware replacing state registers by state counters. The discussed methods target control units based on models of Moore FSMs.

The chapter deals with field-programmable gate arrays (FPGA). The basic stages are shown concerning evolution of programmable logic (from PROMs and PLAs to FPGAs). Next, the evolution of FPGAs is analysed. Three ages of FPGAs are shown. Next, the modern FPGAs produced by Xilinx and Intel (Altera) The last section is devoted to design methods targeting FPGAs. Basing on this information, we show how to execute calculations using digital signal processors, embedded memory blocks, and some components of Zynq 7000 by Xilinx.

Contemporary digital systems include many varying sequential blocks. In the article, we discuss a case when Mealy finite state machines (FSMs) describe the behavior of sequential blocks. In many cases, the performance is the most important characteristic of an FSM circuit. In the article, we propose a method which allows increasing the operating frequency of multi-level look-up table (LUT)-based Mealy FSMs. The main idea of the proposed approach is to use together two methods of structural decomposition. They are: (1) the known method of transformation of codes of collections of outputs into FSM state codes and (2) a new method of extension of state codes. The proposed approach allows producing FPGA-based FSMs having three levels of logic combined through the system of regular interconnections. Each function for every level of logic was implemented using a single LUT. An example of the synthesis of Mealy FSM with the proposed architecture is shown. The effectiveness of the proposed method was confirmed by the results of experimental studies based on standard benchmark FSMs. The research results show that FSM circuits based on the proposed approach have a higher operating frequency than can be obtained using other investigated methods. The maximum operating frequency is improved by an average of 3.18 to 12.57 percent. These improvements are accompanied by a small growth of LUT count.

A method is proposed for hardware reduction in FPGA-based Mealy FSMs. The method is based on encoding of the terms corresponding to rows of FSM direct structure table. The example of synthesis is given. The application of this method allows reducing the numbers of LUTs in FSM circuits.

A method is proposed for reducing hardware in LUT-based Mealy FSMs. The method is based on dividing the set of states by classes. Each state has two codes. This approach is used together with encoding of collections of outputs. An example of synthesis is given, as well as results of investigation.

A method is proposed for decreasing hardware in FPGA-based Mealy FSMs. The method is based on partitioning the set of states by classes. Each state is encoded as an element of the set of states and as an element of some class. An example of synthesis is given, as well as results of investigations.

A method is proposed for implementing Mealy FSMs logic circuits with embedded memory blocks. The method is based on encoding of the rows of FSM structure table and replacement of logical conditions. Example of design and results of investigations are given. Our approach allows diminishing the number of LUTs in the block of RLC due to splitting the initial set of logical conditions. Also it results in the decrease of used EMBs for around 15% of standard benchmarks.

This article is devoted to design of Mealy FSM with FPGAs using embedded memory blocks and look-up table elements. There is presented the state-of-the-art. The method is proposed for design of Mealy FSM logic circuit with embedded memory blocks based on encoding of collections of outputs and replacement of inputs. Example of design and research results are given.

The Chapter provides some basic information. Firstly, the language of GSA is introduced. Next, the connections are shown with GSAs and state transition graphs of both Mealy and Moore FSMs. Classical principles of FSM logic synthesis are discussed. The basic features of FPGA are analyzed. It is shown that embedded memory blocks allow implementing systems of regular Boolean functions. The modern design flow is analyzed targeting FPGA-based projects. Next, the basic problems of FSM design are considered. Different state assignment methods are analyzed, as well as the methods of functional decomposition. Next the issues are discussed connected with implementing FSM logic circuits with EMBs. The peculiarities of hybrid FPGAs are discussed last part of the Chapter.

The Chapter deals with optimization of logic circuits of hybrid FPGA-based Mealy FSMs. First of all, the models with two state registers are discussed. This approach allows removal of direct dependence among logical conditions and output functions of Mealy FSM. Next, the proposed design methods are presented. Some improvements are proposed for further hardware reduction. They are based on the special state assignment and transformation of state codes. The proposed methods target joint using such blocks as LUTs, PLAs and EMBs in FSM circuits. The models are discussed based on the principle of object transformation. The last part of the chapter is connected with design methods connected with the object transformation.

A design method is proposed for HFPGA-based Mealy FSMs. The method is based on transformation of collections of output functions into state variables. It allows diminishing the number of LUTs in FSM circuits in comparison with known method. There is an example of design shown in the article.

A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with CPLDs. The method is based on the idea of code sharing. The main difference from already known methods is that the counter increases its content during conditional and unconditional transitions. An example of application of proposed method is given.

A method is proposed for designing LUT-based Moore FSMs. The method is based on splitting the set of classes of pseudoequivalent states. There are given example of design and results of investigations. The method allows obtaining FSM logic circuits having less amount of LUTs than known from literature methods.

In this paper results of research of hardware amount in the logic circuit of the finite state machine (FSM) with datapath of transitions are shown. A research method is reduced to simulating structural blocks of the FSM using VHDL. There is investigated the efficiency of the FSM with datapath of transitions in comparison to the FSM with canonic structure.

A method is proposed targeting the decrease of the number of look-up tables (LUTs) in logic circuits of field programmable gate arrays (FPGA)-based Mealy finite state machines. The method is based on constructing a partition for the set of output variables. It diminishes the number of additional variables encoding the collections of output variables (COVs). A formal method is proposed for finding the partition. An example of synthesis is given, as well as the results of investigations. The investigations were conducted for standard benchmarks.

A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocells, and existence of free outputs of embedded memory block in CPLD chips. An example of applying the method is given. It is shown that the method reduces hardware expenses to 30%.

A method is proposed allowing implementing Mealy FSM logic circuits with embedded memory blocks of FPGA chips. The method is based on transformation of FSM structure table and replacement of some logical conditions. Example of design and results of investigations are given.

A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on replacement of the state register by a state counter. The main di_erence form already known methods is that the counter increases its state during conditional and unconditional transitions. An example of application of proposed methods is given.

This chapter deals with design of Mealy FSMs based on using embedded memory blocks. The methods of trivial EMB-based implementation of logic circuits of Mealy FSMs are discussed. In this case, only one EMB is enough for implementing the circuit. Next, the optimization methods are discussed based on encoding of the collections of microoperations and replacement of logical conditions. Also, the methods are discussed based on encoding of the rows of FSM structure table. All these methods lead to two-level models of Mealy FSMs. Next, these methods are combined together for further optimizing the hardware amount in FSM logic circuits. The last section considers different methods proposed for diminishing the hardware amount in LUTer implementing the block of replacement of logical conditions. The Chapter includes a lot of tables with results of investigations of proposed methods for the standard benchmarks.

The chapter deals with design of Moore FSMs based on using embedded memory blocks. The methods of trivial EMB-based implementation of logic circuits of Moore FSMs are discussed. In this case, only a single EMB is enough for implementing the logic circuit. Next, the optimization methods are discussed based on the structural decomposition leading to two-level models of FSMs. It is shown how to use the classes of PES for decreasing the number of EMBs in the final circuit. The last section considers different methods proposed for diminishing the hardware amount in LUTer implementing the block of replacement of logical conditions. It is shown that at least 17 different models can be used for optimizing the LUTer.

The chapter is devoted to application of field programmable gate arrays (FPGA) in the design of logic circuits of FSMs. The general characteristic of FPGA is given. The methods are shown used for the trivial implementation (without the hardware reduction) of FSM’s logic circuits. The main methods of state assignment are discussed in details. At last, there are discussed the methods of hardware reduction for FPGA-based FSMs.

A method is proposed for optimization of hardware expenditures for the implementation of Moore automatons (Moore FSMs) in CPLDs. The method lies in using several sources of codes of classes of pseudo-equivalent states, which is possible owing to a wide fan-in of PAL macrocells. The proposed method generates five new circuit models of a Moore automaton. A method of synthesis of a model with three sources of codes is proposed, and an example of its application is presented.

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSMOptimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.

A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on the idea of code sharing. The main difference from already known methods is that the counter increases its content during conditional and unconditional transitions. An example of application of proposed method is given.

A method is proposed allowing implementing logic circuit of Moore FSM with embedded memory blocks of FPGA chips. The method is based on replacement of some part of the set of logical conditions by additional variables. It results in diminishing for the number of LUTs in the multiplexer used for replacement of logical conditions. An example of proposed design methods application is given.

A method for reducing the number of LUT elements in the circuit of FPGA-based Moore FSM is proposed. The method is based on using two sources of codes of pseudoequivalent states. It allows reducing the number of terms in systems of input memory functions up to this value for equivalent Mealy FSM. The system of microoperations is implemented using embedded memory blocks.

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

The proposed method is targeted on reduction of hardware amount in logic circuit of Moore finite-state machine implemented with programmable logic arrays (PLA). The method is based on using more than minimal amount of variables in codes of FSM internal states. The method includes two stages of state encoding. The second stage is connected with recoding of states inside each class of pseudoequivalent states.

A method is proposed allowing implementing logic circuit of Moore FSM with embedded memory block of FPGA chips. The method is based on replacement some part of the set of logical conditions by additional variables. It results in diminishing for the number of LUTs in the multiplexer used for replacement of logical conditions. An example of proposed design methods application is given.