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A high current, low voltage, single sided MOSFET device has been designed and experimentally verified. The device is based on a die fabricated in standard CMOS and a special package based on PCB technique fabricated in a standard PCB process. The transistor, its special package and its mounting on a mother board are carefully analyzed through simulation. The experimental verification indicates an on-resistance less than 0.5mohm, corresponding to a specific on-resistance of 6.7mohm-mm2.

With the advent of Internet of Things (IoT) it has become clear that radio-frequency (RF) designers have to be aware of power constraints, e.g., in the design of simplistic ultra-low power receivers often used as wake-up radios (WuRs). The objective of this work, one of the first systematic studies of power bounds for RF-systems, is to provide an overview and intuitive feel for how power consumption and sensitivity relates for low-power receivers. This was done by setting up basic circuit schematics for different radio receiver architectures to find analytical expressions for their output signal-to-noise ratio including power consumption, bandwidth, sensitivity, and carrier frequency. The analytical expressions and optimizations of the circuits give us relations between dc-energy-per-bit and receiver sensitivity, which can be compared to recent published low-power receivers. The parameter set used in the analysis is meant to reflect typical values for an integrated 90 nm complementary metal-oxide-semiconductor fabrication processes, and typical small sized RF lumped components.

An edge-on silicon strip detector designed for photon-counting spectral computed tomography (CT) is presented. Progress on the development of an application specific integrated circuit (ASIC) to pr ...

A simulation technique is developed in TCAD to study the non-linear behavior of RF power transistor. The technique is based on semiconductor transport equations to swot up the overall non-linearity’s occurring in RF power transistor. Computational load-pull simulation technique (CLP) developed in our group, is further extended to study the non-linear effects inside the transistor structure by conventional two-tone RF signals, and initial simulations were done in time domain. The technique is helpful to detect, understand the phenomena and its mechanism which can be resolved and improve the transistor performance. By this technique, the third order intermodulation distortion (IMD3) was observed at different power levels. The technique was successfully implemented on a laterally-diffused field effect transistor (LDMOS). The value of IMD3 obtained is −22 dBc at 1-dB compression point (P 1 dB) while at 10 dB back off the value increases to −36 dBc. Simulation results were experimentally verified by fabricating a power amplifier with the similar LDMOS transistor.

For PC DRAM memory buses, the number of slots per channel have been decreased as signal frequencies increase. This limits the data capacity per channel. In this paper, we show that the slot reduction is not due to fundamental limits of the channel structure but due to signaling schemes. An equalization scheme is presented which enables higher bit-rates with minimum modification of bus structure and memory circuits. The circuitry added to the host side of the bus has reasonable complexity and features very low latency. Measurements of memory-to-host transmissions over a four-drop-bus at 2.6 Gb/s using a 0.13 mum CMOS test-circuit is presented.

Si-LDMOS transistor is studied by TCAD simulation for improved RF performance. In LDMOS structure, a low-doped reduced surface field (RESURF) region is used to obtain high breakdown voltage, but it reduces the transistor RF performance due to high on-resistance. The interface charges between oxide and the RESURF region are studied and found to have a strong impact on the transistor performance both in DC and RF. The presence of excess interface state charges at the RESURF region results not only higher DC drain current but also improved RF performance in terms of power, gain and efficiency. The most important achievement is the enhancement of operating frequency and RF output power is obtained well above 1 W/mm up to 4 GHz.

The switching behavior of a previously fabricated and tested SiC transistor is studied in Class-C amplifier in TCAD simulation. The transistor is simulated for pulse input signals in Class-C power ...

Power consumption of analog systems is poorly understood today, in contrast to the very well developed analysis of digital power consumption. We show that there is good opportunity to develop also the analog power understanding to a similar level as the digital. Such an understanding will have a large impact in the design of future electronic systems, where low power consumption will be crucial. Eventually we may reach a power centric analog design methodology.

A description of a new facility for X-ray absorption spectroscopy at the materials science beamline, I811, at MAX-lab synchrotron source, Lund, Sweden, is given. The beamline is based on a superconducting multipole wiggler source inserted in a straight section of the 1.5 GeV MAX-II ring. X-rays in the energy range 2.4-12 keV are extracted by a standard optical scheme consisting of a vertical collimating first mirror, double-crystal monochromator, and a second vertically focusing mirror. The second monochromator crystal provides sagittal focusing. The total flux impinging on the sample at 9 keV is 5 x 10(11) photons s(-1), for a minimum beam spot of 0.5 mm x 0.5 mm. The beamline has facilities for experiments in transmission, fluorescence and total-electron-yield mode and experiments have been performed by international research groups on a wide range of materials, such as dilute systems with metal concentrations below 10 p.p.m.

Models of electrical interconnects, including inductance and skin effect, are reviewed. The models are used for estimating the performance of electrical interconnects, particularly related to delays, data rates, and power consumption for off-chip and on-chip interconnects and for clock distribution. It is demonstrated that correctly utilized, electrical interconnects do not severely limit chip or circuit board capacity. Delays, data rates, and power consumption of electrical interconnects within a circuit board are acceptable and superior to optical alternatives.

Ibis work deals with silicon carbide (SiC) metal semieonduetor field effect transistors (MESFETs) and microwave amplifiers using them. The wide bandgap (WBG) semiconductors silicon carbide and gallium nitride have a large potential for microwave power generation. The high power density combined with the comparably high impedance attainable by devices in these materials also offers new possibilities for wideband high power microwave systems. To realise these possibilities we need transistors that are well understood and optimised and amplifier designs that take advantage of the broadband possibilities offered by the transistors. We have developed and used physical drift-diffusion simulation models for SiC MESFETs. The simulation results showed a large influence of the doping and thickness of the channel and buffer layers, and the properties of the semi-insulating substrate on the DC and small signal device performance. A comparison between the physical simulations and measured device characteristics has also been carried out. A novel and efficient way to extend the physical simulations to the large signal high frequency domain has been developed. The method was used to investigate experimentally detected problems in the dynamies of the transistors during large signal operation and to further optimise the device structure. In this work a number of broadband SiC MESFET amplifiers were designed, fabricated and characterized. The packaging and charaeterisation of transistors is described and the design and characterisation of the amplifiers are presented. A 100-500 MHz amplifier showed a measured output power above 20 W and gain >15 dB across the band and a peak power of 26 W at 400 MHz, corresponding to a power density of 5.2 W/mm, with an associated power added efficiency (PAE) of 46 %. A 0.8-2 GHz feedback amplifier showed a measured output power above 5 W, gain >7 dB and PAE above 15 % across the band. A two stage 2.8-3.3 GHz amplifier had a maximum measured output power of 12.6 W with 22 dB gain and 9% PAE measured at 2.8 GHz. These results clearly show that SiC devices have a large potential for microwave power amplifiers in general and broadband amplifiers in particular.

We present a theory for metastability error power in Successive Approximation A/D converters. The traditional measure, BER, does not account for the error influence on signal quality, only the error rate. The metastability error is instead compared with noise, and a Signal-to-Metastability-error-Ratio, SMR, is suggested as a new measure. Suppressing SMR below SNR imposes a gain requirement on the comparator.

The main idea of this paper is to compare the readout architectures for uncooled microbolometer focal plane detector arrays with respect to the detector and readout circuit noise. The comparison is done keeping the total power consumption of all architectures constant. Three CMOS readout architectures with different degree of parallelism are described in this paper: pixelwise, columnwise and serial. The noise model of the readout circuit is given. Also, the optimization for the lowest NETD (noise equivalent temperature difference) and estimation of the self-heating effect is presented.

An analytical delay model of a uniform wire and driver, based on a combination of a switch-level model and Elmore delay is developed for the on-chip interconnections. The model is utilized for the optimization of delay, power, area, or combinations thereof, subject to different constraints. A linear relation between wire width and transistor widths is proposed, which leads to closed-form solutions to the optimization problems. These solutions are valid also for a multistage uniform wire and driver and are easily used in practical design. The solutions are compared to SPICE simulated results, using practical process parameters. Results show that the root of mean square (rms) errors of delay and power between SPICE simulation and the proposed method are around 3%.

A number of recently reported CMOS line receivers and downconversion mixers are based on sampling. A key component in these designs is the NMOS sampling switch. It can sample a very high bandwidth signal, several GHz for a 0.8-/spl mu/m transistor. We present an expression for the aperture time for an NMOS switch when the input has low swing. The switch can, under this condition, be modeled as a device that determines a weighted average over time of the input signal. The weight function is derived. The aperture time function shows that the maximum theoretical time resolution for a switch in 0.8-/spl mu/m standard CMOS is 21 ps (/spl sim/48 Gb/s). SPICE simulations agree with the theory. Transient two-dimensional (2-D) device simulations do not contradict the predicted results. Experiments on a switch made in a 0.8-/spl mu/m standard CMOS process show successful sampling of every thirty second bit of a 5-Gb/s data stream.

New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.

Data-rate of wireless links are increasing fast, particularly when new carrier bands with very high bandwidth becomes available. Utilizing the full bandwidth for a single carrier facilitates very large baud-rates. When the baud-rates approaches or exceeds Gbaud, the implementation of the digital baseband is no longer a simple extension of existing methods. In the present paper we propose a resource efficient implementation of digital baseband for multi-Gbaud rates in a standard FPGA utilizing Xilinx Simulink-based System generator design and verification tool.

This brief presents the design and analysis of a 5.5-V class-D stage used in two fully integrated watt-level, +32.0 and + 29.7 dBm, outphasing RF power amplifiers (PAs) in standard 130- and 65-nm CMOS technologies. The class-D stage utilizes a cascode configuration, driven by an ac-coupled low-voltage driver, to allow a 5.5-V supply in the 1.2-/2.5-V technologies without excessive device voltage stress. The rms electric fields (E) across the gate oxides and the optimal bias point, where the voltage stress is equally divided between the transistors, are computed. At the optimal bias point, the rms E, the power dissipation of the parasitic drain capacitance of the common-source transistors, and the equivalent on-resistances are reduced by approximately 25%, 50%, and 25%, compared to a conventional cascode (inverter) stage. To the authors' best knowledge, the class-D PAs presented are among the first fully integrated CMOS outphasing PAs reaching +30 dBm and demonstrate state-of-the-art output power and bandwidth.

Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits. >

A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-/spl mu/m CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm/sup 2/ and the core of the parallel ADC array occupies an area of 2.7/spl times/3.3 mm/sup 2/. The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively. >

This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +32dBm at 1.85 GHz in a standard 130nm CMOS technology. The PA utilizes four on-chip transformers to combine the outputs of eight Class-D stages. The Class-D stages utilize a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V 130nm process without excessive device voltage stress. Spectral and modulation requirements were met when a WCDMA and an LTE signal (20 MHz, 16-QAM) were applied to the outphasing PA. At +28.0 dBm channel power for the WCDMA signal, the measured ACLR at 5 MHz and 10 MHz offset were −38.7 dBc and −47.0 dBc, respectively. At +24.9 dBm channel power for the LTE signal, the measured ACLR at 20MHz offset was −34.9 dBc. To the authors' best knowledge, the PA presented in this work has a 3.9 dB higher output power compared to published CMOS Class-D RF PAs.

Power consumption is an important limitation to analog-to-digital converters. The objective of this paper is to estimate a lower bound to the power consumption of successive approximation analog-to-digital converters. This is an extension of our previous work which was limited to pipelined and flash architectures. We find that the power consumption in our case is bounded by capacitor mismatch or thermal noise at high resolution and by digital switching power at low resolution. We also evaluate our methods and the estimated lower bound is compatible with experimental data.

A new silicon strip detector with sub-millimeter pixel size operated in single photon-counting mode has been developed for use in spectral computed tomography (CT). An ultra fast application specif ...

This paper presents analytical expressions for the sensitivity of a low power envelope detector driven by a weak RF signal in the presence of a blocking signal. The envelope detector has been proposed for low power Wake-Up radios in applications such as RFID and wireless sensor systems. The theoretical results are verified with simulations of a modern short channel MOS transistor in a commonly used circuit topology. A discussion around a tutorial example of a radio frontend, consisting of an LNA and a detector, is presented. It is shown that the sensitivity of a low power envelope detector can reach -62 dBm with a low power LNA and in presence of a CW blocker. © 2011 IEEE.

We compare quantum interference devices, exemplified by a resonant tunnel transistor, an Aharonov–Bohm interferometer, and a Y‐branch switch, to field‐effect transistors regarding their capability to reach fundamentally limited switch energies as well as their normalized transconductance. The resonant tunnel transistor is found to behave similarly to the field‐effect transistor (FET). The Aharonov–Bohm interferometer is essentially equivalent to a single‐mode Y‐branch switch, while the Y branch has an advantage in allowing multimode operation. The normalized transconductance of these two devices can be an order of magnitude larger than for a FET.

We have constructed an addressable 256 × 256 photodiode sensor array together with an 8-bit ADC (analog-to-digital converter) on the same chip. Such a digital camera is easy to connect to a computer where also the flexibility of the computer can be used to control the camera output. The sensor has been constructed in two versions. The first version was implemented with a 256-column parallel-bit-slice image processor on the same die in a commercial project and the second as a separate addressable digital image sensor. The sensor was functionally fabricated using 1.6 µm design rules in a 1.2 µm CMOS process where it required a total area of 96 mm2.

In this paper fabrication and characterization of Schottky gate planar field-effect transistors using poly(3-alkylthiophene) as an active semiconductor region are reported. This is the first time that planar MESFET transistors utilizing a polymer semiconductor have been fabricated and measured. Aluminum metal is used for the rectifying contact and two gold electrodes are constructed as source and drain. From the MESFET characteristic the channel carrier mobility is evaluated as 10 −5 cm 2 V −1 s −s , which is one order of magnitude larger than a MOSFET utilizing the same polymer.

A personal description of the history of gas-sensitive field-effect devices is given. It is shown how the originally described palladium-gate metal-oxide-semiconductor field-effect transistor has developed into sensing surfaces enabling the production of response images to odours. Images obtained for the odour from different cheeses are presented as examples of such ‘artificial olfactory images’.

To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) IC using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2- mu m CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results in an output frequency tuning range from DC up to 350 MHz with a 41.7-Hz tuning resolution and a peak-to-peak phase jitter of 1.4 ns. The 1.7-mm*1.7-mm IC dissipates 850 mW with a single 5-V supply, which is substantially lower than similar ECL and GaAs devices. >

This paper presents a high-speed single channel pipeline analog-to-digital converter sampling at 2.4 GS/s which, to the authors' best knowledge, is the fastest reported for pipeline converters. The use of a time-borrowing clocking scheme eliminates the comparator latency from the critical path and together with the use of fast open-loop current-mode amplifiers the high sample rate is achieved. Implemented in a 65nm general purpose CMOS technology the effective number of bits is above 4.7 in the Nyquist band, being 5.4 and 4.9 at DC and Nyquist respectively. This shows that very fast pipeline ADCs are possible to implement as key building blocks in interleaved structures.

Key blocker requirements of software defined radio receivers are identified from first principles. Three challenges are derived from these requirements, the need for passive filter banks or tunable passive filters, a very highly linear RF front-end and a high performance analog-to-digital converter. Each of these challenges is analyzed regarding possible solutions in the context of state-of-the art technology. The original publication is available at www.springerlink.com:Christer Svensson, The blocker challenge when implementing software defined radio receiver RF frontends, 2010, Analog Integrated Circuits and Signal Processing, (64), 2, 81-89.http://dx.doi.org/10.1007/s10470-009-9446-zCopyright: Springer Science Business Mediahttp://www.springerlink.com/

Two of the main consequences of advances in VLSI technologies are increased cost of design and wiring. In CMOS synchronous systems, this cost is partly due to tedious synchronization of different clock phases and routing of these clock signals. Here, a single-phase clocking scheme that makes the design very compact and simple is described. It is shown that this scheme is general, simple, and safe. It provides a structure that can contain all components of a digital VLSI system, including static, dynamic, and precharged logic as well as memories and PLAs. Clock and data signals are presented in a clean way that makes VLSI circuits and systems well suited for design compilation. >

In this paper, the proposed technique can be used to study the internal device non-linearity by TCAD device level simulations to enhance the device performance by physical structure/doping.

"Radio Design in Nanometer Technologies" addresses current trends and future directions in radio design for wireless applications. As radio transceivers constitute the major bottleneck in a wireless chipset in terms of power consumption and die size, the radio must be designed in the context of the entire system, end to end. Therefore the book will address wireless systems as well as the DSP parts before it gets into coverage of radio design issues. To that end, the book contains three parts: Part 1 is a general part discussing current and future wireless networks, chipset evolution over the past decade and ending with a discussion on radio requirements for software defined radio(SDR). Part 2 will focus on the digital baseband of a wireless chip set, flexible DSP cores for multi-standard wireless platforms and system-on-chip SoC implementation and design flow issues. Part 3 will be devoted to radio design issues starting at the transceiver level and going down to discuss critical issues facing design of future multi band multi standard radios for emerging wireless standards such as UMTS, WiMaX, MIMO and WLAN in a way that is consistent with the prevailing vision of SDR. As such, the book is the first volume that looks at the integrated radio design problem as a 'piece of a big puzzle', namely the entire chipset or single chip that builds an entire wireless system. This is the only way to successfully design radios to meet the stringent demands of today's increasingly complex wireless systems

We designed simulated and optimized laterally diffused Si-MOSFET (LDMOS) transistors in Sentaurus TCAD software. By introducing excess interface charge density at the RESURF (reduced surface field) region, a power density 1.5 W/mm with a PAE (power added efficiency) of 45% at 3 GHz were obtained. The gain was 20.3 dB. These results show the enhancement in RF performance by introducing excess interface charge density at the RESURF region.

We successfully show the practical feasibility of a purely electrical global on-chip communication link with near velocity-of-light delay. The implemented high-speed link comprises a 5mm long, fully shielded, repeaterless, on-chip global bus reaching 3Gb/s/wire in a standard 0.18/spl mu/m CMOS process. Transmission-line-style interconnects are achieved by routing signal wires in the thicker top metal M6 layer and utilizing a metal M4 ground return plane to realize near velocity-of-light data transmission. The nominal wire delay is measured to 52.8ps corresponding to 32% of the velocity of light in vacuum. A 22% measured worst-case crosstalk induced delay variation is dominated by inductive coupling.

The paper presents a fast and accurate high-level model of a pipelined analog-to-digital converter implemented in MATLAB. Mechanisms causing dynamic errors, such as the settling time of a slew-rate-limited amplifier, are analyzed and parameters to model these identified. All parameters are associated with actual physical properties and all simulations are validated by comparison to measured data in both time and frequency domains.

In this paper, measurements of drain thermal noise for three NMOS devices with different channel lengths was carried out. The three NMOS devices were all implemented in a 0.18 μm CMOS technology, with channel lengths 0.18. 0.36, and 0.72 μm, respectively. The result was then compared with simulated data using the BSIM3- model and parameters provided by the vendor Large discrepancies between measurements and simulations were observed. This work was done in order to understand how to utilize transistor length as a design parameter to achieve optimal noise gures for wideband LNAs in deep submicron technologies.

A very flexible multiphase clock generation circuit is proposed. It is aimed for applications where very accurate phase shifts and low jitter is required, such as time-interleaved samplers and multistandard radio receivers. Robustness to supply voltage variation for phase shifts and jitter performance is demonstrated with simulations as well as measurements.

A decision feedback equalizer (DFE), well suited for implementation in standard CMOS and capable of recovering data sent over a multi-drop memory bus at several Gb/s per wire, is presented. The structure features low latency and permits easy switching of filter coefficient sets, which enables the bus host to receive data from different slaves. Results from near-hardware simulations of 3 Gb/s per wire transmissions over a four tap standard DDR memory bus are presented.

In this paper we present and carefully analyze a transition energy cost model aimed for efficient power estimation of performance critical deep submicron buses. We derive an accurate transition energy cost matrix, scalable to buses of arbitrary bit width, which includes properties that closer capture effects present in high-performance VLSI buses. The proposed energy model is verified against Spectre simulations of an implementable bus, including drivers. The average discrepancy between results from Spectre and the suggested model is limited to 4.5% when fringing effects of edge wires is neglected. The proposed energy model can account for effects that limit potential energy savings from bus transition coding.

A new beamline, Cassiopeia, at MAX II is about to come into operation. It consists of an energy‐tunable station and four side stations intended for macromolecular crystallography. The X‐ray source is a 3.5 T superconducting multipole wiggler installed in the 1.5 GeV MAX II storage ring. The energy‐tunable station use grazing incidence Rh‐coated silicon mirrors and an internally water‐cooled Si(111) double‐crystal monochromator while the four side stations use bent diamond and germanium monochromators and multilayer mirrors. This paper concentrates on the optics design of the energy‐tunable station and also briefly describes other beamline components.

Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. This basic analysis is presented, together with design constraints. We demonstrate a scheme for this, based on the utilization of upper-level metals as transmission lines. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore very high bandwidth in buses of limited width. As an example, we demonstrate a 320μm wide bus with a capacity of 160Gb/s in a nearly standard 0.18μm process.

A methodology to implement fully programmable narrow-band FIR filters with switched capacitor (SC) technique is presented. The SC implementation, which offers a fixed order of complexity, is suitable for high-order FIR filter realizations followed by decimation. The filter performance and the requirements are analyzed.

A mixed analog/digital (MAD) multiply-accumulate (MAC) unit, implemented with switched-capacitor (SC) technique is presented. The MAC unit consist of a programmable capacitor array (PCA) for coefficient representation, and an integrator for accumulation. A coefficient compensation technique to neutralize the non-ideal MAC properties due to finite opamp gain is introduced. The MAD-MAC unit is a new concept for effective mapping of signal processing tasks on SC technique; in particular high-order fully programmable narrow-band FIR filter applications. The utilization of the MAD-MAC unit concept is shown with a simulation of a decimated 400-tap narrow-band FIR filter.

In high speed CMOS clock buffer design, the duty cycle of clock is liable to be influenced when the clock passes through a multistage buffer because the circuit is not strictly digital. Signal quality degradation is caused by temperature and process deviation. In this paper, we address a pulse width control loop (PWCL), to get a required pulse width. To investigate the loop stability, a linearized small signal analysis model is used. Results of SPICE simulation show that the pulse width can be well controlled if the loop parameters are properly chosen. The pulse width can be easily adjusted to a desired value by changing the ratio of transistor sizes in the current mirror of the charge pump.

Previous approaches to video-rate CMOS A/D (analog-to-digital) converters are based on fully-parallel, subrange, or pipeline architectures. The authors describe a 5-MHz 8-bit experimental design of a successive-approximation A/D converter using 3- mu m CMOS technology. Since neither capacitors nor a resistor string are needed in the current-switching technique, a conventional digital technology can be used. The use of the CMOS current-switch technique makes bipolar input signals possible. A circuit realization of a high-speed successive approximation register is also presented, using a single phase clock. The proposed technique is compatible with digital VLSI technology. >

The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, called SLOP (switch-level optimization), is based on a switch-level simulation program for CMOS circuits. Consequently, the results are always verified by simulation. It gives the delay-area curve and the final sizes of each transistor according to the maximum width limitation specified by the user. Experimental results are presented. The typical improvement in circuit speed is 60%-90% with an area increase of 80%-110%. >

In the new TSPC flipflops, speed and power bottlenecks of the original TSPC and the existing differential flipflops are removed. Delays are reduced by factors of 2.0, 2.2 and 2.4 for the dynamic, the semi-static and the fully-static flipflops, respectively. In the same time, power consumptions are also reduced so the power-delay products are reduced by factors of 3.5, 3.4 and 6.5 for A=0.25. Moreover, the clock loads are minimized, the circuits are completely non-precharged and the logic-related transistors are purely n-type in both n-latches and p-latches. It means that all logic operations can be done completely by n-transistors, which gives a very large speed advantage to this kind of CMOS circuits.

This paper presents a 65-MHz clock rate and 32-times oversampling digital-to-analog sigma-delta converter in a standard 1 /spl mu/m CMOS technology. The modulator have been designed for large bandwidth, large input range and low tonality. These demands have been met by a 6th-order lossy modulator. To utilize the modulator bandwidth and relax the reconstruction filter requirements a high-order FIR-filter have been used that combines D/A-conversion with a sharp transition-band filtering. For the application novel use of a interpolated half-band FIR-filter gives a low number of nonzero tap coefficients compared to earlier reported designs. >