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Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small residual error signals—this challenge is addressed by the addition of interleaved, offset-canceled deserializing samplers. Clock generation as well as distribution circuits are implemented to complete the receiver frontend. The proposed 65 nm CMOS receiver operates at 60 Gb/s, consuming 173 mW from 1.2 V and 1.0 V supplies. [ABSTRACT FROM PUBLISHER]

Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy–performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal Ion/Ioff and Edyn/Eleak ratios are set only by circuit-level parameters as well as the device transfer characteristic off-state Soff, on -state Son, and effective Seff inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal Edyn/Eleak ratio is approximately (K/\2)(Seff/Soff) - \0.56(Son/Soff) - \0.56, where K ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for Soff, Son, and Seff are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope S is insufficient, since energy dissipation is set mainly by Seff and not by S. Finally, the general shape of the energy–delay curve is also set by these inverse slopes, with its steepness directly proportional to Son/Soff. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology. [ABSTRACT FROM AUTHOR]

This paper describes design techniques to maximize the efficiency and power density of fully integrated switched-capacitor (SC) DC-DC converters. Circuit design methods are proposed to enable simplified gate drivers while supporting multiple topologies (and hence output voltages). These methods are verified by a proof-of-concept converter prototype implemented in 0.374 mm^2 of a 32 nm SOI process. The 32-phase interleaved converter can be configured into three topologies to support output voltages of 0.5 V–1.2 V from a 2 V input supply, and achieves 79.76% efficiency at an output power density of 0.86 W/mm ^2. [ABSTRACT FROM PUBLISHER]

Microelectromechanical relays have recently been proposed for ultra-low-power digital logic because their nearly ideal switching behavior can potentially enable reductions in supply voltage (Vdd) and, hence, energy per operation beyond the limits of MOSFETs. Using a calibrated analytical model, a sensitivity-based energy–delay optimization approach is developed in order to establish simple relay design guidelines. It is found that, at the optimal design point, every 2 \times energy increase can be traded off for a \sim\!\!\1.5\times reduction in relay delay. A contact-gap-to-actuation-gap thickness ratio of 0.7–0.8 is shown to result in the most energy-efficient relay operation, implying that pull-in operation is preferred for an energy-efficient relay design. Based on the analytical model and design guidelines, a scaling theory for relays is presented. A scaled relay technology is projected to provide >\10\times energy savings over an equivalent MOSFET technology, for circuits operating at clock frequencies up to \sim100 MHz. [ABSTRACT FROM AUTHOR]

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area. [ABSTRACT FROM AUTHOR]

Multiple-input relays are proposed to enable more compact implementation of digital logic circuits, and the first functional prototypes are presented. A relay with three equally sized input electrodes is demonstrated to perform various three-input logic functions, with a delay that can be well predicted by a lumped-parameter model. Relays with differently sized input electrodes can be used to perform more complex functions. A flash-type analog-to-digital converter is presented as one example. [ABSTRACT FROM PUBLISHER]