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A contact resistance (${R}_{c}$) becomes a major parasitic resistance in highly scaled modern semiconductor devices. A wrap-around contact (WAC) has been suggested as a promising solution to reduce the ${R}_{c}$ , because its contact area is larger than that for the conventional top contact (TC) structure. Therefore, in this article, the electrical and thermal characteristics are widely investigated in vertically stacked gate-all-around (GAA) MOSFET with a WAC by using a 3-D technology computer-aided design (TCAD) simulation. First, compared with the TC, the WAC shows 1.74 times higher ON-state current. It is attributed in part to the low ${R}_{c}$ and in part to the low source–drain resistance (${R}_{\text {SD}}$). Furthermore, thermal resistance (${R}_{\text {th}}$) is also reduced by 9.73% in WAC, which improves self-heating effects (SHEs). Considering the results, it is expected that the WAC structure could be an attractive candidate to simultaneously improve device performance and reliability. [ABSTRACT FROM AUTHOR]

This paper examines a tunnel field-effect transistor (TFET) as a promising device for achieving steeper switching and better electrical performances in low-power operation. It features a double-gate TFET with vertical channel sandwiched by lightly doped Si (VS-TFET). The vertical tunnel junction is employed on the source side for the steeper subthreshold swing (SS) and for the higher ON-current (${I}_{ \mathrm{\scriptscriptstyle ON}}$) by restricting tunnel barrier width. The VS-TFET shows 17-mV/dec minimum SS and ${10}^{ {4}}~{ \mathrm{\scriptstyle ON}}/{ \mathrm{\scriptstyle OFF}}$ current ratio (${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$) for sub-0.7-V gate overdrive. In addition, the VS-TFET shows sub-60-mV/dec SS in a wide range of ${I}_{D}$ regardless of sweep directions. In conclusion, the work presented here demonstrates that the VS-TFET will be one of the most promising candidates for a next-generation low-power device. [ABSTRACT FROM AUTHOR]

In order to verify the effects of localized body doping (LBD) on alternating current switching performances of tunnel FETs (TFETs) with vertical structures, The TFET inverter composed of n-/p-type TFET with the localized p+/n+ body doping is simulated with the help of mixed-mode device and circuit simulations. As a result, falling/rising delay is significantly improved due to the locally high channel-to-drain side energy barrier induced by the LBD. Furthermore, LBD conditions, such as doping concentration, depth, and width, are optimized to maximize the improvement of falling/rising delay. Based on the optimization results, it is found that enough wide doping width and deep depth are inevitable to minimize the drain voltage ( V D )-induced lowering of the locally increased barrier and the increase of ambipolar current and too wide doping width cannot be applied due to the ON-current reduction caused by the degraded controllability of gate voltage on channel similarly to short channel effects. Moreover, the doping width and depth should be adjusted according to LBD concentration. [ABSTRACT FROM PUBLISHER]

A comprehensive study was done regarding stabilities under simultaneous stress of light and negative gate bias ( V\mathrm{ G} )/positive drain bias ( V\mathrm{ D} ) in amorphous hafnium-indium–zinc-oxide thin-film transistors. Negative threshold voltage ( V\mathrm {\mathbf {th}} ) shift was observed in transfer characteristics after the stress. Through the consecutive stresses of ( V\mathrm{G}= -5 V, V\mathrm{D}= 15 V, and V\mathrm{ S}= 0 V) and ( V\mathrm{G}= -5 V, V\mathrm{D}= 0 V, and V\mathrm{S}= 15 V) under light illumination, it is found that the negative V\mathrm {\mathbf {th}} shift is affected only by V\mathbf {G} , because the drain current is determined by source-side energy barrier though drain-side energy band is locally lowered by V\mathrm{D} -induced drain-side trapped holes. Furthermore, the drain-side trapped holes increase ON-current by reducing channel resistance after channel accumulation. Gate-to-drain capacitance ( C\mathrm {\mathbf {GD}} ) was measured before/after the ( V\mathrm{G}= -5 V, V\mathrm{D}= 15 V, and V\mathrm{S}= 0 V) stress to clarify the presence and distribution of the drain-side trapped holes. From C\mathrm {\mathbf {GD}} stretching out after the stress, it is revealed that the trapped holes introduce an additional capacitance by responding to the accumulated electrons and the capacitance is distributed according to the vertical electric field distribution of the stress. [ABSTRACT FROM AUTHOR]

A comprehensive study was done regarding stability under simultaneous stress of light and negative gate dc bias in amorphous hafnium–indium–zinc-oxide ( \alpha -HIZO) thin-film transistors. A negative threshold voltage ( V_{\mathrm{ th}}) shift and an anomalous hump were observed in transfer characteristics after the stress, and it is explained that these phenomena are caused by the hole trapping in the SiO2 gate insulator, not by interface state generation. Furthermore, capacitance–voltage ( C_{G} – VG) measurements were performed with various frequencies to investigate the vertical distribution of the trapped holes in the gate insulator. As a result, the correlation between the vertical location of the trapped holes and the influence on CG – VG characteristics were revealed clearly. First, at the beginning of the stress, photogenerated holes are mainly trapped at the \alpha -HIZO/SiO2 interface and interfacial SiO2 in contact with the interface, which induces the negative V_{\mathrm{ th}} shift. Second, as the stress time increases, the holes start to be trapped in the spatially deeper insulator, which leads to an additional hump in the C_{G}$ – VG characteristics at sufficiently low frequencies. [ABSTRACT FROM AUTHOR]

An L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time. It is more scalable than other vertical-BTBT-based TFET designs and provides more than $1000\times $ higher ON-current ( $I_{{\mathrm{\scriptscriptstyle ON}}} ) than a conventional planar TFET with the same gate overdrive ( V\mathrm{ov} ) of 0.8 V, due to improved subthreshold swing ( S ) and larger tunnel junction area. Its temperature dependence, constant $S$ , and nonlinear output characteristics are discussed. [ABSTRACT FROM AUTHOR]

For the first time, a comprehensive study is done regarding the stability under simultaneous application of light and gate dc bias in amorphous hafnium–indium–zinc–oxide (\alpha-HIZO) thin-film transistors (TFTs). Subthreshold swing (SS) degradation, a negative threshold voltage (Vth) shift, and the occurrence of hump are observed in transfer curves after applying a negative gate bias and light stress. Based on the retention test at room temperature and the hysteresis analysis, it is revealed that all these phenomena result from hole trapping in the gate insulator. Moreover, it is proven that the SS degradation and hump occurrence are mainly attributed to hole trapping in \SiO2 at the edge regions along the channel length/width directions and that a negative Vth shift is derived from hole trapping in the gate insulator far from the \SiO2/\HIZO interface. [ABSTRACT FROM AUTHOR]